Semiconductor device
By setting epitaxial layer regions with different doping concentrations on a semiconductor substrate, and placing field-effect transistors and Schottky diodes in different regions, the problems of on-resistance and leakage current of power semiconductor devices are solved, and performance is improved.
Patent Information
- Application Number
- CN202520113607.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-17
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2035-01-17
AI Technical Summary
How to further reduce the on-resistance and leakage current of power semiconductor devices without increasing the difficulty of the manufacturing process or affecting the electrical performance of other components.
An epitaxial layer region with different doping concentration is formed on a semiconductor substrate, and a field-effect transistor and a Schottky diode are respectively placed in different regions. The on-resistance is reduced by forming the field-effect transistor in the first region of the epitaxial layer, and the leakage current is reduced by forming the Schottky diode in the second region.
It effectively reduces the on-resistance and leakage current of power semiconductor devices, improves overall performance, and avoids increasing the difficulty of the manufacturing process.
Smart Images
Figure CN223829698U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a kind of semiconductor devices, especially a kind of power semiconductor device. BACKGROUND
[0002] Generally speaking, as shown in Figure 3 In power semiconductor devices, a diode (e.g., a Schottky diode) is connected in parallel between the source and drain of a transistor switch to reduce the recovery time of the transistor switch. In addition, to reduce the on-resistance of the power semiconductor device, the on-resistance can be reduced by decreasing the cell pitch of the transistor on one hand. However, as the cell pitch is reduced, the process difficulty is increased and it is difficult to further reduce the cell pitch. On the other hand, the on-resistance of the transistor can also be reduced by providing two epitaxial layers on the substrate, which, however, can cause a large leakage current of other components (e.g., diodes) provided on the substrate. Therefore, how to further reduce the on-resistance of the power semiconductor device without affecting the electrical performance of other components is a problem to be solved at present. SUMMARY
[0003] The utility model provides a kind of semiconductor devices, it has low on-resistance and reduced leakage current.
[0004] The semiconductor device of the utility model includes a semiconductor substrate, an epitaxial layer, a body layer, a source doped region and a first conductive layer. The epitaxial layer is disposed on the semiconductor substrate and has a first conductivity type. The epitaxial layer includes a first region and a second region. The first region includes a first drift region having a first doping concentration and a second drift region having a second doping concentration, wherein the second doping concentration is not equal to the first doping concentration. The second region is adjacent to the first region and includes a third drift region having a third doping concentration, wherein the third doping concentration is equal to the first doping concentration. The body layer is disposed in the second drift region and has a second conductivity type, which is opposite to the first conductivity type. The source doped region is disposed in the body layer and has the first conductivity type. The first conductive layer is disposed on the epitaxial layer and directly contacts a surface of the second region of the epitaxial layer, and is electrically connected with the source doped region.
[0005] In an embodiment of the utility model, the first drift region is located between the semiconductor substrate and the second drift region.
[0006] In an embodiment of the utility model, the epitaxial layer has a plurality of first trenches, and the plurality of first trenches are at least partially located in the second drift region of the first region.
[0007] In an embodiment of the present application, the semiconductor device further includes a first lower gate disposed in the plurality of first trenches.
[0008] In an embodiment of the present application, the semiconductor device further includes a dielectric layer disposed in the plurality of first trenches and between any two of the first upper gate, the first lower gate, and the epitaxial layer.
[0009] In an embodiment of the present application, the source doped region has a fourth doping concentration, and the fourth doping concentration is greater than the second doping concentration.
[0010] In an embodiment of the present application, the semiconductor substrate has a fifth doping concentration, and the fifth doping concentration is greater than the first doping concentration and the second doping concentration.
[0011] In an embodiment of the present application, the first conductive layer further includes a conductive contact extending into the source doped region and the body layer, and the first conductive layer is electrically connected to the body layer through the conductive contact.
[0012] In an embodiment of the present application, the semiconductor device further includes a second conductive layer disposed below the semiconductor substrate.
[0013] In an embodiment of the present application, an interface between the first conductive layer and the third drift region is a Schottky junction.
[0014] Based on the above, the semiconductor device of the present application has the second drift region and the first drift region in the first region of the epitaxial layer, and has the third drift region in the second region of the epitaxial layer. In this way, different components can be disposed in different regions according to different electrical requirements, so as to improve the overall performance of the semiconductor device. For example, a field effect transistor can be located in the first region to help reduce its on-voltage, and a Schottky diode can be located in the second region to help reduce its leakage current.
[0015] In order to make the above features and advantages of the present application more obvious and easy to understand, the following embodiments are described in detail below, and the drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 is a cross-sectional schematic view of a semiconductor device according to the present application;
[0017] Figures 2A to 2E is a cross-sectional schematic view of a manufacturing process of a semiconductor device according to the present application;
[0018] Figure 3is a circuit schematic diagram of a power semiconductor device. DETAILED DESCRIPTION
[0019] Reference will now be made in detail to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings / taken to indicate the same or similar elements.
[0020] In this document, terms such as "comprise", "include", "contain" and "have" are open-ended terms, i.e., meaning "including, but not limited to".
[0021] When using terms such as "first" and "second" to describe elements, they are only used to distinguish the elements, and do not limit the order or importance of the device. Therefore, in some cases, the first element can also be referred to as the second element, and the second element can also be referred to as the first element, which is within the scope of the present application.
[0022] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to the present application.
[0023] Please refer to Figure 1 The semiconductor device 10 includes a semiconductor substrate 100, an epitaxial layer 110, a body layer 116, a source doped region 118, and a first conductive layer 150. The epitaxial layer 110 is disposed on the semiconductor substrate 100 and has a first conductivity type, including a first region R1 and a second region R2. The body layer 116 is disposed in the first region R1 of the epitaxial layer 110 and has a second conductivity type, which is opposite to the first conductivity type. The source doped region 118 is disposed in the body layer 116 and has the first conductivity type. The first conductive layer 150 is disposed on the epitaxial layer 110 and directly contacts a surface of the second region R2 of the epitaxial layer 110, and is electrically connected with the source doped region 118. In some embodiments, the first conductivity type is N-type, and the second conductivity type is P-type, but the present application is not limited thereto. In other embodiments, the first conductivity type can be P-type, and the second conductivity type can be N-type.
[0024] Further, the first region R1 in the epitaxial layer 110 is configured to form a field effect transistor FET, and the second region R2 is configured to form a Schottky barrier diode SBD.
[0025] The first region R1 includes a first drift region 112 having a first doping concentration and a second drift region 114 having a second doping concentration, wherein the second doping concentration is not equal to the first doping concentration. In some embodiments, the second doping concentration can be greater than the first doping concentration to help reduce the on-resistance of the field effect transistor FET located in the first region R1. In some embodiments, the first drift region 112 is located between the semiconductor substrate 100 and the second drift region 114. In other embodiments, the first region R1 can include only the second drift region 114 without the first drift region 112.
[0026] The second region R2 is adjacent to the first region R1 and includes a third drift region 113 having a third doping concentration, wherein the third doping concentration is equal to the first doping concentration. Thus, the third drift region 113 can also be considered as an extension of the first drift region 112 extending into the second region R2, or the first drift region 112 can be considered as an extension of the third drift region 113 extending into the first region R1.
[0027] In some embodiments, the first drift region 112 and the third drift region 113 can be N-type drift regions, and the second drift region 114 can be an N-type drift region.
[0028] In some embodiments, the source doped region 118 has a fourth doping concentration, and the fourth doping concentration is greater than the second doping concentration. In some embodiments, the source doped region 118 can be an N+ type doped region, and the body layer 116 can be a P-type.
[0029] In some embodiments, the semiconductor substrate 100 can include a silicon substrate or other suitable semiconductor substrate. In some embodiments, the semiconductor substrate 100 has a first conductivity type. In some embodiments, the semiconductor substrate 100 has a fifth doping concentration, and the fifth doping concentration is greater than the first doping concentration and the second doping concentration. In some embodiments, the semiconductor substrate 100 can be an N+ type semiconductor substrate.
[0030] In some embodiments, the epitaxial layer 110 has a plurality of trenches, such as a plurality of first trenches T1 and a plurality of second trenches T2. The plurality of first trenches T1 is located in the first region R1, and the plurality of second trenches T2 is located in the second region R2. In some embodiments, the first trenches T1 are configured to form gates G of the field effect transistor FET, and the second trenches T2 are configured to form anodes E1 of the Schottky diode SBD.
[0031] In some embodiments, the first trench T1 is at least partially located in the second drift region 114, that is, the gate of the field effect transistor FET is at least partially surrounded by the second drift region 114. In some embodiments, the depth of the second drift region 114 can exceed the bottom of the first trench T1, that is, the depth H2 of the second drift region 114 is greater than the depth H1 of the first trench T1, such that the second drift region 114 surrounds the entire first trench T1. However, the present disclosure is not limited thereto. In other embodiments, the depth H2 of the second drift region 114 can also be less than or equal to the depth H1 of the first trench T1.
[0032] In some embodiments, the semiconductor device 10 further includes a first lower gate 132a, a first upper gate 134a, and a first dielectric layer 120a disposed in the first trench T1, and the first upper gate 134a is located above the first lower gate 132a. The first dielectric layer 120a is located between any two of the first upper gate 134a, the first lower gate 132a, and the epitaxial layer 110.
[0033] In some embodiments, the first dielectric layer 120a includes a first portion 122a, a second portion 124a, and a third portion 126a. The first portion 122a is located between the first lower gate 132a and the epitaxial layer 110. The second portion 124a is located between the first lower gate 132a and the first upper gate 134a. The third portion 126a is located between the first upper gate 134a and the epitaxial layer 110, and the third portion 126a can also be referred to as a gate dielectric layer 126a.
[0034] In some embodiments, the body layer 116 can be located between adjacent first trenches T1, and the depth of the body layer 116 does not exceed the top surface of the first lower gate 132a. The source doped region 118 is located on one side of the body layer 116 close to the top surface 110t of the epitaxial layer 110. That is, the body layer 116 and the source doped region 118 can be located between adjacent first upper gates 134a.
[0035] In some embodiments, the gate G of the field effect transistor FET can be constituted by the first upper gate 134a, which is configured for the formation of a channel of the field effect transistor FET, the source S of the field effect transistor FET can be constituted by the source doped region 118, and the drain D of the field effect transistor FET can be constituted by the semiconductor substrate 100. Due to the second drift region 114 between the source S and the drain D of the field effect transistor FET, it can be helpful to reduce the on-state voltage of the field effect transistor FET. In some embodiments, the first lower gate 132a can be electrically connected to the source S of the field effect transistor FET.
[0036] In some embodiments, the semiconductor device 10 further includes a dielectric layer 140 disposed between the first conductive layer 150 and the epitaxial layer 110, and the dielectric layer 140 covers the first trench Tl to electrically isolate the first upper gate 134a from the first conductive layer 150.
[0037] In some embodiments, the first conductive layer 150 includes a conductive contact 152. The conductive contact 152 extends through the dielectric layer 140 into the source doped region 118 and part of the body layer 116 to electrically connect the first conductive layer 150 with the source doped region 118 and the body layer 116. That is, the first conductive layer 150 can be in direct contact with the source doped region 118 and the body layer 116.
[0038] In some embodiments, the semiconductor device 10 further includes a second conductive layer 160 disposed on a side of the semiconductor substrate 100 opposite to the epitaxial layer 110 (i.e. below the semiconductor substrate 100) and electrically connected with the semiconductor substrate 100. Figure 1
[0039] In some embodiments, the third drift region 113 surrounds the entire second trench T2, and thus it can be understood that the Schottky diode SBD is disposed in the third drift region 113 (or the extended portion of the first drift region 112) but not in the second drift region 114. In this way, the leakage current of the Schottky diode SBD can be reduced.
[0040] In some embodiments, the semiconductor device 10 further includes a second lower gate 132b, a second upper gate 134b and a second dielectric layer 120b disposed in the second trench T2, and the second upper gate 134b is on top of the second lower gate 132b. The second dielectric layer 120b is between any two of the second upper gate 134b, the second lower gate 132b and the epitaxial layer 110.
[0041] In some embodiments, the second dielectric layer 120b includes a first portion 122b, a second portion 124b and a third portion 126b. The first portion 122b is between the second lower gate 132b and the epitaxial layer 110. The second portion 124b is between the second lower gate 132b and the second upper gate 134b. The third portion 126b is between the second upper gate 134b and the epitaxial layer 110, and the third portion 126b can also be referred to as a gate dielectric layer 126b.
[0042] In some embodiments, the first conductive layer 150 further comprises a conductive contact 154. The conductive contact 154 penetrates the dielectric layer 140 to electrically connect the first conductive layer 150 with the third drift region 113 and the second upper gate 134b. That is, the first conductive layer 150 can be in direct contact with the third drift region 113 and the second upper gate 134b. In some embodiments, the second lower gate 132b can also be electrically connected to the source potential.
[0043] In some embodiments, the anode E1 of the Schottky diode SBD can be formed by the second lower gate 132b, the second upper gate 134b and the partial first conductive layer 150, and the cathode E2 of the Schottky diode SBD can be formed by the third drift region 113 and the semiconductor substrate 100, so that the junction between the first conductive layer 150 and the third drift region 113 is formed as a Schottky junction.
[0044] In the present embodiment, the anode E1 of the Schottky diode SBD is electrically connected to the source S of the field effect transistor FET through the conductive contact 152 of the first conductive layer 150, and the cathode E2 of the Schottky diode SBD is electrically connected to the drain D of the field effect transistor FET. That is, the Schottky diode SBD is connected in parallel between the source S and the drain D of the field effect transistor FET, so that the switching recovery time of the field effect transistor FET can be shortened, thereby reducing the energy loss.
[0045] In addition, since the second drift region 114 and the first drift region 112 are provided between the source S and the drain D of the field effect transistor FET, and the Schottky diode SBD is located in the third drift region 113, the on-voltage of the field effect transistor FET can be reduced while avoiding increasing the leakage current of the Schottky diode SBD.
[0046] Figures 2A to 2E is a sectional view of a manufacturing process of a semiconductor device according to the present application. It must be noted that, Figures 2A to 2E the embodiments of Figure 1 the components of the embodiments of
[0047] Please refer to Figure 2AAn epitaxial layer 110 is formed on a semiconductor substrate 100, wherein the epitaxial layer 110 has a first region R1 and a second region R2. The epitaxial layer 110 can be formed by an epitaxial growth process. In some embodiments, a dopant having a first conductivity type may be introduced during the epitaxial growth process, so that the epitaxial layer 110 has a first conductivity type. In some embodiments, the first conductivity type is N-type, and the N-type dopant may include phosphorus, arsenic, antimony, or the like. In other embodiments, the first conductivity type is P-type, and the P-type dopant may include boron, aluminum, gallium, or the like.
[0048] Then, a plurality of trenches are formed in the epitaxial layer 110, for example, a first trench T1 is formed in a first region R1 of the epitaxial layer 110, and a second trench T2 is formed in a second region R2 of the epitaxial layer 110.
[0049] A dielectric material layer 122 is formed on the epitaxial layer 110. For example, the dielectric material layer 122 may be conformally deposited on the surfaces of the first trench T1 and the second trench T2 and on the top surface 110t of the epitaxial layer 110 by a deposition process (e.g., chemical vapor deposition, physical vapor deposition, etc.). In some embodiments, the dielectric material layer 122 comprises silicon oxide or other suitable dielectric material.
[0050] Subsequently, a conductive material is formed on the dielectric material layer 122 and in the first trench T1 and the second trench T2, and the conductive material is removed to form a first lower gate 132a in the first trench T1 and a second lower gate 132b in the second trench T2. In some embodiments, the materials of the first lower gate 132a and the second lower gate 132b may include polysilicon or other suitable conductive materials.
[0051] Please refer to Figure 2B Additional dielectric material is formed in the first trench T1 and the second trench T2 and on the top surface 110t of the epitaxial layer 110, so as to interact with... Figure 2A The dielectric material layer 122 is formed together with the dielectric material layer 122'. Then a planarization process is performed until the top surface 110t of the epitaxial layer 110 is exposed, so that the top surface of the dielectric material layer 122' is flush with the top surface 110t of the epitaxial layer 110.
[0052] Please refer to Figure 2CA patterned mask layer Ml (e.g., a hard mask layer or a photoresist layer) is formed on the top surface 110t of the epitaxial layer 110, covering the second region R2 of the epitaxial layer 110 and exposing the first region Rl of the epitaxial layer 110 where the second drift region is to be formed. Dopants of the first conductivity type are then implanted into the top surface 110t of the epitaxial layer 110 not covered by the patterned mask layer Ml by an ion implantation process P to form the second drift region 114 surrounding the first trench Tl in the first region Rl of the epitaxial layer 110, and the portion of the first region Rl not implanted by the ion implantation process forms the first drift region 112. Since the second region R2 is covered by the patterned mask layer Ml, no ion implantation occurs in the second region R2, which becomes the third drift region 113.
[0053] Referring to Figure 2D The patterned mask layer Ml is removed, and then a portion of the dielectric material layer 122' is removed by an etching process to expose a portion of the sidewalls of the first and second trenches Tl, T2 and the top surface 110t of the epitaxial layer 110, while the dielectric material layer 122' remaining in the first trench Tl forms the first and second portions 122a, 124a of the first dielectric layer 120a, and the dielectric material layer 122' remaining in the second trench T2 forms the first and second portions 122b, 124b of the second dielectric layer 120b.
[0054] A third portion 126a (also referred to as a gate dielectric layer 126a) of the first dielectric layer 120a is then formed on the exposed sidewalls of the first trench Tl by a thermal oxidation process or other suitable deposition process, and a third portion 126b (also referred to as a gate dielectric layer 126b) of the second dielectric layer 120b is formed on the exposed sidewalls of the second trench T2. In some embodiments, dielectric material is also formed on the exposed top surface of the epitaxial layer 110, such that the gate dielectric layer 126a extends from the sidewalls of the first trench Tl to the top surface 110t of the epitaxial layer 110, and the gate dielectric layer 126b extends from the sidewalls of the second trench T2 to the top surface 110t of the epitaxial layer 110.
[0055] Conductive material is then formed in the first and second trenches Tl, T2 and on the epitaxial layer 110, and an etching process or a planarization process is performed on the conductive material until the first and second dielectric layers 120a, 120b on the top surface 110t of the epitaxial layer 110 are exposed, while the conductive material remaining in the first trench Tl forms the first upper gate 134a, and the conductive material remaining in the second trench T2 forms the second upper gate 134b. In some embodiments, the material of the first and second upper gates 134a, 134b can include polysilicon or other suitable conductive material.
[0056] Referring to Figure 2EA patterned mask layer M2 (e.g., a hard mask layer or a photoresist layer) is formed over the top surface 110t of the epitaxial layer 110, covering the second region R2 of the epitaxial layer 110 and exposing the first region Rl of the epitaxial layer 110 where the body layer 116 is to be formed. Dopants of the second conductivity type are then implanted into the top surface 110t of the epitaxial layer 110 not covered by the patterned mask layer to form the body layer 116 in the second drift region 114. Subsequently, dopants of the first conductivity type can be implanted into the top surface 110t of the epitaxial layer 110 not covered by the patterned mask layer to form the source doped region 118 in the body layer 116.
[0057] Next, referring to Figure 1 , the patterned mask layer M2 is removed, and additional dielectric material is formed on the epitaxial layer 110, which is located on the top surface 110t of the epitaxial layer 110 to collectively form the dielectric layer 140. Thereafter, the dielectric layer 140 is patterned by a plurality of photolithography and etching processes to form a first opening OPl passing through the dielectric layer 140, the source doped region 118 and part of the body layer 116, and a second opening OP2 passing through the dielectric layer 140 to expose the top surface 110t of the second region R2 of the epitaxial layer 110 and the top surface of the second upper gate 134b. A first conductive layer 150 is then formed on the dielectric layer 140 and filled into the first opening OPl and the second opening OP2, where the portion of the first conductive layer 150 filled into the first opening OPl is referred to as a conductive contact 152, and the portion of the first conductive layer 150 filled into the second opening OP2 is referred to as a conductive contact 154.
[0058] In some embodiments, a second conductive layer 160 can be formed under the semiconductor substrate 100.
[0059] In some embodiments, the dielectric layer 140 can include silicon oxide or other suitable dielectric material. In some embodiments, the materials of the first conductive layer 150 and the second conductive layer 160 can include metal (e.g., copper, aluminum, tungsten, titanium, silver, alloys thereof, combinations thereof, etc.) or other suitable conductive material.
[0060] Based on the above, the manufacturing of the semiconductor device 10 can be substantially completed.
[0061] In summary, the semiconductor device of the present application has a second drift region and a first drift region in a first region of an epitaxial layer, and a third drift region in a second region of the epitaxial layer. In this way, different components can be arranged in different regions according to different electrical requirements to improve the performance of the semiconductor device. For example, a field effect transistor can be located in the first region to help reduce its on-voltage, and a Schottky diode can be located in the second region to help reduce its leakage current.
[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not limited thereto; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A semiconductor device, characterized in that, include: Semiconductor substrate; An epitaxial layer, disposed on the semiconductor substrate, and having a first conductivity type, wherein the epitaxial layer comprises: A first region includes a first drift region having a first doping concentration and a second drift region having a second doping concentration, wherein the second doping concentration is not equal to the first doping concentration; and The second region is adjacent to the first region and includes a third drift region having a third doping concentration, wherein the third doping concentration is equal to the first doping concentration; The main body layer is disposed in the second drift region and has a second conductivity type, which is opposite to the first conductivity type; A source-doped region, disposed in the main body layer, and having the first conductivity type; and A first conductive layer is disposed on the epitaxial layer and directly contacts the surface of the second region of the epitaxial layer, and is electrically connected to the source doped region.
2. The semiconductor device according to claim 1, characterized in that, The first drift region is located between the semiconductor substrate and the second drift region.
3. The semiconductor device according to claim 1, characterized in that, The epitaxial layer has a plurality of first trenches located in the second drift region of the first region.
4. The semiconductor device according to claim 3, characterized in that, Also includes: A first lower gate is disposed in the plurality of first trenches; as well as A first upper gate is disposed in the plurality of first trenches and located above the first lower gate, wherein the depth of the main body layer does not exceed the top surface of the first lower gate.
5. The semiconductor device according to claim 4, characterized in that, Also includes: A dielectric layer is disposed in the plurality of first trenches and located between any two of the first upper gate, the first lower gate and the epitaxial layer.
6. The semiconductor device according to claim 1, characterized in that, The source doped region has a fourth doping concentration, which is greater than the second doping concentration.
7. The semiconductor device according to claim 1, characterized in that, The semiconductor substrate has a fifth doping concentration, which is greater than the first doping concentration and the second doping concentration.
8. The semiconductor device according to claim 1, characterized in that, The first conductive layer further includes conductive contacts that extend into the source doped region and the main body layer. The conductive contact is electrically connected to the main body layer.
9. The semiconductor device according to claim 1, characterized in that, It also includes a second conductive layer disposed below the semiconductor substrate and electrically connected to the semiconductor substrate.
10. The semiconductor device according to claim 1, characterized in that, The interface between the first conductive layer and the third drift region is a Schottky interface.