Packaging frame with built-in MIS substrate and packaging structure
By using a packaging frame structure with an integrated MIS substrate, discrete devices are placed on the MIS substrate. By using a traditional frame base island as a carrier, the problem of traditional packaging being unable to support complex circuit connections is solved, thereby improving the packaging integration and controlling the packaging size. It also has good current carrying capacity, voltage withstand capability, and heat dissipation performance.
Patent Information
- Application Number
- CN202422968165.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2034-12-02
AI Technical Summary
Traditional frame-type packaging cannot support complex circuit connection functions, making it difficult to achieve multi-chip packaging. Furthermore, the current carrying capacity, voltage withstand capability, and heat dissipation performance of existing MIS substrates are insufficient, resulting in large package size and easy warping.
The packaging frame structure with an integrated MIS substrate is adopted to place discrete devices on the MIS substrate and use traditional frame base islands as carriers to realize the built-in packaging of discrete devices, combining the complex connection function of the MIS substrate and the excellent performance of traditional frames.
It enables the built-in assembly of discrete components, improves package integration, controls package size, simplifies the wire bonding process, and has good current carrying capacity, voltage withstand capability, and heat dissipation performance, making it suitable for complex application scenarios.
Smart Images
Figure CN223829831U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of packaging technology, specifically to built-in MIS substrate's packaging frame, packaging structure. BACKGROUND
[0002] Traditional frame class package, since it only has a layer of metal frame, thus cannot bear complex circuit connection function, it is difficult to realize internal multi -core's plastic package scheme. In addition, the traditional joint package multi -chip package structure needs to hang capacitor and pull -down resistance when power supply, this requires increasing external pin on the packaging structure to set up capacitor device, such as Figure 1 As shown, only necessary discrete devices can be set outside the frame. Doing so not only needs to increase the size of single package, but also increases the complexity of the application end. In addition, the existing packaging process is difficult to deal with complex wire bonding, and does not allow cross wire bonding. Although advanced packaging substrates such as MIS substrates can meet the function of complex circuit connection, their current carrying capacity, voltage resistance and heat dissipation performance are slightly inferior to traditional packaging frames. Furthermore, using MIS substrate to realize frame base island manufacturing, too large size will cause warping risk due to insufficient strength. SUMMARY
[0003] The utility model wants to solve the technical problem of built-in MIS substrate's packaging frame, packaging structure, realizing discrete device built-in under the condition of controlling packaging size and not increasing processing difficulty, improving chip integration.
[0004] In order to solve the above technical problem, the first technical scheme adopted by the utility model is:
[0005] Built-in MIS substrate's packaging frame, including frame base island, MIS substrate and discrete device, the discrete device is arranged on the MIS substrate, the MIS substrate is arranged on the frame base island.
[0006] Optionally, it further includes a chip, the chip is arranged on the frame base island, and the discrete device is connected with the chip through wire bonding.
[0007] Optionally, it further includes a chip, the chip is arranged on the MIS substrate, and the discrete device is connected with the chip through wire bonding.
[0008] Optionally, the discrete device includes resistance and capacitor.
[0009] Optionally, the frame base island includes a first frame base island and a second frame base island which are isolated, the MIS substrate includes a first MIS substrate and a second MIS substrate, and the discrete device includes a first discrete device and a second discrete device.
[0010] The first discrete device is arranged on the first MIS substrate; the first MIS substrate is arranged on the first frame base island; the second discrete device is arranged on the second MIS substrate; and the second MIS substrate is arranged on the second frame base island.
[0011] Optionally, the first chip and the second chip are further included; the first chip is arranged on the first frame base island; the first discrete device is connected with the first chip; the second chip is arranged on the second frame base island; and the second discrete device is connected with the second chip.
[0012] Optionally, the first chip and the second chip are further included; the first chip is arranged on the first MIS substrate; the first discrete device is connected with the first chip; the second chip is arranged on the second MIS substrate; and the second discrete device is connected with the second chip.
[0013] The second technical scheme adopted by the utility model is:
[0014] The packaging structure of the built-in MIS substrate comprises the packaging frame of the built-in MIS substrate.
[0015] Optionally, the plastic package body is further included; and the plastic package body encapsulates the packaging frame of the built-in MIS substrate.
[0016] The utility model discloses the beneficial effect lies in: the utility model discloses by using the traditional frame as the frame base island, then utilizes MIS substrate as the carrier of discrete device and realizes the built-in packaging of discrete device, solves the problem of single MIS substrate warping, utilizes the advantage of MIS substrate and realizes complex circuit connection and discrete device built-in assembly, and does not need to increase external pin, can control the packaging size, improves the sealing function, and further, can rewire on MIS substrate, simplifies the frame lead-out end wire, further, can also have the excellent performance of traditional frame in current-carrying voltage resistance heat dissipation etc., makes traditional frame satisfy complex application scene, thereby, the utility model discloses can realize discrete device built-in, improves the sealing function, and further improves the packaging integration, is favorable to product miniaturization. DRAWINGS
[0017] Figure 1 It is the structural schematic diagram of traditional chip;
[0018] Figure 2 It is the structural schematic diagram of the packaging frame of built-in MIS substrate provided by the utility model embodiment one;
[0019] Figure 3 It is the structural schematic diagram of the packaging frame of built-in MIS substrate provided by the utility model embodiment two Figure 1 ;
[0020] Figure 4 Structure diagram of the packaging frame with built-in MIS substrate provided in Embodiment Two of the present application Figure 2
[0021] Figure 5 Structure diagram of the packaging frame with built-in MIS substrate provided in Embodiment Three of the present application Figure 1
[0022] Figure 6 Process flow diagram of the packaging frame with built-in MIS substrate Figure 5
[0023] Figure 7 Structure diagram of the packaging frame with built-in MIS substrate provided in Embodiment Three of the present application Figure 2
[0024] Figure 8 Process flow diagram of the packaging frame with built-in MIS substrate Figure 7
[0025] Label explanation:
[0026] 1, frame base island; 2, MIS substrate; 3, discrete device; 4, chip;
[0027] 11, first frame base island; 12, second frame base island;
[0028] 21, first MIS substrate; 22, second MIS substrate;
[0029] 31, first discrete device; 32, second discrete device;
[0030] 41, first chip; 42, second chip. DETAILED DESCRIPTION
[0031] In order to describe possible application scenarios, technical principles, specific implementation schemes, purposes and effects of the present application in detail, the following specific embodiments are combined with the accompanying drawings for detailed description. The embodiments described in this paper are only used to more clearly illustrate the technical scheme of the present application, therefore, only as an example, and cannot limit the protection scope of the present application.
[0032] The term "embodiment" is mentioned in this document means that the specific features, structures or properties described in combination with the embodiment can be included in at least one embodiment of the present application. The term "embodiment" appearing in various places in the specification does not necessarily refer to the same embodiment, nor does it particularly limit its independence or association with other embodiments. In principle, in this application, as long as there is no technical contradiction or conflict, each technical feature mentioned in each embodiment can be combined in any way to form a corresponding implementable technical solution.
[0033] Unless otherwise defined, the meanings of the technical terms used herein are the same as those commonly understood by those skilled in the art to which the present application belongs; the use of related terms in this document is only for the purpose of describing specific embodiments, and is not intended to limit the present application.
[0034] In the description of the present application, the phrase "and / or" is a description of the logical relationship between the objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases: A exists, B exists, and A and B exist at the same time. In addition, the character " / " in this document generally represents a "or" logical relationship between the associated objects before and after.
[0035] In the present application, terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual quantity, primary or secondary, or order relationship between the entities or operations.
[0036] Without more limitations, in the present application, the use of "includes", "contains", "has" or other similar expressions in the sentence is intended to cover non-exclusive inclusion, and these expressions do not exclude the presence of other elements in the process, method or product including the described elements, so that the process, method or product including a series of elements can not only include those limited elements, but also include other elements not explicitly listed, or also include elements inherent to such process, method or product.
[0037] As understood in the "Guidelines for Examination", in the present application, "greater than", "less than", "exceeding" and the like are understood as not including the number; "above", "below", "within" and the like are understood as including the number. In addition, in the description of the embodiments of the present application, the meaning of "multiple" is more than two (including two), and similar expressions related to "multiple" are also understood in this way, for example, "multiple groups", "multiple times" and the like, unless otherwise specifically limited.
[0038] In the description of the embodiments of the utility model, the space related expressions used, such as '' center '' '' longitudinal '' '' transverse '' '' length '' '' width '' '' thickness '' '' upper '' '' lower '' '' front '' '' rear '' '' left '' '' right '' '' vertical '' '' horizontal '' '' perpendicular '' '' top '' '' bottom '' '' inner '' '' outer '' '' clockwise '' '' counterclockwise '' '' axial '' '' radial '' '' circumferential '' and the like, the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the specific embodiment or the drawing, only for the convenience of describing the specific embodiment of the utility model or for the convenience of the reader to understand, and not indicate or imply that the indicated device or component must have a specific position, a specific orientation, or be constructed or operated in a specific orientation, therefore, it cannot be understood as the limitation of the embodiment of the utility model.
[0039] Unless otherwise expressly provided or limited, in the description of the embodiments of the utility model, the terms such as '' installation '' '' connection '' '' fixed '' '' set '' should be understood broadly.For example, the '' connection '' can be fixed connection, or detachable connection, or integrated setting, it can be mechanical connection, or electrical connection, or communication connection, it can be direct connection, or indirect connection through intermediate medium, it can be the communication or interaction relationship between two elements.For the skilled in the art to which the utility model belongs, the specific meaning of the above terms in the embodiments of the utility model can be understood according to the specific circumstances.
[0040] Please refer to Figure 2 , the embodiment of the utility model is:
[0041] The embodiment provides a packaging frame with built-in MIS substrate, as shown in Figure 2 , which comprises a frame base island 1, an MIS substrate 2 and a discrete device 3, the discrete device 3 is arranged on the MIS substrate 2, and the MIS substrate 2 is arranged on the frame base island 1.
[0042] In some specific embodiments, the discrete device includes resistors, capacitors, diodes, transistors, thyristors, MOS tubes and other electronic devices for realizing rectification, voltage stabilization, switching and the like.
[0043] In some specific embodiments, the packaging frame further comprises a chip, here, the chip specifically refers to an integrated circuit die (Die). In the packaging process, the die (Die) is bonded on the substrate by glue, and then the bonding pad of the die is connected to the corresponding pin of the substrate through ultrafine metal wires, thereby forming the required circuit.In the embodiment, the discrete device and the chip are connected through the wire bonding process.
[0044] In the embodiment, the traditional packaging frame is used as the base island, so that the base island has advantages in current-carrying, voltage-withstanding and heat dissipation; the advanced packaging material MIS substrate is used as the carrier of the discrete device, so that the built-in and complex connection of the discrete device are realized. Therefore, the embodiment can realize the complex scene application of the traditional frame, realize the built-in of the discrete device, improve the packaging integration, and is beneficial to product miniaturization.
[0045] Referring to Figure 3 and Figure 4 , the second embodiment of the utility model provides:
[0046] The embodiment further extends the first embodiment, and provides two specific setting modes of the chip.
[0047] In some specific embodiments, as shown in Figure 3 , the chip 4 can be arranged on the frame base island 1. That is, only the discrete device 3 is arranged on the MIS substrate 2. The discrete device 3 arranged on the MIS substrate 2 is connected with the chip 4 arranged on the frame base island 1 through wire bonding.
[0048] In some specific embodiments, as shown in Figure 4 , the chip 4 can be arranged on the MIS substrate 2. That is, the discrete device 3 and the chip 4 are arranged on the MIS substrate 2. The discrete device 3 and the chip 4 on the MIS substrate 2 are connected through wire bonding.
[0049] The embodiment can provide two feasible specific setting modes for the chip under the premise of ensuring the built-in packaging of the discrete device and obtaining good packaging effect, and users can flexibly select according to the actual scene demand or the convenience of process manufacturing, so as to provide more selectivity for users.
[0050] Referring to Figure 5 and Figure 6 , the third embodiment of the utility model provides:
[0051] The embodiment further extends the first embodiment and the second embodiment, and provides a packaging frame with a built-in MIS substrate. The packaging architecture can be used in a scene with isolation communication transmission demand.
[0052] In the embodiment, as shown in Figure 5 and Figure 6 , the frame base island 1 includes a first frame base island 11 and a second frame base island 12 which are isolated from each other (which can also be understood as independent from each other, and there is no connection relationship); the MIS substrate 2 includes a first MIS substrate 21 and a second MIS substrate 22 which are independent from each other; the discrete device 3 includes a first discrete device 31 and a second discrete device 32; and the chip 4 specifically includes a first chip 41 and a second chip 42.
[0053] Specifically, the first discrete device 31 is arranged on the first MIS substrate 21 to form a first MIS module; the first MIS substrate 21 is arranged on the first frame base island 11; and the first chip 41 is arranged corresponding to the first frame base island 11.
[0054] The second discrete device 32 is arranged on the second MIS substrate 22 to form a second MIS module; the second MIS substrate 22 is arranged on the second frame base island 12; and the second chip 42 is arranged corresponding to the second frame base island 12.
[0055] In the embodiment, corresponding to the two specific arrangement modes of the chip provided in the above-mentioned embodiment two, the packaging frame provided in the embodiment and having the isolation communication function can also have two specific implementation modes.
[0056] In some specific embodiments, the chip is specifically arranged on the frame base island.
[0057] As shown in Figure 5 , the first chip 41 is arranged on the first frame base island 11; the first discrete device 31 arranged on the first MIS substrate 21 is connected with the first chip 41 through wire bonding; the second chip 42 is arranged on the second frame base island 12; and the second discrete device 32 arranged on the second MIS substrate 22 is connected with the second chip 42 through wire bonding.
[0058] Corresponding to the process flow of the above-mentioned specific embodiments, as shown in Figure 6 , the process flow is as follows:
[0059] S1: MIS substrate manufacturing;
[0060] S2: Discrete devices such as resistors and capacitors are attached to the MIS substrate to form an MIS module;
[0061] S3: Frame base island manufacturing;
[0062] S4: The chip and the MIS module are bonded on the frame base island;
[0063] S5: Wire bonding pins and substrate signals;
[0064] S6: Overall plastic packaging;
[0065] S7: Cutting and forming to obtain a finished chip.
[0066] In some other specific embodiments, the chip is specifically arranged on the MIS substrate.
[0067] As shown in Figure 7As shown, the first chip 41 is arranged on the first MIS substrate 21; the first discrete device 32 is connected with the first chip 42 through wire bonding; the second chip 42 is arranged on the second MIS substrate 22; and the second discrete device 32 is connected with the second chip 42 through wire bonding.
[0068] The process flow corresponding to the above embodiment is shown in the following figure: Figure 8
[0069] S1: MIS substrate manufacturing;
[0070] S2: Discrete devices such as resistors and capacitors are attached to the MIS substrate, and at the same time, chips are also attached to the MIS substrate to manufacture an MIS module;
[0071] S3: Frame base island manufacturing;
[0072] S4: The MIS module is bonded on the frame base island;
[0073] S5: Wire bonding pins and substrate signals;
[0074] S6: Overall plastic packaging;
[0075] S7: Cutting rib forming to obtain a finished chip.
[0076] It can be understood that the packaging frame of the embodiment comprises two chip base island structures which are independent of each other and have consistent structures and functions. By utilizing the isolation property between them, wireless isolation communication transmission can be realized, such as high and low voltage wireless isolation devices in power systems and other scenarios requiring wireless isolation transmission.
[0077] Embodiment four of the utility model discloses:
[0078] The embodiment is based on any of the above embodiments and provides a packaging structure with a built-in MIS substrate, which comprises the packaging frame with a built-in MIS substrate and a plastic package body. The packaging frame is plastic packaged by the plastic package body to obtain the packaging structure. Here, the specific structure of the packaging frame with a built-in MIS substrate is not repeated, and details can be referred to the description of embodiments one to three.
[0079] The packaging structure of the embodiment can be used in decoupling filtering, terminal matching, chip pin function configuration and other scenarios.
[0080] In particular, the packaging structure obtained based on the packaging architecture of embodiment three comprises two base island structures which are independent of each other and have consistent structures and functions. By utilizing the isolation property between them, wireless isolation communication transmission can be realized, such as high and low voltage wireless isolation devices in power systems and other scenarios requiring wireless isolation transmission.
[0081] In summary, the utility model provides the packaging frame of built -in MIS base plate, packaging structure, on the basis of traditional frame base island, utilize MIS base plate as the carrier of discrete device and realize built -in packaging of discrete device. Not only can reduce the number of external pin, improve the function of sealing, control the package size, but also can rewire on MIS base plate, simplify frame lead -out end wire; Further, still can have the excellent performance of traditional frame in current -carrying voltage resistance heat dissipation etc, make traditional frame satisfy complex application scene. Thus realize built -in discrete device, improve the function of sealing, and then improve the packaging integration, be favorable to product miniaturization.
[0082] The above-mentioned is only the embodiment of the utility model, and does not limit the patent range of the utility model, and any equivalent transformation, direct or indirect application in related technical field by the contents of the utility model specification and drawings are all included in the patent protection range of the utility model.
Claims
1. A packaging frame with an integrated MIS substrate, characterized in that, It includes a frame base island, a MIS substrate, and discrete devices; the discrete devices are disposed on the MIS substrate; the MIS substrate is disposed on the frame base island.
2. The packaging frame with an embedded MIS substrate as described in claim 1, characterized in that, It also includes a chip; the chip is disposed on the frame base island; the discrete device is connected to the chip by wire bonding.
3. The packaging frame with an embedded MIS substrate as described in claim 1, characterized in that, It also includes a chip; the chip is disposed on the MIS substrate; the discrete device is connected to the chip by wire bonding.
4. The packaging frame with an embedded MIS substrate as described in claim 1, characterized in that, The discrete components include resistors and capacitors.
5. The packaging frame with an embedded MIS substrate as described in claim 1, characterized in that, The frame base island includes a first frame base island and a second frame base island that are isolated from each other; the MIS substrate includes a first MIS substrate and a second MIS substrate; the discrete device includes a first discrete device and a second discrete device. The first discrete device is disposed on the first MIS substrate; the first MIS substrate is disposed on the first frame base island; the second discrete device is disposed on the second MIS substrate; the second MIS substrate is disposed on the second frame base island.
6. The packaging frame with an embedded MIS substrate as described in claim 5, characterized in that, It also includes a first chip and a second chip; the first chip is disposed on the first frame base island; the first discrete device is connected to the first chip; the second chip is disposed on the second frame base island; and the second discrete device is connected to the second chip.
7. The packaging frame with an embedded MIS substrate as described in claim 5, characterized in that, It also includes a first chip and a second chip; the first chip is disposed on the first MIS substrate; the first discrete device is connected to the first chip; the second chip is disposed on the second MIS substrate; and the second discrete device is connected to the second chip.
8. A packaging structure with an embedded MIS substrate, characterized in that, The packaging frame includes the built-in MIS substrate as described in any one of claims 1 to 7.
9. The packaging structure with an embedded MIS substrate as described in claim 8, characterized in that, It also includes a molding compound; the molding compound encapsulates the packaging frame of the built-in MIS substrate.