Chip packaging module and semiconductor device
By setting conductive metal pads or wafer pads on the packaging substrate as bridging, the problem of needing to design separate carrier boards for chips from different manufacturers is solved, achieving chip compatibility and cost savings.
Patent Information
- Application Number
- CN202520210481.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-10
- Publication Date
- 2026-01-23
- Estimated Expiration
- 2035-02-10
AI Technical Summary
In the existing technology, the high correlation between the carrier board and the chip means that chips from different manufacturers need to be designed with dedicated carrier boards, which is costly and makes it difficult to make chips from different manufacturers compatible on the same carrier board.
By setting conductive metal pads or wafer pads on the packaging substrate as bridges, the electrical connection between the second chip and the packaging substrate is achieved, allowing chips from different manufacturers to be compatiblely set on the same packaging substrate and share the main control chip.
It achieves compatibility settings for chips from different manufacturers, shortening the development process and saving development costs.
Smart Images
Figure CN223829834U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a chip packaging module and a semiconductor device including the chip packaging module. Background Technology
[0002] In existing technologies, chips are typically packaged on a carrier board (substrate) and then mounted on a printed circuit board. The carrier board not only provides support, heat dissipation, and protection for the chip but also provides electronic connections between the chip and the printed circuit board. There is a high degree of interdependence between the carrier board and the chip; different chips often require dedicated carrier boards, resulting in high costs. Chips from different manufacturers require separately designed carrier boards (substrates), making it difficult to design them on a single carrier board. Utility Model Content
[0003] This application provides a chip packaging module, including:
[0004] The packaging substrate includes a first surface and a second surface opposite to each other, and the first surface is provided with a plurality of gold fingers;
[0005] A first chip is disposed on the first surface;
[0006] The second chip is stacked on the side of the first chip that faces away from the packaging substrate; and
[0007] A conductive metal pad or wafer pad is disposed on the surface of the second chip away from the packaging substrate. The conductive metal pad or wafer pad is electrically connected to the chip select signal of the second chip and is connected to the gold finger through metal leads.
[0008] The chip packaging module of this application embodiment achieves electrical connection between the second chip and the packaging substrate by setting conductive metal pads / wafer pads on the second chip on the packaging substrate as a bridge. In this way, even if the first chip and the second chip are produced by different manufacturers, and the pads of the first chip and the second chip are arranged or sized differently, they can be compatiblely set on the same packaging substrate and share the same main control chip, thereby shortening the development process and saving development costs.
[0009] In at least one embodiment, both the first chip and the second chip are memory chips.
[0010] In at least one embodiment, the plurality of gold fingers are disposed near one edge of the packaging substrate.
[0011] In at least one embodiment, the second chip has a plurality of conductive metal pads or a plurality of wafer pads disposed on the surface away from the packaging substrate. At least one conductive metal pad or at least one wafer pad is connected to another adjacent conductive metal pad or wafer pad through a metal lead. The adjacent conductive metal pad or the adjacent wafer pad is then connected to the gold finger through the metal lead.
[0012] In at least one embodiment, along the thickness direction of the packaging substrate, the projected area of the first chip on the packaging substrate is greater than or equal to the projected area of the first chip on the packaging substrate.
[0013] In at least one embodiment, the first chip has pads on its surface away from the packaging substrate, and the pads are connected to the gold fingers via metal leads.
[0014] In at least one embodiment, the chip packaging module further includes at least one chip stacked between the first chip and the second chip.
[0015] In at least one embodiment, an electrically insulating die-casting film is disposed between the first chip and the packaging substrate, and an electrically insulating die-casting film is disposed between the first chip and the second chip.
[0016] In at least one embodiment, the chip packaging module further includes a main control chip, which is disposed on the first surface and spaced apart from both the first chip and the second chip.
[0017] This application also provides a semiconductor device, including a printed circuit board and the aforementioned chip packaging module disposed on the printed circuit board. Attached Figure Description
[0018] Figure 1 This is a cross-sectional schematic diagram of the chip packaging module according to an embodiment of this application.
[0019] Figure 2 This is a top view of the chip packaging module according to an embodiment of this application.
[0020] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of this application.
[0021] Explanation of main component symbols
[0022] Chip packaging module 100, packaging substrate 10, first chip 20, second chip 30.
[0023] Main control chip 40, first surface 11, second surface 12, gold fingers 13.
[0024] Input / output terminals 14, die-cast adhesive film 50, metal leads 60.
[0025] Conductive metal pad / wafer pad 31, molding compound 70, semiconductor device 200.
[0026] Printed circuit board 210. Detailed Implementation
[0027] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application pertain. The terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the embodiments of this application. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply.
[0028] It should be noted that all directional indicators (such as up, down, left, right, front, and back) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.
[0029] like Figure 1 and Figure 2 As shown, this application embodiment provides a chip packaging module 100, including a packaging substrate 10, a first chip 20, a second chip 30, and a main control chip 40 disposed on the packaging substrate 10. The first chip 20 and the second chip 30 are stacked one on top of the other on the packaging substrate 10, with the second chip 30 stacked on the side of the first chip 20 facing away from the packaging substrate 10. The main control chip 40 is spaced apart from the stacked first chip 20 and the second chip 30. The main control chip 40 is used to control the first chip 20 and the second chip 30. The main control chip 40 can control the first chip 20 and the second chip 30 through the packaging substrate 10.
[0030] The packaging substrate 10 is a core material in the chip packaging process. Developed based on printed circuit board technology, the packaging substrate 10 features high density, high precision, high performance, miniaturization, and thinness. The packaging substrate 10 plays a crucial role in the chip packaging process, not only providing support, heat dissipation, and protection for the chip, but also establishing electronic connections between the chip and the PCB, realizing electrical and physical connections, power distribution, and signal distribution functions.
[0031] In this embodiment, the packaging substrate 10 includes a first surface 11 and a second surface 12 facing each other, wherein the first chip 20, the second chip 30, and the main control chip 40 are disposed on the first surface 11. The first surface 11 of the packaging substrate 10 is also provided with gold fingers 13, and the second surface 12 is provided with input / output terminals 14. In this embodiment, the input / output terminals 14 are solder balls protruding from the second surface 12. The gold fingers 13 are connected to the input / output terminals 14 of the second surface 12 through vias. Through-holes are provided in the packaging substrate 10, and conductive material is disposed in the through-holes to connect the gold fingers 13 and the input / output terminals 14.
[0032] In this embodiment, a plurality of gold fingers 13 are disposed near one side edge of the packaging substrate 10. This prevents the gold fingers 13 from being obstructed when the larger first chip 20 is mounted on the packaging substrate 10. Furthermore, arranging as many gold fingers 13 as possible along the side edge facilitates connection with a greater number of metal leads 60.
[0033] Based on different materials, packaging substrates can be divided into the following categories: Rigid packaging substrates: These have a rigid structure and are the most widely used. Their main raw materials include BT packaging substrates, ABF packaging substrates, and MIS packaging substrates. BT substrates are not easily affected by thermal expansion and contraction, have stable dimensions, are hard, and have thick circuitry, making them suitable for mobile phone MEMS, communications, memory, and LED applications. ABF substrates are suitable for large, high-end chips such as CPUs, GPUs, and chipsets. Flexible packaging substrates: These use polyimide film as the base film and are suitable for applications requiring bending or flexibility. Flexible film substrates are mainly divided into three-layer adhesive substrates and two-layer adhesive-free substrates. Adhesive-free substrates are thinner and suitable for high-density wiring, representing the main development direction for future flexible packaging substrates. Ceramic packaging substrates: These have stable thermal properties and excellent thermal conductivity, and are mainly used in applications requiring high reliability.
[0034] In this embodiment, both the first chip 20 and the second chip 30 are memory chips, such as flash memory chips, dynamic random access memory (DRAM) chips, etc.
[0035] In this embodiment, the first chip 20 has a front side and a back side, with the back side facing the packaging substrate 10, and the first chip 20 is disposed on the packaging substrate 10 with the front side facing upwards. An electrically insulating die attach film (DAF) 50 is disposed between the first chip 20 and the packaging substrate 10. The die attach film 50 is a high-performance film widely used in semiconductor packaging for connecting the chip and the packaging substrate 10; it has excellent adhesion and thermal conductivity, can remain stable in high-temperature environments, and provides reliable mechanical connection and thermal management for the chip.
[0036] This embodiment uses wire bonding (WB) to connect the first chip 20 to the packaging substrate 10. The WB process uses fine metal wires and leverages heat, pressure, and ultrasonic energy to tightly bond the metal leads 60 to the chip pads and the packaging substrate 10, achieving electrical interconnection and information exchange between the chip and the packaging substrate 10. This method is widely used in the packaging of RF modules, memory chips, and microelectromechanical systems (MEMS) devices. Although not shown in the figures, the front side of the first chip 20 has pads, such as chip select signal pads. The pads are electrically connected to the gold fingers 13 of the packaging substrate 10 via metal leads. The metal leads can be made of various conductive metals or conductive alloys, such as gold.
[0037] In this embodiment, the second chip 30 has a front and a back side, with the back side facing the first chip 20, and the second chip 30 is disposed on the first chip 20 with its front side facing upwards. A die-casting adhesive film 50 is disposed between the second chip 30 and the first chip 20. Multiple conductive metal pads or multiple wafer pads 31 are disposed on the front side of the second chip 30, and the conductive metal pads / wafer pads 31 are connected to the chip select signal pads on the front side of the second chip 30. The conductive metal pads can be made of conductive metals, such as aluminum or copper. The wafer pads can be made of silicon (Si) or other semiconductor materials. The conductive metal pads / wafer pads 31 on the second chip 30 are then electrically connected to the gold fingers 13 of the packaging substrate 10 via metal leads 60. That is, the chip select signal on the second chip 30 is electrically connected to the conductive metal pads / wafer pads 31, the conductive metal pads / wafer pads 31 are then electrically connected to the metal leads 60, and the metal leads 60 are then electrically connected to the gold fingers 13 of the packaging substrate 10. Thus, the chip select signal of the second chip 30 passes sequentially through the conductive metal pad / wafer pad 31 and the metal lead 60 to reach the gold fingers 13 of the packaging substrate 10. The gold fingers 13 connected to the first chip 20 are different from those connected to the second chip 30. Figure 1 This is a cross-sectional view. Figure 1 The connection between the metal lead 60 of the conductive metal pad / wafer pad 31 and the gold finger 13 is shown for illustration only and does not represent the actual connection.
[0038] In this embodiment, the pad positions for the chip select signal of the first chip 20 and the chip select signal of the second chip 30 are different. Therefore, if the chip select signal of the first chip 20 is directly connected to the corresponding gold finger 13 of the package substrate 10 via the metal lead 60, and the chip select signal of the second chip 30 is also directly connected to the corresponding gold finger 13 of the package substrate 10 via the metal lead 60, then the metal lead 60 of the second chip 30 typically needs to be extended quite a bit to connect to the corresponding gold finger 13. This extended metal lead 60 poses a risk of short circuit. In this embodiment, by providing a conductive metal pad / wafer pad 31 on the second chip 30, and using the conductive metal pad / wafer pad 31 to connect the chip select signal and the gold finger 13 of the package substrate 10, the extension length of the metal lead 60 can be effectively shortened, thereby effectively avoiding the risk of short circuit.
[0039] like Figure 2 As shown, the front side of the second chip 30 is provided with multiple conductive metal pads / wafer pads 31. Some of the conductive metal pads / wafer pads 31 are directly connected to metal leads 60, and the metal leads 60 are then directly connected to the gold fingers 13 of the packaging substrate 10. Some of the conductive metal pads / wafer pads 31 are connected to another adjacent conductive metal pad / wafer pad 31 through metal leads 60, and the adjacent conductive metal pad / wafer pad 31 is then directly connected to metal leads 60, and the metal leads 60 are then directly connected to the gold fingers 13 of the packaging substrate 10.
[0040] Although not shown in the figures, an insulating film is also provided between the second chip 30 and the conductive metal pad / wafer pad 31 in this embodiment of the application.
[0041] In this embodiment, the area of the first chip 20 is greater than or equal to the area of the second chip 30. Along the thickness direction of the packaging substrate 10, the projected area of the first chip 20 on the packaging substrate 10 is greater than or equal to the projected area of the second chip 30 on the packaging substrate 10. Thus, the first chip 20, being closer to the packaging substrate 10, can better support the second chip 30. However, if the area of the second chip 30 is larger than the area of the first chip 20, an insulating layer needs to be provided around the first chip 20, in the area where the second chip 30 extends beyond the first chip 20, to support the second chip 30.
[0042] The chip packaging module 100 of this application embodiment achieves electrical connection between the second chip 30 and the packaging substrate 10 by adding conductive metal pads or multiple wafer pads 31 as bridges to the second chip 30 on the packaging substrate 10. In this way, even if the first chip 20 and the second chip 30 are produced by different manufacturers, and the pads of the first chip 20 and the second chip 30 are arranged or sized differently, they can be compatiblely set on the same packaging substrate 10 and share the same main control chip 40, thereby shortening the development process and saving development costs.
[0043] Understandably, the number of chips stacked in the chip packaging module 100 is not limited to two. At least one chip can be placed between the first chip 20 and the second chip 30, and adjacent chips are bonded to each other by a die-casting adhesive film 50.
[0044] like Figure 1 As shown, the chip packaging module 100 also includes a molding compound 70 disposed on the first surface 11 of the packaging substrate 10. The molding compound 70 completely encapsulates the first chip 20, the second chip 30 and the main control chip 40 to protect the chips.
[0045] The method for preparing the chip packaging module 100 according to this application includes the following steps:
[0046] The conductive metal block or wafer block is thinned to an appropriate thickness (e.g., a thickness of several to tens of micrometers) and cut into the appropriate size as needed to form a conductive metal pad / wafer pad 31;
[0047] The conductive metal pad / wafer pad 31 is attached to the front side of the second chip 30;
[0048] The first chip 20 is bonded to the packaging substrate 10, and then the pads of the first chip 20 are connected to the gold fingers 13 of the packaging substrate 10 through the metal leads 60.
[0049] The second chip 30 is bonded to the front side of the first chip 20, and then the conductive metal pad / wafer pad 31 is connected to the gold finger 13 of the packaging substrate 10 through the metal lead 60.
[0050] like Figure 3 As shown, this application also provides a semiconductor device 200, including a printed circuit board 210 and the aforementioned chip packaging module 100 disposed on the printed circuit board 210. Input / output terminals 14 on the packaging substrate 10 in the chip packaging module 100 are electrically connected to the printed circuit board 210. The packaging substrate 10 supports a first chip 20, a second chip 30, and a main control chip 40, and connects these chips to the printed circuit board 210, serving as chip support, protection, and signal transmission. The printed circuit board 210 is mainly used for supporting and electrically connecting electronic components. By arranging conductive lines on the board, the various electronic components are connected to achieve electrical signal transmission.
[0051] This application achieves compatibility by appropriately designing the packaging substrate 10 and electrically connecting the topmost chip of the packaging substrate 10 with conductive metal pads / wafer pads 31, thereby enabling chips from different manufacturers to be compatiblely mounted on the same packaging substrate 10, shortening the product development cycle and saving costs.
[0052] Those skilled in the art should recognize that the above embodiments are only used to illustrate this application and are not intended to limit this application. Any appropriate changes and variations made to the above embodiments within the essential spirit and scope of this application fall within the scope of protection claimed by this application.
Claims
1. A chip packaging module, characterized in that, include: The packaging substrate includes a first surface and a second surface opposite to each other, and the first surface is provided with a plurality of gold fingers; A first chip is disposed on the first surface; The second chip is stacked on the side of the first chip that is away from the packaging substrate; as well as A conductive metal pad or wafer pad is disposed on the surface of the second chip away from the packaging substrate. The conductive metal pad or wafer pad is electrically connected to the chip select signal of the second chip and is connected to the gold finger through metal leads.
2. The chip packaging module as described in claim 1, characterized in that, Both the first chip and the second chip are memory chips.
3. The chip packaging module as described in claim 1, characterized in that, The plurality of gold fingers are disposed near one edge of the packaging substrate.
4. The chip packaging module as described in claim 1, characterized in that, The second chip has a plurality of conductive metal pads or a plurality of wafer pads disposed on the surface away from the packaging substrate. At least one conductive metal pad or at least one wafer pad is connected to another adjacent conductive metal pad or wafer pad through a metal lead. The adjacent conductive metal pad or the adjacent wafer pad is then connected to the gold finger through the metal lead.
5. The chip packaging module as described in claim 1, characterized in that, Along the thickness direction of the packaging substrate, the projected area of the first chip on the packaging substrate is greater than or equal to the projected area of the first chip on the packaging substrate.
6. The chip packaging module as described in claim 1, characterized in that, The first chip has pads on its surface away from the packaging substrate, and the pads are connected to the gold fingers via metal leads.
7. The chip packaging module as described in claim 1, characterized in that, The chip packaging module further includes at least one chip stacked between the first chip and the second chip.
8. The chip packaging module as described in claim 1, characterized in that, An electrically insulating die-casting film is disposed between the first chip and the packaging substrate, and an electrically insulating die-casting film is disposed between the first chip and the second chip.
9. The chip packaging module as described in claim 1, characterized in that, The chip packaging module also includes a main control chip, which is disposed on the first surface and spaced apart from both the first chip and the second chip.
10. A semiconductor device, characterized in that, It includes a printed circuit board and a chip packaging module disposed on the printed circuit board as described in any one of claims 1 to 9.