Conductive via and semiconductor device

Abstract

A conductive via and a semiconductor device having the same are provided. The conductive through hole comprises a first end and a second end; a first portion adjacent to the first end; the second part is adjacent to the second end; and an intermediate portion between the first portion and the second portion wherein the conductive vias consist of metal particles, the metal particles in the first portion having a first particle size; the metal particles in the second part have a second particle size; the metal particles in the intermediate portion have a third particle size; the first particle size is larger than the third particle size; and the second particle size is larger than the third particle size.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a conductive via and a semiconductor device. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit elements and components thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic devices by continually reducing the minimum feature size of the devices. However, as the minimum feature size is reduced, additional problems arise that should be addressed.

[0004] In an effort to reduce the size of integrated circuits and reduce RC delay, three-dimensional integrated circuits (3DICs) and stacked dies are commonly used. As a result, conductive through-substrate vias (TSVs) are used in 3DICs and stacked dies. For example, conductive TSVs are commonly used to connect integrated circuits on a die to the backside of the die. In addition, conductive TSVs are also used to provide a short ground path for grounding the integrated circuits through the backside of the die, which can be covered by a ground metal film. SUMMARY

[0005] Some embodiments of the present disclosure provide a conductive via, comprising: a first end, a second end, a first portion adjacent to the first end, a second portion adjacent to the second end, and a middle portion between the first portion and the second portion. Wherein the conductive via is composed of a plurality of metal particles, wherein the metal particles in the first portion have a first particle size; wherein the metal particles in the second portion have a second particle size; wherein the metal particles in the middle portion have a third particle size; wherein the first particle size is greater than the third particle size; and wherein the second particle size is greater than the third particle size.

[0006] Some embodiments of the present disclosure provide a semiconductor device, comprising: a metal interconnect, comprising: a copper core; and a titanium copper alloy surrounding the copper core.

[0007] Some embodiments of the present disclosure provide a semiconductor device including a metal interconnect, the metal interconnect including: a copper core; a titanium copper alloy surrounding the copper core; and a titanium layer surrounding the titanium copper alloy at a top portion of the copper core. The copper core includes copper grains; the copper core includes a top portion, a bottom portion, and a middle portion between the top portion and the bottom portion; the copper grains in the top portion have a first average grain size; the copper grains in the bottom portion have a second average grain size; the copper grains in the middle portion have a third average grain size; the first average grain size is greater than the third average grain size; and the second average grain size is greater than the third average grain size. BRIEF DESCRIPTION OF DRAWINGS

[0008] The aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, for the sake of clarity, various features of the drawings can not be drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. DETAILED DESCRIPTION

[0009] Figure 1 A flowchart illustrating a method according to some embodiments;

[0010] Figures 2 to 8 A cross-sectional view of an intermediate stage of manufacturing a wafer including a conductive TSV and a deep conductive via connected to the conductive TSV according to various embodiments;

[0011] Figure 9 A wafer including a conductive TSV and a deep conductive via, where a metal line connecting the conductive TSV and the deep conductive via is formed in a process step separate from process steps used to form the conductive TSV and the deep conductive via is illustrated;

[0012] Figure 10 A wafer including a conductive TSV and a deep conductive via, where the conductive TSV extends through a substrate that is substantially free of integrated circuit devices is illustrated;

[0013] Figures 11 to 22 A cross-sectional view of an intermediate stage of manufacturing a wafer including a conductive TSV and a deep conductive via connected to the conductive TSV according to various embodiments;

[0014] Figure 23 A graph illustrating a grain size distribution within a top portion, a middle portion, and a bottom portion of a conductive TSV according to various embodiments is illustrated;

[0015] Figure 24 A cross-sectional view of a portion of a layer deposited on a trench sidewall, for example, during Figure 16 an anneal process of

[0016] Figure 25 A cross-sectional view of a portion of a layer formed of an alloy, for example, after an anneal process of Figure 20 .

[0017] SYMBOL DESCRIPTION

[0018] 20: device

[0019] 22: substrate

[0020] 22a: front surface

[0021] 24: integrated circuit / transistor / active integrated circuit device / semiconductor device

[0022] 26: interconnect structure

[0023] 28: ILD

[0024] 30: contact plug

[0025] 34: IMD

[0026] 38, 38A, 38B: metal line / solder pad

[0027] 40: via

[0028] 44: trench

[0029] 46, 46A-D: trench

[0030] 47, 72: layer

[0031] 50: photoresist

[0032] 52, 152: insulating layer

[0033] 54: stack

[0034] 56: mask

[0035] 58, 111: opening

[0036] 60, 200: conductive via / conductive TSV

[0037] 62: deep via

[0038] 66: metal line

[0039] 67: diffusion barrier layer

[0040] 72: passivation layer

[0041] 74, 78: UBM

[0042] 76, 80: metal bump

[0043] 108: total height

[0044] 110: device layer

[0045] 112: trench sidewall

[0046] 114: trench bottom surface

[0047] 120: device

[0048] 121: device surface

[0049] 141: bottom sidewall location

[0050] 142: middle height sidewall location

[0051] 143: top sidewall location

[0052] 144: trench

[0053] 152: layer

[0054] 154, 158: layer

[0055] 156: layer

[0056] 159: arrow

[0057] 160: gaseous material

[0058] 162: layer

[0059] 164: conductive material / layer / copper core

[0060] 166: alloy

[0061] 170: RDL

[0062] 200: conductive via / conductive TSV / conductive interconnect structure

[0063] 201: top surface

[0064] 202: bottom surface

[0065] 208: height / depth

[0066] 209: lateral critical dimension

[0067] 210: portion

[0068] 220: portion

[0069] 230: portion

[0070] 300: particle

[0071] 310, 320, 330: particle

[0072] 399: void

[0073] 900: method

[0074] D1-D5: depth

[0075] M1, M2, M3, Mtop: metallization layer

[0076] S902, S904, S906, S950, S954, S956, S958, S960, S962, S968, S970, S972, S980, S982, S994, S996, S998: operation

[0077] T1-T4: thickness

[0078] W1-W5: horizontal size DETAILED DESCRIPTION

[0079] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the subject matter. Specific examples of elements and configurations are described below to provide a thorough description of embodiments. Of course, it is contemplated that the concepts and principles described herein can be embodied in various arrangements, all of which are within the scope of the present disclosure. Various examples of the aspects disclosed herein are illustrated in the following figures. Being illustrative only, the figures are not exhaustive or limiting of the scope of the disclosure. Certain aspects of the disclosure can be appreciated to more fully understand various aspects of the embodiments. It should be noted that where potentially conflicting details are presented, it is to be understood that a compromise between the various embodiments is also an embodiment of the present disclosure.

[0080] In addition, spatially relative terms, such as "on", "over", "above", "up", "top", "down", "under", "below", "downward", "upward", "side" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0081] In certain embodiments herein, a "material structure" is a structure that contains at least 50 wt.% of an identified material (e.g., at least 60 wt.% of an identified material, at least 75 wt.% of an identified material, at least 90 wt.% of an identified material, at least 95 wt.% of an identified material, or at least 99 wt.% of an identified material); and a structure formed from a "material" contains at least 50 wt.% of an identified material, e.g., at least 60 wt.% of an identified material, at least 75 wt.% of an identified material, at least 90 wt.% of an identified material, at least 95 wt.% of an identified material, or at least 99 wt.% of an identified material. For example, certain embodiments, each of a tungsten structure and a structure formed from tungsten is at least 50 wt.%, at least 60 wt.%, at least 75 wt.%, at least 90 wt.%, at least 95 wt.%, or at least 99 wt.% tungsten.

[0082] For the sake of brevity, typical technical details probably not pertinent to the present disclosure can not be described in great detail. In addition, various tasks and processes outlined in the present disclosure can be combined in a manner not specifically described herein. In particular, various semiconductor device manufacturing tasks are well known and so, for brevity, many conventional tasks have been omitted or simply referenced. As will be apparent to those of ordinary skill in the art, after having been fully described, the structures disclosed herein can employ a variety of technologies and can be incorporated into a wide variety of semiconductor devices and products. In addition, it should be noted that semiconductor device structures include different numbers of elements, and a single element shown in an illustration can represent multiple elements.

[0083] Embodiments of semiconductor devices and methods for fabricating such devices with through-substrate vias (TSVs), which are sometimes also referred to as through-silicon vias (TSVs) when formed in silicon substrates, are presented herein. The methods described herein can be readily integrated into current process flows.

[0084] Certain embodiments herein are directed to three-dimensional integrated circuit (3DIC) applications built by vertically stacking different dies or wafers together into a single package. For example, in 3DIC applications, through-substrate vias (TSVs) can be applied to die-to-die stacks or die-to-interposer stacks for vertical electrical signal connections. Certain embodiments herein optimize the stress and void distribution in the TSVs to achieve 100% yield during manufacturing. For example, a selective metallization process for forming a conductive TSV can be used to achieve a Large-Small-Large (L-S-L) grain distribution along the height or depth of the TSV, i.e., from top to bottom (or from bottom to top). Moreover, this grain distribution can be symmetrical.

[0085] In some embodiments, a method of achieving a Large-Small-Large (LSL) grain distribution in a conductive structure, such as in a conductive via like a conductive TSV, is provided. The method can utilize a metallization process to fill a trench, including forming an outer adhesion layer having a thickness gradient, forming an outer barrier layer having a constant thickness on the outer adhesion layer, forming an inner adhesion layer having a thickness gradient on the outer barrier layer, removing the inner adhesion layer from a trench bottom surface, and subsequently forming a seed layer and performing an annealing process to form an alloy having grains before filling the trench with a conductive fill.

[0086] In some embodiments, the annealing process for forming the TSV can cause small voids to diffuse to the middle or mid-level height of the TSV, instead of diffusing to the bottom of the TSV. Specifically, the voids move down from the top of the TSV to the mid-level, while the voids move up from the bottom of the TSV to the mid-level.

[0087] Moreover, the conductive TSV material forms relatively large grains at the top and bottom of the conductive TSV, and relatively small grains at the mid-level of the conductive TSV. As the voids migrate from high stress to low stress (i.e., from large grains to small grains or to the TSV top surface or bottom surface), there is no void accumulation at the interface between the top of the conductive TSV and the top grain redistribution layer (RDL), and there is also no void accumulation at the interface between the bottom of the conductive TSV and the bottom grain redistribution layer (RDL). Instead, most of the voids diffuse towards the mid-level of the conductive TSV. Thus, there is less void accumulation at the TSV top surface or the TSV bottom surface.

[0088] Embodiments herein avoid or reduce the formation of large voids, sidewall delamination, conductive TSV end protrusions, and TSV / die interface voids. Embodiments herein improve the grain distribution of conductive materials, such as copper and / or titanium copper alloys, to form conductive TSVs with high thermal stability.

[0089] Embodiments of the disclosure provide advantages over the prior art, although it should be understood that other embodiments can provide different advantages and not necessarily all of the advantages discussed herein, and all embodiments need not necessarily exhibit the same advantages.

[0090] For the purposes of the following discussion, Figure 1 A flowchart of a method 900 for fabricating a semiconductor device during a semiconductor fabrication process is provided. The following description is made in conjunction with illustrations of a semiconductor device at various stages of fabrication according to the method 900. Figures 2 to 10 and Figures 11 to 22 The method 900 is described.

[0091] Figures 2 to 8 A cross-sectional view of an intermediate stage of fabricating a wafer including a conductive TSV and a deep conductive via connected to the conductive TSV according to various embodiments is illustrated. Figure 9 A wafer including a conductive TSV and a deep conductive via is illustrated, where a metal line connecting the conductive TSV and the deep conductive via is formed in a process step separate from process steps used to form the conductive TSV and the deep conductive via. Figure 10 A wafer including a conductive TSV and a deep conductive via is illustrated. Figures 11 to 22 A cross-sectional view of an intermediate stage for forming a conductive TSV within a trench is illustrated.

[0092] Referring to Figure 2 The method 900 includes, at operation S902, providing a semiconductor device 20 including a substrate 22 and an integrated circuit 24 (represented by a transistor) therein. According to various embodiments, the device 20 is a wafer including an active integrated circuit device 24, such as a transistor. The substrate 22 can be a semiconductor substrate, such as a bulk silicon substrate, although the substrate 22 can be formed of other semiconductor materials, such as silicon germanium, gallium arsenide, and / or the like. Semiconductor devices, such as transistors (represented by transistor 24), can be formed at a front surface 22a of the substrate 22. An interconnect structure 26 is formed on a front side of the substrate 22. The interconnect structure 26 can include an interlayer dielectric (ILD) 28 (in which electrodes of the transistors are located) and a contact plug 30 in the ILD 28, where the contact plug 30 can be formed of tungsten or other metal materials.

[0093] Furthermore, the interconnect structure 26 includes inter-metal dielectric (IMD) 34 and metal lines / pads 38 (including 38A and 38B) and vias 40 in the IMD 34. The IMD 34 can be formed of a low-k dielectric material having a low-k value, such as less than about 2.5 or even less than about 2.0. The interconnect structure 26 can include a bottom metallization layer (commonly referred to as Ml) and a top metallization layer (commonly referred to as Mtop) and a plurality of metallization layers therebetween, including a metallization layer directly above Ml (M2), a metallization layer directly above M2 (M3), and the like. Metal features in the interconnect structure 26 can be electrically coupled to the semiconductor devices 24. The metal lines / pads 38 and vias 40 can be formed of copper or a copper alloy and can be formed using a well-known damascene process. The metal lines / pads 38 include metal lines 38A and metal pads 38B, where the metal pads 38B are used to connect to deep vias formed later.

[0094] The interconnect structure 26 can further include one or more passivation layers 47 directly above the metallization layer Mtop. The passivation layers 47 can be non-low-k dielectric layers and can be formed of silicon oxide, silicon nitride, undoped silicate glass, polyimide, or the like. Furthermore, additional metal lines / pads and vias (not shown) can be formed in the passivation layers 47.

[0095] In alternative embodiments, such as in Figure 10 In examples where the device 20 is an interposer wafer and substantially free of integrated circuit devices, including active devices, such as transistors and diodes formed therein. In these embodiments, the substrate 22 can be formed of a semiconductor material or a dielectric material. The dielectric material can be silicon oxide, an organic material such as polyimide, a hybrid material such as a molded compound, glass, or the like. Furthermore, the interposer device 20 can include or be free of passive devices, such as capacitors, resistors, inductors, varactor diodes, and / or the like.

[0096] Referring to Figure 3After the interconnect structure 26 is formed, the interconnect structure 26 can or can not include the layer 47, the method 900 can include, at operation S904, forming trenches, such as the TSV trenches 44 and the deep via trenches 46 (including 46A, 46B, 46C, 46D, and possibly more trenches not illustrated). In an embodiment, the photoresist 50 is formed and patterned. The TSV trenches 44 and the deep via trenches 46 are then formed simultaneously by etching. The TSV trenches 44 extend into the substrate 22, while the deep via trenches 46 stop at the respective metal pads 38B, where the metal pads 38B are exposed by the deep via trenches 46. Further, the formation of the deep via trenches 46 can stop at the metal pads 38B in any of the different metallization layers in any desired combination ranging from Ml to Mtop.

[0097] In an embodiment, the pattern loading effect is applied to form the TSV trenches 44 and the deep via trenches 46 with different depths simultaneously. It is observed that when forming certain via openings, a via opening with a larger horizontal size can have a greater depth than a via opening with a smaller size, even if the via openings are formed with the same etching process. As a result of the pattern loading effect in the etching process, and also due to the size difference between the TSV trenches 44 and the deep via trenches 46, the resulting TSV trenches 44 and deep via trenches 46 will have different depths. By properly adjusting the horizontal sizes Wl to W5, when a desired depth Dl of the TSV trenches 44 is reached, the desired depths D2, D3, D4, D5, and the like are also reached. This can reduce undesirable over-etching of the metal pads 38B, and thus can minimize undesirable damage to the metal pads 38B. Accordingly, the horizontal size Wl (which can be a diameter or a length / width, depending on the shape of the TSV trenches 44) of the TSV trenches 44 is greater than the horizontal sizes W2, W3, W4, and W5 of the deep via trenches 46. In an embodiment, the ratio of Wl / W2 (or Wl / W3, Wl / W4, etc.) can be greater than about 1.5, greater than about 5, or even greater than about 100. Further, the depth Dl of the TSV trenches 44 is greater than the depths D2 of the deep via trenches 46. In an embodiment, the ratio of Dl / D2 (or Dl / D3, Dl / D4, etc.) can be greater than about 5, or even greater than about 5000. Further, in the illustrated embodiment, W2 can be greater than W3, where the ratio W2 / W3 is greater than about 1.2, W3 can be greater than W4, where the ratio W3 / W4 is greater than about 1.2, and W4 can be greater than W5, where the ratio W4 / W5 is greater than about 1.2.

[0098] Referring to Figure 4 The method 900 can continue, at operation S906, by forming the insulating layer 52. For example, the insulating layer 52 can be deposited and patterned, and the metal pads 38B can be exposed through openings in the insulating layer 52.

[0099] Method 900 can continue at operation S950 with forming an adhesion / barrier layer stack 54.

[0100] Method 900 can continue at operation S962 with forming a thin seed layer Figure 4 (not shown in FIG. 6). For example, the seed layer can be formed over the stack 54. The material of the seed layer can include copper or copper alloy, and can also include metals such as silver, gold, aluminum, and combinations thereof. In an embodiment, the seed layer is formed by sputtering. In other embodiments, other commonly used methods such as electroplating or electroless plating can be used.

[0101] Referring to Figure 5 , method 900 can include, at operation S968, patterning a photoresist 56 over the previously formed structure. In an embodiment, for example, the photoresist 56 includes a photoresist. In an exemplary embodiment, the resulting conductive TSVs need to be connected to the metal pads 38B. Therefore, openings 58 are formed in the photoresist 56, exposing the TSV trenches 44 and the deep via trenches 46.

[0102] In Figure 6 , method 900 includes, at operation S970, filling the trenches 44, 46 and the openings 58 with a metal material and forming conductive vias 60, such as conductive TSVs 60 in the TSV trenches 44, deep conductive vias 62 in the deep via trenches 46, and metal lines 66 in the openings 58. In various embodiments, the filling material includes copper or copper alloy, but other metals such as aluminum, silver, gold, and combinations thereof can also be used. The forming method can include printing, electroplating, electroless plating, and the like. In the same deposition process of filling the TSV trenches 44 with the metal material, the same metal material can also be filled in the openings 58, forming metal lines 66, which are also known as redistribution lines (RDLs).

[0103] Next, as shown in Figure 7 , method 900 includes, at operation S972, removing the photoresist 56.

[0104] Method 900 can include, at S980, performing an annealing process.

[0105] Method 900 can continue at operation S982 with planarizing the top device surface.

[0106] In Figure 8In method 900, during operation S994, a front-side interconnect structure is formed, such as including a redistribution layer (RDL), a passivation layer 72, and under-bump metallurgy (UBM) 74 and metal bumps 76. The metal bumps 76 may be solder bumps, copper bumps, and may include other layers / materials such as nickel, gold, solder, and / or the like.

[0107] exist Figure 8 In method 900, during operation S996, the back side of the apparatus 20 is polished to expose the conductive TSV 60. Furthermore, method 900 includes, during operation S998, forming a back-side interconnect structure on the back side of the apparatus 20, which may include a UBM 78 and bonding pads / metal bumps 80. Additionally, a back-side interconnect structure (not shown) comprising multiple redistribution layers may be formed between the conductive TSV 60 and the metal bumps 80, electrically coupling the conductive TSV 60 and the metal bumps 80.

[0108] Figure 9 Alternative embodiments are described. These embodiments are essentially the same as... Figure 8 The illustrated embodiment is the same, except that the metal line 66 is not formed in the same process as forming the conductive TSV 60 and the deep through-hole 62. Figure 9 In the embodiment, in forming Figure 4 Following the structure shown, TSV trenches 44 and via trenches 46 are filled, followed by a planarization process such as chemical mechanical polishing (CMP) to remove excess metal, thus forming conductive TSVs 60 and vias 62. After the CMP process, the conductive TSVs 60 and vias 62 are electrically disconnected from each other. Next, metal lines 66 are formed to electrically couple the conductive TSVs 60 to the vias 62. In the resulting structure, a diffusion barrier layer 67 separates the conductive TSVs 60 and vias 62 from the metal lines 66. The diffusion barrier layer 67 may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. However, in Figure 8 In the structure shown, no diffusion barrier layer is formed to separate the conductive TSV 60 and the deep via 62 from the metal line 66.

[0109] Although a device die containing semiconductor devices is used as an example in the illustrated figures, the teachings provided by the embodiments can be readily applied to interposers that do not include integrated circuits, such as transistors, resistors, diodes, capacitors, and / or the like. Similarly, by using the embodiments, deep vias can be formed on the interconnect structures in either or both of the front and back interconnect structures, wherein the deep vias connect to TSVs in the interposer.

[0110] Figures 11 to 22 This describes an embodiment for forming a conductive interconnect structure 200, such as a conductive via 200. Figures 2 to 10 Examples of conductive TSV 60 formed in the embodiments.

[0111] Figure 11 This describes the device 120 after operation S904, in which a structure similar to that from... Figures 2 to 10 The embodiment includes a TSV trench 44 with trench 144. Specifically, trench 144 is etched into a device layer, typically indicated by reference numerals (device layer 110). Device layer 110 may comprise various dielectric layers or substrates. Figure 11 In the device, a groove 144 extends from the upper device surface 121 through the device layer and forms opposing groove sidewalls 112 and a groove bottom surface 114. As shown, the groove 144 has an opening 111 at the upper device surface 121.

[0112] Figure 12 Following operation S906, an insulating layer 152 is formed in the trench 144 of the device 120. For example, the insulating layer 152 may be silicon oxide or another suitable insulating material. In some embodiments, the insulating layer 152 is conformally deposited and formed along the upper device surface 121, the trench sidewall 112, and the trench bottom surface 114.

[0113] Figures 13 to 16 This describes an embodiment for forming the adhesion / barrier stack 54 for operation S950. Specifically, as... Figure 13 As shown, method 900 can continue in operation S954, whichever is selected as appropriate, to form an adhesion layer 154 over the insulating layer 152. In some embodiments, the adhesion layer 154 is titanium (Ti). In other embodiments, the adhesion layer 154 can be selected from common materials such as titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof. In some embodiments, the adhesion layer 154 is deposited using physical vapor deposition (PVD). As shown, the adhesion layer 154 is formed over the upper device surface 121, over the trench sidewall 112, and over the trench bottom surface 114. Due to the deposition process, the adhesion layer 154 typically has a larger relative thickness above the horizontal surfaces (i.e., above the upper device surface 121 and above the trench bottom surface 114) compared to the vertical surface of the trench sidewall 112. Furthermore, due to the deposition process, the adhesion layer 154 is typically formed on the trench sidewall 112 with a thickness decreasing from the upper device surface 121, where the adhesion layer thickness is greatest, toward the trench bottom surface 114, where the adhesion layer sidewall thickness is smallest and can be zero.

[0114] For example, in embodiments, the adhesion layer 154 is formed with a maximum lateral or sidewall thickness on each trench sidewall 112 at the opening 111 of the trench 144 that is 25 to 60 times greater, such as 50 times greater, than a minimum lateral or sidewall thickness on each trench sidewall 112 adjacent to the trench bottom surface 114. For example, the maximum sidewall thickness of the adhesion layer 154 can be 250 nanometers (nm), and the minimum sidewall thickness of the adhesion layer 154 can be 5 to 10 nanometers (nm). In this example, the vertical thickness of the adhesion layer 154 above the trench bottom surface 114 can be 50 nanometers (nm).

[0115] In Figure 14 the method 900 can continue at operation S956 by forming a barrier layer 156 over the adhesion layer 154. In some embodiments, the barrier layer 156 is titanium nitride (TiN). In other embodiments, the barrier layer 156 can be selected from commonly used materials such as titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof. In some embodiments, the barrier layer 156 is deposited using chemical vapor deposition (CVD). As shown, the barrier layer 156 is formed over the upper device surface 121, over the trench sidewall 112, and over the trench bottom surface 114. In some embodiments, the barrier layer 156 is conformally deposited over the upper device surface 121, the trench sidewall 112, and the trench bottom surface 114 at substantially the same thickness.

[0116] In Figure 15 the method 900 can continue at operation S958 by forming an adhesion layer 158 over the barrier layer 156. In some embodiments, the adhesion layer 158 is titanium (Ti). In other embodiments, the adhesion layer 158 can be selected from commonly used materials such as titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof. In some embodiments, the adhesion layer 158 is deposited using physical vapor deposition (PVD). As shown, the adhesion layer 158 is formed over the upper device surface 121, over the trench sidewall 112, and over the trench bottom surface 114. Due to the deposition process, the adhesion layer 158 is typically formed with a greater relative thickness over horizontal surfaces (i.e., over the upper device surface 121 and over the trench bottom surface 114) as compared to more vertical surfaces of the trench sidewall 112. Further, due to the deposition process, the adhesion layer 158 is typically formed with a decreasing thickness on the trench sidewall 112 from the upper device surface 121, where the adhesion layer thickness is greatest, toward the trench bottom surface 114, where the adhesion layer sidewall thickness is smallest and can be zero.

[0117] For example, in embodiments, the adhesion layer 158 is formed with a maximum lateral or sidewall thickness on each trench sidewall 112 at the opening 111 of the trench 144 that is 25 to 60 times greater, such as 50 times greater, than a minimum lateral or sidewall thickness on each trench sidewall 112 adjacent to the trench bottom surface 114. For example, the maximum sidewall thickness of the adhesion layer 158 can be 250 nanometers (nm), and the minimum sidewall thickness of the adhesion layer 158 can be 5 to 10 nanometers (nm). In this example, the vertical thickness of the adhesion layer 158 above the trench bottom surface 114 can be 50 nanometers (nm).

[0118] In Figure 16 the method 900 can continue at operation S960 with performing an etching process to remove the adhesion layer 158 from above the trench bottom surface 114. For example, a dry etching process such as a plasma etching process can be performed. In some embodiments, the etching process can use argon gas without reactive ions. In some embodiments, the etching process is a sputter etching process. For example, ions such as argon ions can bombard the adhesion layer 158 above the trench bottom surface 114. The etching process can be highly directional such that it can be focused on the trench bottom surface 114.

[0119] As a result of the etching process, the adhesion layer 158 is removed from above the trench bottom surface 114. In particular, the barrier layer 156 is exposed at the trench bottom surface 114. In addition, as indicated by arrow 159, the removed adhesion layer can form a gaseous material 160 that is subsequently deposited on the trench sidewall 112. Thus, the coverage of the adhesion layer material above the lower portion of the trench sidewall 112 can be increased. It should be noted that enhancing the coverage of the lower portion of the trench sidewall 112 with adhesion layer material such as titanium can prevent copper delamination.

[0120] Figure 16Formation of a metallization stack or structure including adhesion layer 154, barrier layer 156, and adhesion layer 158 is described, which is configured to provide a final conductive TSV with a desired grain distribution. As shown, layers 154, 156, and 158 are provided with different thicknesses at different locations of the trench 144. For example, layers 154, 156, and 158 can be provided with different thicknesses over the trench bottom surface 114, at a bottom sidewall location 141 adjacent to the trench bottom surface 114, at a top sidewall location 143 adjacent to the opening 111 of the trench, and at a mid-layer or mid-height sidewall location 142 between the top sidewall location 143 and the bottom sidewall location 141. In some embodiments, the mid-height sidewall location 142 can be equidistant from the top sidewall location 143 and the bottom sidewall location 141. In other embodiments, the mid-height sidewall location can be located at a height over the trench bottom surface 114 equal to 20%, 30%, 40%, 50%, 60%, 70%, or 80% of the total height 108 of the trench 144.

[0121] In Figure 17 Method 900 can continue at operation S962 by forming a seed layer 162 over the device surface 121 and in the trench 144. The seed layer 162 can be copper. In some embodiments, the material of the seed layer can include copper or a copper alloy, and can also include metals such as silver, gold, aluminum, and combinations thereof.

[0122] In embodiments, the seed layer 162 is formed using physical vapor deposition (PVD). Further, the seed layer 162 can be deposited with selectivity to form over the material of the adhesion layer 158, such as titanium, as compared to the material of the barrier layer 156, which is titanium nitride. Thus, the seed layer can be formed with a maximum thickness over the adhesion layer 158 at the horizontal device surface 121, a minimum thickness or zero thickness over the barrier layer 156 at the trench bottom surface 114, and a decreasing thickness from the maximum seed layer thickness at the horizontal device surface 121 toward the minimum and can be zero seed layer thickness at the trench bottom surface 114 over the adhesion layer 158 at the trench sidewall 112.

[0123] In Figure 18At this point, method 900 can continue in operation S970, depositing conductive material 164 to fill trench 144. In some embodiments, conductive material 164 is a metallic material, such as copper. In various embodiments, the filler material 164 comprises copper or a copper alloy, but other metals, such as aluminum, silver, gold, and combinations thereof, may also be used. Formation methods may include printing, electroplating, electroless plating, and the like. For example, conductive material 164 may be deposited using electrochemical deposition (ECD).

[0124] Typically, during the deposition process, the conductive material 164 is formed in small particles. As used herein, "small particles" have a maximum size of 0.5 micrometers (μm). In some embodiments, the small particles have a maximum size of 0.4 μm, 0.3 μm, 0.2 μm, or 0.1 μm. In some embodiments, at least 50 wt.%, at least 60 wt.%, at least 70 wt.%, at least 80 wt.%, at least 90 wt.%, at least 95 wt.%, or at least 99 wt.% of the conductive material 164 is formed from small particles.

[0125] Because the adhesive layer 158 has been previously removed from the bottom surface 114 of the trench, the conductive material 164 directly contacts the barrier layer 156, such as titanium nitride, at the bottom surface 114 of the trench. Along the trench sidewall 112, the conductive material and / or seed layer 162 directly contacts the adhesive layer 158, such as titanium.

[0126] exist Figure 19 At this point, method 900 can continue in operation S980, performing an annealing process. The annealing process may relate to particle growth and stress release. Specifically, during the annealing process, a conductive material 164, such as copper, is heated above its recrystallization temperature to release internal stress and is subsequently allowed to cool under controlled conditions. Therefore, particles of the conductive material 164 may grow during the annealing process. Furthermore, voids may migrate from high-stress locations to low-stress locations, i.e., from large particles to small particles. In addition, an alloy 166 may be formed in the region adjacent to the materials of the conductive material 164 and the adhesion layer 158. For example, a titanium-copper alloy 166 may be formed. It should be noted that a seed layer 162 is formed between the conductive material 164 and the adhesion layer 158 or the barrier layer 156. For simplicity, the conductive material 164 is described below, and it can be collectively referred to as the separately deposited seed layer 162 and the conductive material 164. Furthermore, in some embodiments, the seed layer 162 and the conductive material 164 are the same material.

[0127] As noted above, prior to the annealing process, the conductive material 164 directly contacts the barrier layer 156 at the trench bottom surface 114, and the conductive material and / or seed layer 162 directly contacts the adhesion layer 158 along the trench sidewall 112. Thus, formation of the titanium-copper alloy along the trench sidewall 112 can be more than the formation of the titanium-copper alloy at the trench bottom surface 114.

[0128] In embodiments herein, the conductive material 164 can form large particles in certain regions, and can form small particles in certain regions, as described below with respect to Figure 22

[0129] In Figure 20 , the method 900 can continue at operation S982 by planarizing the upper device surface 121. In particular, material of the layers 152, 154, 156, 158, 162, and 164 located above the upper device surface 121 can be removed, such as with a chemical mechanical planarization (CMP) process. Thus, the conductive via 200 is formed and defined within the trench 144.

[0130] In Figure 21 , the method 900 can continue at operation S994 by forming a front side interconnect structure including forming a redistribution layer (RDL) 170 over the conductive via 200.

[0131] In Figure 22 , the method 900 can continue at operation S996 by grinding a backside of the device and removing the device layer 110 below the trench bottom surface 114, thereby opening the trench bottom surface 114. For example, a planarization process can be used to open the trench bottom surface 114. Further, a bottom end of the conductive TSV 200 can be polished.

[0132] In Figure 22 , the method 900 can further continue at operation S998 by forming a backside interconnect structure including a redistribution layer (RDL) 170 over the opened bottom end of the conductive TSV 200.

[0133] As Figure 22 ​As shown, the conductive TSV 200 has a top surface 201 and a bottom surface 202. The top surface 201 is separated from the bottom surface, such as in the Z-direction, by a vertical height 208. The vertical height 208 can be 5 micrometers to 200 micrometers (pm). Further, the conductive TSV 200 has a lateral width or critical dimension in the X-direction, which is perpendicular to the Z-direction. The lateral critical dimension 209 can be 1 micrometer to 10 micrometers (pm). Thus, the conductive TSV 200 can have an aspect ratio (height / critical dimension) of 5 to 20.

[0134] Further, the conductive TSV 200 includes a top portion 210 adjacent to the top surface 201, a bottom portion 220 adjacent to the bottom surface 202, and a middle portion 230 or mid-layer between the top portion 210 and the bottom portion 220. Each portion 210, 220, and 230 can have a height equal to one-third of the total height 208.

[0135] Figure 22 Further, the conductive TSV 200 includes a top portion 210 adjacent to the top surface 201, a bottom portion 220 adjacent to the bottom surface 202, and a middle portion 230 or mid-layer between the top portion 210 and the bottom portion 220. Each portion 210, 220, and 230 can have a height equal to one-third of the total height 208.

[0136] In some embodiments, the largest particle 310 in the first portion 210 defines a maximum particle size. In some embodiments, the maximum particle size is 200 nanometers to 1000 nanometers (nm).

[0137] In some embodiments, the average particle size of the particles 310 in the first portion 210 is greater than 0.5 times the maximum particle size. For example, the average particle size of the particles 310 in the first portion 210 can be greater than 0.51, 0.52, 0.53, 0.54, 0.55, 0.56, 0.57, 0.58, 0.59, 0.60, 0.61, or 0.62 times the maximum particle size. Further, the average particle size of the particles 310 in the first portion 210 can be less than 0.8, 0.75, 0.74, 0.73, 0.72, 0.71, 0.70, 0.69, less than 0.68, 0.67, 0.66, 0.65, 0.64, 0.63, or 0.62 times the maximum particle size.

[0138] In some embodiments, the average particle size of the particles 320 in the second portion 220 is greater than 0.5 times the maximum particle size. For example, the average particle size of the particles 320 in the second portion 220 can be greater than 0.51, 0.52, 0.53, 0.54, or 0.55 times the maximum particle size. Further, the average particle size of the particles 320 in the second portion 220 can be less than 0.8, 0.75, 0.7, 0.65, 0.64, 0.63, 0.62, 0.61, 0.60, 0.59, 0.58, 0.57, 0.56, or 0.55 times the maximum particle size.

[0139] In some embodiments, the average particle size of the particles 330 in the middle portion 230 is less than 0.5 times the maximum particle size. For example, the average particle size of the particles 330 in the middle portion 230 can be greater than 0.25, 0.28, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, or 0.37 times the maximum particle size. Further, the average particle size of the particles 330 in the middle portion 230 can be less than 0.5, 0.49, 0.48, 0.47, 0.46, 0.45, 0.44, 0.43, 0.42, 0.41, 0.40, 0.39, 0.38, or 0.37 times the maximum particle size.

[0140] In Figure 23 A particle size distribution plot is provided in FIG. 3. In the plot, the vertical axis is the number of particles on a log scale, and the horizontal axis is the ratio of the particle size to the maximum particle size (Gmax). As shown, one particle 310 in the top portion 210 has the maximum particle size, and no particles 320 or 330 have the maximum particle size. More than one particle 310 and more than one particle 320 have a size of 0.8 times the maximum particle size. More particles 330 have a minimum size of 0.2 times the maximum particle size.

[0141] Without being bound by theory, the free surface, i.e., unconstrained surface, above the opening of the trench 144, results in the formation of large particles 310 in the top portion 210 (as shown in FIG. 3). With a free surface, there is no constraint in at least one direction, allowing for larger particle growth. Figure 19

[0142] ​Further, without being bound by theory, small particles 330 are formed in the middle portion 230 due in part to the large amount of titanium available to form titanium copper alloy from the titanium adhesion layer 158. For example, alloying from copper and titanium occurs at temperatures above 300 °C; thus, in an annealing process performed at a temperature below 300 °C, such as at 400 °C, more titanium copper is formed. In certain embodiments, an annealing process can be performed such that all of the titanium adhesion layer 158 is converted to titanium copper alloy. As the formation of titanium copper alloy increases, the grain growth of copper can be inhibited and smaller particles are formed. Further, the surface of the titanium adhesion layer 158 in contact with the copper can promote small particle growth at selected annealing temperatures, such as in an annealing process performed at 400 °C.

[0143] Further, without being bound by theory, large particles 310 are formed in the bottom portion 220 due in part to the absence or small amount of titanium copper alloy formation. Alloying from copper and titanium nitride occurs at temperatures above 450 °C; thus, in an annealing process performed at a temperature below 450 °C, such as at 400 °C, little to no titanium copper alloy is formed from the titanium nitride barrier layer 156. With little to no titanium copper alloy formation, the grain growth of copper is not inhibited. Further, the surface of the titanium nitride barrier layer 156 forming the trench bottom surface 114 in contact with the copper can promote large particle growth at selected annealing temperatures, such as in an annealing process performed at 400 °C.

[0144] It is noted that the copper grain size growth rate is generally largest at free, unconstrained surfaces and decreases in order at the silicon oxide layer, the titanium nitride layer, the titanium nitride layer, the titanium layer, and finally the titanium layer with the smallest growth rate. Thus, having titanium surrounding the middle portion 230, having titanium nitride at the trench bottom surface 114 in the bottom portion 220, and having the formation of the trench 144 with an open free surface of the top portion 210, provides for the formation of a conductive TSV 200 with a large-small-large grain size distribution as shown in FIG. 1C. Figure 22 More specifically, the top portion 210 can have the largest grain size, or largest average or mean grain size; the bottom portion 220 can have the second largest grain size, or second largest average or mean grain size, and the middle portion 230 can have the smallest grain size or smallest average or mean grain size.

[0145] As described above, prior to the annealing process, the conductive material 164 directly contacts the barrier layer 156 at the trench bottom surface 114 and the conductive material and / or seed layer 162 directly contacts the adhesion layer 158 along the trench sidewall 112. Thus, the formation of titanium copper alloy along the trench sidewall 112 can be more than the formation of titanium copper alloy at the trench bottom surface 114.

[0146] Figure 22 Further, small voids 399 are formed in the middle portion 230. Specifically, after the thermal treatment, the small voids 399 diffuse into the middle portion 230. Thus, unlike the large void formation that can occur in other fabrication processes of the bottom portion 220 and cause delamination, the voids 399 can have little or no impact on device yield.

[0147] Embodiments herein further provide good adhesion between the copper conductive material 164 and the titanium nitride barrier layer 156 at the trench bottom surface 114. Further, embodiments herein use a resputter or ion etch process to increase the coverage of the trench sidewall 112 with titanium material from the adhesion layer 158 removed from the trench bottom surface 114. The increased amount of titanium on the trench sidewall 112 in the bottom portion 220 improves adhesion and reduces delamination. Further, embodiments herein avoid barrier layer failure by using CVD deposited titanium nitride as the barrier layer 156.

[0148] Figure 24 To focus on the trench sidewall 112 and the layers formed thereon prior to performing the anneal process, such as the CVD deposited titanium nitride at the barrier layer 156, a schematic cross-sectional view is shown in FIG. 1C. Figure 16 To focus on the trench sidewall 112 and the layers formed thereon prior to performing the anneal process, such as the CVD deposited titanium nitride at the barrier layer 156, a schematic cross-sectional view is shown in FIG. 1C. Figure 24 To focus on the trench sidewall 112 and the layers formed thereon prior to performing the anneal process, such as the CVD deposited titanium nitride at the barrier layer 156, a schematic cross-sectional view is shown in FIG. 1C. Figure 16 To focus on the trench sidewall 112 and the layers formed thereon prior to performing the anneal process, such as the CVD deposited titanium nitride at the barrier layer 156, a schematic cross-sectional view is shown in FIG. 1C. To focus on the trench sidewall 112 and the layers formed thereon prior to performing the anneal process, such as the CVD deposited titanium nitride at the barrier layer 156, a schematic cross-sectional view is shown in FIG. 1C.

[0149] As shown in FIG. 1G, the insulating layer 152 is formed on the trench sidewall 112, the adhesion layer 154 is formed on the insulating layer 152 and has a thickness T1, the barrier layer 156 is formed on the adhesion layer 154 and has a thickness T2, and the adhesion layer 158 is formed on the barrier layer 156 and has a thickness T3. Figure 24 The thicknesses T1, T2, and T3 can be measured after depositing the layers 154, 156, and 158 and after etching the layer 158 from the trench bottom surface, i.e., after performing operation S960.

[0150] In embodiments herein, the thicknesses T1, T2, and T3 can vary depending on the height of the measurement location relative to the trench bottom surface 114 (or the depth relative to the trench opening 111). It is noted that at the bottom sidewall location 141, the thickness can be measured at a location 5 pm above the trench bottom surface 114 or at a location 10% of the trench height above the trench bottom surface 114. Further, at the top sidewall location 143 adjacent to the trench opening 111, the thickness can be measured at a location 1 pm from the trench opening 111 or at a location 2% of the trench height below the trench opening 111.

[0151]

[0152] For example, at the bottom sidewall location 141 (and in the bottom portion 220 of the conductive via 200), the thickness T1 can be 1 nm to 10 nm, such as 2 nm. At the bottom sidewall location 141, the thickness T1 can be at least 1 nm, at least 1.1 nm, at least 1.2 nm, at least 1.3 nm, at least 1.4 nm, at least 1.5 nm, at least 1.6 nm, at least 1.7 nm, at least 1.8 nm, at least 1.9 nm, or at least 2.0 nm. Further, at the bottom sidewall location 141, the thickness T1 can be at most 10 nm, at most 9 nm, at most 8 nm, at most 7 nm, at most 6 nm, at most 5 nm, at most 4 nm, at most 3.5 nm, at most 3 nm, at most 2.9 nm, at most 2.8 nm, at most 2.7 nm, at most 2.6 nm, at most 2.5 nm, at most 2.4 nm, at most 2.3 nm, at most 2.2 nm, at most 2.1 nm, or at most 2 nm.

[0153] Further, at the bottom sidewall location 141 (and in the bottom portion 220 of the conductive via 200), the thickness T2 can be 15 nm to 40 nm, such as 25 nm. At the bottom sidewall location 141, the thickness T2 can be at least 15 nm, at least 20 nm, at least 21 nm, at least 22 nm, at least 23 nm, at least 24 nm, at least 25 nm, at least 26 nm, at least 27 nm, or at least 30 nm. At the bottom sidewall location 141, the thickness T2 can be at most 40 nm, at most 35 nm, at most 34 nm, at most 33 nm, at most 32 nm, at most 31 nm, at most 30 nm, at most 29 nm, at most 28 nm, at most 27 nm, at most 26 nm, or at most 25 nm.

[0154] Further, at the bottom sidewall location 141 (and in the bottom portion 220 of the conductive via 200), the thickness T3 can be 1 nm to 60 nm. In some embodiments, the thickness T3 at the bottom sidewall location 141 depends on the critical dimension of the trench 144. For example, the thickness T3 at the bottom sidewall location 141 measured in nanometers (nm) can be equal to or greater than 60,000 divided by the lateral critical dimension measured in nanometers (nm), or equal to or greater than 60 divided by the lateral critical dimension measured in micrometers (pm). Thus, for a critical dimension of 1 micrometer to 10 micrometers (pm), the thickness T3 at the bottom sidewall location 141 can be 1 nm to 60 nm. Thus, for a critical dimension of 4 micrometers (pm), the thickness T3 at the bottom sidewall location 141 can be 15 nm.

[0155] In some embodiments, at the bottom sidewall location 141 (and in the bottom portion 220 of the conductive via 200), the thickness T3 can be at least 1 nm, at least 2 nm, at least 3 nm, at least 4 nm, at least 5 nm, at least 6 nm, at least 7 nm, at least 8 nm, at least 9 nm, at least 10 nm, at least 12 nm, at least 14 nm, at least 16 nm, at least 18 nm, at least 20 nm, at least 22 nm, at least 24 nm, at least 26 nm, at least 27 nm, at least 30 nm, at least 32 nm, at least 34 nm, at least 36 nm, at least 38 nm, at least 40 nm, at least 42 nm, at least 44 nm, at least 46 nm, at least 48 nm, at least 50 nm, at least 52 nm, at least 54 nm, at least 56 nm, at least 58 nm, or at least 60 nm. In some embodiments, at the bottom sidewall location 141 (and in the bottom portion 220 of the conductive via 200), the thickness T3 can be at most 80 nm, at most 70 nm, at most 65 nm, at most 60 nm, at most 58 nm, at most 56 nm, at most 54 nm, at most 52 nm, at most 50 nm, at most 48 nm, at most 46 nm, at most 44 nm, at most 42 nm, at most 40 nm, at most 38 nm, at most 36 nm, at most 34 nm, at most 32 nm, at most 30 nm, at most 28 nm, at most 26 nm, at most 24 nm, at most 22 nm, at most 20 nm, at most 18 nm, at most 16 nm, at most 14 nm, at most 12 nm, at most 10 nm, at most 9 nm, at most 8 nm, at most 7 nm, at most 6 nm, at most 5 nm, at most 4 nm, at most 3 nm, at most 2 nm, or at most 1 nm.

[0156] The thicknesses T1, T2, and T3 at the middle or intermediate height sidewall location 142 of the trench 144 (such as in the middle portion 230 of the conductive via 200) are generally greater than the thickness at the trench bottom surface 114.

[0157] For example, at the middle or intermediate height sidewall location 142 (such as in the middle portion 230 of the conductive via 200), the thickness T1 can be 6 nm to 20 nm, such as 12 nm. At the middle or intermediate height sidewall location 142, the thickness T1 can be at least 6 nm, at least 8 nm, at least 9 nm, at least 10 nm, at least 11 nm, at least 12 nm, at least 13 nm, at least 14 nm, or at least 15 nm. Further, at the middle or intermediate height sidewall location 142, the thickness T1 can be at most 20 nm, at most 18 nm, at most 16 nm, at most 15 nm, at most 14 nm, at most 13 nm, at most 12 nm, at most 11 nm, or at most 10 nm.

[0158] Further, at the middle or intermediate height sidewall location 142, the thickness T2 can be 20 nm to 35 nm, such as 27 nm. At the middle or intermediate height sidewall location 142, the thickness T2 can be at least 20 nm, at least 22 nm, at least 24 nm, at least 25 nm, at least 26 nm, or at least 27 nm. Further, at the middle or intermediate height sidewall location 142, the thickness T2 can be at most 35 nm, at most 30 nm, at most 29 nm, at most 28 nm, at most 27 nm, at most 26 nm, or at most 25 nm.

[0159] At the middle or intermediate height sidewall location 142, such as in the middle portion 230 of the conductive via 200, the thickness T3 can be 40 nm to 80 nm, such as 60 nm. At the middle or intermediate height sidewall location 142, the thickness T3 can be at least 40 nm, at least 45 nm, at least 50 nm, at least 55 nm, at least 56 nm, at least 57 nm, at least 58 nm, at least 59 nm, or at least 60 nm. Further, at the middle or intermediate height sidewall location 142, the thickness T3 can be at most 80 nm, at most 75 nm, at most 70 nm, at most 65 nm, at most 64 nm, at most 63 nm, at most 62 nm, at most 61 nm, or at most 60 nm.

[0160] The thicknesses T1, T2, and T3 at the top sidewall location 143, such as in the top portion 210 of the conductive via 200, adjacent to the trench opening 111, are generally greater than the thicknesses at the middle or intermediate height.

[0161] For example, at the top sidewall location 143, such as in the top portion 210 of the conductive via 200, the thickness T1 can be 20 nm to 50 nm, such as 36 nm. At the top sidewall location 143, the thickness T1 can be at least 20 nm, at least 25 nm, at least 30 nm, at least 31 nm, at least 32 nm, at least 33 nm, at least 34 nm, at least 35 nm, or at least 36 nm. At the top sidewall location 143, the thickness T1 can be at most 50 nm, at most 45 nm, at most 40 nm, at most 39 nm, at most 38 nm, at most 37 nm, or at most 36 nm.

[0162] At the top sidewall location 143, the thickness T2 can be 15 nm to 50 nm, such as 30 nm. At the top sidewall location 143, the thickness T2 can be at least 20 nm, at least 25 nm, at least 26 nm, at least 27 nm, at least 28 nm, at least 29 nm, or at least 30 nm. At the top sidewall location 143, the thickness T2 can be at most 50 nm, at most 45 nm, at most 40 nm, at most 35 nm, at most 34 nm, at most 33 nm, at most 32 nm, at most 31 nm, or at most 30 nm.

[0163] At the top sidewall location 143, the thickness T3 can be 100 nm to 300 nm, such as 180 nm. At the top sidewall location 143, the thickness T3 can be at least 100 nm, at least 125 nm, at least 150 nm, at least 175 nm, at least 180 nm, at least 200 nm, or at least 250 nm. At the top sidewall location 143, the thickness T3 can be at most 300 nm, at most 250 nm, at most 225 nm, at most 200 nm, at most 190 nm, at most 180 nm, at most 160 nm, or at most 150 nm.

[0164] Figure 25 to focus on a portion of the copper core 164, the adjacent adhesion layer 158, and the alloy 166 formed by performing the anneal process.

[0165] In particular, Figure 25 The formation of the alloy 166 at the interface of the conductive material 164 and the adhesion layer 158 is described. For example, the titanium copper alloy 166 can be formed between the copper conductive material 164 and the titanium adhesion layer 158. The amount of alloy 166 formed can be controlled using the temperature and duration of the anneal process. In some embodiments, the temperature of the anneal process is 400 °C, and the duration of the anneal process is 30 minutes. In some embodiments, the anneal process is a hydrogen (H2) anneal process, i.e., performed with hydrogen.

[0166] As shown, the adhesion layer 158 is formed with a lateral thickness T3 prior to the anneal process that varies along the height or depth 208 of the trench 144 and between portions 210, 220, and 230. During the anneal process, the alloy 166 is formed with a lateral thickness T4. Each lateral thickness T3 and T4 can vary along the height (or depth) 208 of the trench 144, as shown. As shown, the pre-anneal lateral thickness T3 is greatest near the opening 111 of the trench 144 and is least at or near the trench bottom surface 114. At each height or depth 208 of the trench 144, the pre-anneal thickness T3 is greater than or equal to the thickness T4. In other words, all or less than all of the adhesion layer 158 can be converted to the alloy 166 at each height.

[0167] While Figure 25 While it is described that a portion of the titanium adhesion layer 158 remains after the anneal process, particularly in the top portion 210, it is contemplated that all of the titanium adhesion layer 158 can be converted to the titanium copper alloy 166 such that T4 = T3 in all locations along the height 208 of the conductive TSV 200.

[0168] Referring to FIGS. 1-4 Figure 22 , Figure 24 and Figure 25In an embodiment, the conductive TSV 200 can include an adhesion layer 154 having a bottom sidewall thickness of 2 nanometers (nm), a middle sidewall thickness of 12 nanometers (nm), and a top sidewall thickness of 36 nanometers (nm). The conductive TSV 200 can include a barrier layer 156 having a bottom sidewall thickness of 25 nanometers (nm), a middle sidewall thickness of 27 nanometers (nm), and a top sidewall thickness of 30 nanometers (nm). The conductive TSV 200 can initially be formed with an adhesion layer 158 having a bottom sidewall thickness of 2 nanometers (nm), a middle sidewall thickness of 12 nanometers (nm), and a top sidewall thickness of 36 nanometers (nm). The conductive TSV 200 can include an alloy layer 166 having a bottom sidewall thickness of 15 nanometers (nm), a middle sidewall thickness of 60 nanometers (nm), and a top sidewall thickness of 180 nanometers (nm). In other words, the adhesion layer 158 can be fully converted to the alloy 166 at the bottom sidewall location and the middle height sidewall location, and can be partially converted to the alloy 166 at the top sidewall location, such that the adhesion layer 158 has a remaining top sidewall thickness of 60 nanometers (nm) in the conductive TSV 200.

[0169] While the above embodiment provides for the use of suitable materials to form the conductive TSV 200, the embodiment selects PVD deposited titanium rather than PVD deposited tantalum for each adhesion layer, and selects CVD deposited titanium nitride rather than CVD deposited tantalum nitride or PVD deposited tantalum nitride or PVD deposited titanium nitride for the barrier layer.

[0170] It is noted that each adhesion layer should have good adhesion, and should inhibit grain growth of the conductive material 164 (i.e., copper) by forming an alloy with the conductive material 164. In addition, the material of the adhesion layer should be susceptible to etching, such as with the process of operation S960. PVD deposited titanium has a material density of 4.5 g / cm 3 and a relatively fast Ar etch rate, while materials having a high material density, such as 10 g / cm 3 or more, have a relatively slow Ar etch rate. Thus, with the argon etch process of operation S960 at 10 A / s, PVD deposited titanium has a high etch rate.

[0171] Copper grain inhibition is related to the alloy formation temperature. For example, a lower alloy formation temperature is related to more alloy formation, and inhibits copper grain growth. PVD deposited titanium forms a titanium copper alloy at a relatively low temperature of above 300 °C. In addition, after annealing at 400 °C, titanium promotes the growth of small copper grains on the titanium.

[0172] Metals are better than metal nitrides for adhesion to copper. In addition, titanium is better than tantalum. Furthermore, PVD deposited titanium is better than CVD deposited titanium due to fewer interface defects and impurities. Thus, PVD deposited titanium has good adhesion to copper.

[0173] In addition, PVD deposited titanium provides 1% to 5% sidewall bottom step coverage and 5% to 15% bottom step coverage. PVD deposited titanium has poor barrier properties.

[0174] It should be noted that according to operation S960, the barrier layer should exhibit good barrier properties and good step coverage, and should be easily etched (or resputtered), such as with a PVD process using argon. CVD deposited titanium nitride has a relatively low material density (g / cm 3 ) of 4.5, and has a relatively fast argon etch rate (at

[0175] CVD deposited titanium nitride forms titanium copper alloys at relatively high temperatures above 450°C. In addition, CVD deposited titanium nitride promotes growth of large copper particles on the titanium nitride after annealing at 400°C.

[0176] CVD deposited titanium nitride exhibits poor copper adhesion.

[0177] CVD deposited titanium nitride provides greater than 90% sidewall bottom step coverage and greater than 90% bottom step coverage. CVD deposited titanium nitride has good barrier properties.

[0178] In addition, in some embodiments, the method 900 provides optional formation of a PVD deposited titanium outer adhesion layer 154, formation of a CVD deposited metal nitride barrier layer 156, formation of a PVD deposited metal inner adhesion layer 158, and etching of the inner adhesion layer 158 from the trench bottom surface 114, such as with a PVD argon etch process.

[0179] Certain embodiments are performed without the optional PVD deposited titanium outer adhesion layer 154. In such embodiments, the method includes forming a CVD deposited metal nitride barrier layer 156 on the trench sidewalls 112 and the trench bottom surface 114, forming a PVD deposited metal inner adhesion layer 158, and etching the inner adhesion layer 158 from the trench bottom surface 114, such as with a PVD argon etch process.

[0180] In some embodiments, the method 900 provides formation of a PVD deposited titanium outer adhesion layer 154, formation of a CVD deposited titanium nitride barrier layer 156, formation of a PVD deposited titanium inner adhesion layer 158, and etching of the inner adhesion layer 158 from the trench bottom surface 114, such as with a PVD argon etch process.​

[0181] In one embodiment, the conductive via includes: a first end and a second end; a first portion adjacent to the first end; a second portion adjacent to the second end; and a middle portion between the first portion and the second portion, wherein the conductive via includes metal particles, the metal particles in the first portion have a first particle size; the metal particles in the second portion have a second particle size; the metal particles in the middle portion have a third particle size; the first particle size is greater than the third particle size; and the second particle size is greater than the third particle size.

[0182] In some embodiments, the conductive via has a critical dimension of 1 micrometer to 10 micrometers (pm).

[0183] In some embodiments, the conductive via has an aspect ratio of 5 to 20.

[0184] In some embodiments, the first particle size is greater than the second particle size.

[0185] In some embodiments, the first particle size is a maximum particle size, and wherein the maximum particle size is 200 nanometers to 1000 nanometers (nm).

[0186] In some embodiments, the first end is a height away from the second end; the first portion, the second portion, and the middle portion each have a sub-height equal to 1 / 3 of the height; the first portion has an average particle size greater than 0.5 times the maximum particle size; the second portion has an average particle size greater than 0.5 times the maximum particle size; and the middle portion has an average particle size less than 0.5 times the maximum particle size.

[0187] In some embodiments, the first portion has an average particle size greater than 0.6 times the maximum particle size; the second portion has an average particle size less than 0.6 times the maximum particle size; and the middle portion has an average particle size less than 0.4 times the maximum particle size.

[0188] In another embodiment, a method for forming a metal structure in a trench is provided and includes: depositing a barrier layer along sidewalls and a bottom surface of the trench; depositing a metal layer over the barrier layer, wherein the metal layer forms a vertical thickness over the bottom surface of the trench and a decreasing sidewall thickness along the sidewalls from an opening of the trench toward the bottom surface of the trench; removing the metal layer from the bottom surface of the trench; and forming a metal in the trench.

[0189] In some embodiments, the method further includes: depositing an adhesion layer along sidewalls and a bottom surface of the trench, wherein the barrier layer is deposited over the adhesion layer, and wherein the adhesion layer forms a vertical thickness over the bottom surface of the trench and a decreasing sidewall thickness along the sidewalls from an opening of the trench toward the bottom surface of the trench.

[0190] In some embodiments of the method, the trench has a lateral critical dimension; the adhesion layer has a first lateral thickness (Tl) at a selected height above the bottom surface; the first lateral thickness (Tl) is greater than 2 nanometers (nm); the barrier layer has a second lateral thickness (T2) at the selected height; the second lateral thickness (T2) is greater than 25 nanometers (nm); the metal layer has a third lateral thickness (T3) at the selected height; and the third lateral thickness (T3) measured in nanometers (nm) is greater than or equal to 60,000 divided by the lateral critical dimension measured in nanometers (nm).

[0191] In some embodiments of the method, depositing the adhesion layer includes depositing titanium with a physical vapor deposition (PVD) process; depositing the barrier layer includes depositing titanium nitride with a chemical vapor deposition (CVD) process; depositing the metal layer includes depositing titanium with a physical vapor deposition (PVD) process; and removing the metal layer from the bottom surface of the trench includes performing an ion etch process.

[0192] In some embodiments of the method, removing the metal layer from the bottom surface of the trench includes re-depositing the metal layer material onto the sidewalls of the trench.

[0193] In some embodiments, the method further includes depositing an insulating liner in the trench, wherein depositing the barrier layer includes depositing the barrier layer over the insulating liner.

[0194] In some embodiments of the method, forming the metal in the trench includes: depositing a seed layer over the metal layer; and depositing a metal fill over the seed layer; and the method further includes: performing an anneal process to grow metal grains having a desired grain distribution from the seed layer and the metal fill.

[0195] In another embodiment, a semiconductor device includes a metal interconnect, the metal interconnect including: a copper core; and a titanium copper alloy surrounding the copper core.

[0196] In some embodiments of the semiconductor device, the copper core includes copper grains; the copper core includes a top portion, a bottom portion, and an intermediate portion between the top portion and the bottom portion; the copper grains in the top portion have a first average grain size; the copper grains in the bottom portion have a second average grain size; the copper grains in the intermediate portion have a third average grain size; the first average grain size is greater than the third average grain size; and the second average grain size is greater than the third average grain size.

[0197] In some embodiments of the semiconductor device, the metal interconnect further includes a titanium layer of the titanium copper alloy surrounding the copper core at the top portion.

[0198] In some embodiments of the semiconductor device, the metal interconnect further includes a titanium nitride layer surrounding the titanium copper alloy below the top portion of the copper core and surrounding the titanium layer at the top portion of the copper core.

[0199] In some embodiments of the semiconductor device, the metal interconnect further includes a titanium nitride layer surrounding the titanium copper alloy.

[0200] In some embodiments of the semiconductor device, the metal interconnect further includes an outer titanium layer surrounding the titanium nitride layer.

[0201] In another embodiment, a semiconductor device includes a metal interconnect including: a copper core; a titanium copper alloy surrounding the copper core; and a titanium layer surrounding the titanium copper alloy at a top portion of the copper core. The copper core includes copper particles; the copper core includes a top portion, a bottom portion, and a middle portion between the top portion and the bottom portion; the copper particles in the top portion have a first average particle size; the copper particles in the bottom portion have a second average particle size; the copper particles in the middle portion have a third average particle size; the first average particle size is greater than the third average particle size; and the second average particle size is greater than the third average particle size.

[0202] The foregoing outlines features of several embodiments so that a person of ordinary skill in the art can better understand the various aspects of the disclosure. Those of ordinary skill in the art will readily understand that they can freely combine the features of the various embodiments as the design or modify other processes and structures for implementing the embodiments introduced herein, and / or achieve the same advantages without departing from the spirit and scope of the disclosure. Those of ordinary skill in the art will also realize that they can readily make changes, substitutions and alterations to the methods and structures described herein without departing from the spirit and scope of the disclosure in its broadest form.

Claims

1. An electrically conductive via, characterized by, comprises: a first end and a second end; a first portion adjacent to the first end; a second portion adjacent to the second end; and a middle portion between the first portion and the second portion, wherein the conductive via is composed of a plurality of metal particles, wherein the plurality of metal particles in the first portion have a first particle size; wherein the plurality of metal particles in the second portion have a second particle size; wherein the plurality of metal particles in the middle portion have a third particle size; wherein the first particle size is greater than the third particle size; and wherein the second particle size is greater than the third particle size. wherein the conductive via has a lateral critical dimension of 1 micrometer to 10 micrometers.

2. The conductive via of claim 1, wherein, wherein the conductive via has an aspect ratio of 5 to 20.

3. The conductive via of claim 1, wherein, wherein the first particle size is greater than the second particle size.

4. The conductive via of claim 1, wherein, wherein the first particle size is a maximum particle size, and wherein the maximum particle size is 200 nanometers to 1000 nanometers.

5. The conductive via of claim 1, wherein, wherein:

6. The conductive via of claim 5, wherein, the first end is a distance of a height from the second end; the first portion, the second portion, and the middle portion each have a sub-height equal to 1 / 3 of the height; the first portion has an average particle size greater than 0.5 times the maximum particle size; the second portion has an average particle size greater than 0.5 times the maximum particle size; and the middle portion has an average particle size less than 0.5 times the maximum particle size. wherein:

7. The conductive via of claim 6, wherein, the first portion has an average particle size greater than 0.6 times the maximum particle size; the second portion has an average particle size less than 0.6 times the maximum particle size; and the middle portion has an average particle size less than 0.4 times the maximum particle size. comprises:

8. A semiconductor device, characterized by comprising: a metal interconnect comprising: a copper core, wherein the copper core is composed of a plurality of copper particles; the copper core includes a top portion, a bottom portion, and a middle portion between the top portion and the bottom portion; the plurality of copper particles in the top portion have a first average particle size; the plurality of copper particles in the bottom portion have a second average particle size; the plurality of copper particles in the middle portion have a third average particle size; the first average particle size is greater than the third average particle size; and the second average particle size is greater than the third average particle size; and a titanium-copper alloy surrounding the copper core. wherein the metal interconnect further comprises:

9. The semiconductor device according to claim 8, wherein a titanium nitride layer surrounding the titanium-copper alloy; and an outer titanium layer surrounding the titanium nitride layer. comprises:

10. A semiconductor device, characterized by comprising: a metal interconnect comprising: a copper core, wherein the copper core is composed of a plurality of copper particles; the copper core includes a top portion, a bottom portion, and a middle portion between the top portion and the bottom portion; the plurality of copper particles in the top portion have a first average particle size; the plurality of copper particles in the bottom portion have a second average particle size; the plurality of copper particles in the middle portion have a third average particle size; the first average particle size is greater than the third average particle size; and the second average particle size is greater than the third average particle size; a titanium-copper alloy surrounding the copper core; and ​ a titanium layer surrounding the copper core at the top portion of the copper core. a titanium layer surrounding the copper core at the top portion of the copper core.

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