Bootstrap capacitor initialization circuit with denoising function
By introducing VREF voltage detection, timer, and noise filtering circuits into the bootstrap capacitor initialization circuit, the problem of slow bootstrap circuit response is solved, achieving fast response and efficient charging, making it suitable for high-frequency systems.
Patent Information
- Application Number
- CN202423143837.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-18
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2034-12-18
AI Technical Summary
Existing bootstrap circuits have slow system response times when supplying power to chips on the high side, making them unsuitable for fast-response scenarios.
Design a bootstrap capacitor initialization circuit with noise reduction function, including a VREF voltage detection circuit, a timer circuit and a noise filtering circuit. By forcibly turning on the low-side power transistor, the bootstrap capacitor is charged to a certain voltage when the system is powered on, thereby improving the response speed. The charging time is calculated by the timer circuit, and the noise filtering circuit reduces the noise impact during the power-on process.
It improves the system's response speed and bootstrap capacitor charging efficiency, reduces logic confusion and noise during power-on, and is suitable for high-frequency systems.
Smart Images
Figure CN223843762U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor integrated circuits, and in particular to a bootstrap capacitor initialization circuit with noise reduction function. Background Technology
[0002] Currently, in switching power supply circuits, bootstrap capacitors are commonly used to power the drive module of the switching transistor. A bootstrap capacitor utilizes the characteristic that the voltage across a capacitor cannot change abruptly. When a certain voltage is maintained across the capacitor, increasing the voltage at the negative terminal will not change the voltage at the positive terminal, which remains at the original voltage difference at the negative terminal. This is equivalent to the voltage at the positive terminal being "lifted up" by the negative terminal; it is essentially a positive feedback capacitor used to raise the supply voltage. A bootstrap capacitor is a bootstrap circuit.
[0003] Because when using a bootstrap circuit to power a chip on the high side, the bootstrap capacitor can only be charged after power-on and when the low-side signal arrives, the system response time is slow, making it unsuitable for fast-response scenarios.
[0004] In view of this, it is necessary to propose further improvements to the current structure. Utility Model Content
[0005] Therefore, the purpose of this utility model is to at least partially solve the shortcomings of the prior art, thereby proposing a bootstrap capacitor initialization circuit with noise reduction function.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] This invention provides a bootstrap capacitor initialization circuit with noise reduction function, including a VREF voltage detection circuit, a timer circuit, and a noise filtering circuit. The VREF voltage detection circuit is connected to the timer circuit, and the timer circuit is also connected to the noise filtering circuit.
[0008] Furthermore, the VREF voltage detection circuit includes a VREF terminal, an output terminal A, a first IB terminal, a GND terminal, a first PM transistor, a second PM transistor, a third PM transistor, a first NM transistor, a second NM transistor, a first diode, and a second diode;
[0009] The VREF terminal is connected to the drain (d) terminal of the first PM transistor, the drain (d) terminal of the second PM transistor, and the timer circuit; the g terminal is connected to the g terminal of the second PM transistor and the drain (d) terminal of the third PM transistor; and the s terminal is connected to the drain (d) terminal of the third PM transistor.
[0010] The gate (g) of the second PM transistor is also connected to the d (d) of the third PM transistor, and the s (s) is connected to the output terminal A and the d of the second NM transistor.
[0011] The gate (g) and source (s) terminals of the third PM transistor are connected to each other and to the first diode; the first diode is also connected to the second diode, which is connected to the drain (d) terminal of the first NM transistor.
[0012] The gate (g) of the first NM transistor is connected to the first IB terminal, and the source (s) is connected to the GND terminal and the source (s) of the second NM transistor, as well as the timer circuit and the noise filter circuit.
[0013] The drain (d) terminal of the second NM transistor is connected to the output terminal A, the g terminal is connected to the first IB terminal, and the s terminal is also connected to the GND terminal, the timer circuit, and the noise filter circuit. The output terminal A is also connected to the timer circuit.
[0014] Furthermore, when the voltage at the VREF terminal increases but is less than the preset threshold value of the first VT, the first NM transistor, the second NM transistor, the first PM transistor, and the second PM transistor are turned on, and the output terminal A of the VREF voltage detection circuit becomes the GND terminal; when the voltage at the VREF terminal is greater than the preset threshold value of the first VT, the output terminal A of the VREF voltage detection circuit becomes the VREF terminal.
[0015] Furthermore, the timer circuit includes a second IB terminal, an output terminal B, a third NM transistor, a fourth PM transistor, a fifth PM transistor, and a first capacitor;
[0016] The d-terminal of the fourth PM tube is connected to the VREF terminal, the d-terminal of the first PM tube, and the d-terminal of the second PM tube; the g-terminal is connected to the second IB terminal; and the s-terminal is connected to the d-terminal of the third NM tube.
[0017] The gate (g) of the third NM transistor is connected to the gate (g) of the output terminal A and the gate (s) of the fifth PM transistor, and the source (s) is also connected to the output terminal B.
[0018] The output terminal B is also connected to the drain of the fifth PM transistor, the first capacitor, and the noise filtering circuit;
[0019] The gate (g) of the fifth PM transistor is also connected to the output terminal A, and the source (s) is also connected to the first capacitor, the source (s) of the second NM transistor, the source (s) of the first NM transistor, the GND terminal, and the noise filtering circuit.
[0020] The first capacitor is also connected to the noise filtering circuit.
[0021] Furthermore, when the voltage at the VREF terminal exceeds the preset threshold first VT value, the third NM transistor is turned on, the fifth PM transistor is turned off, and the output terminal B charges the first capacitor through the fourth PM transistor until the voltage at the VREF terminal reaches the preset threshold second VT value.
[0022] Furthermore, the noise filtering circuit includes an OUT terminal, a second capacitor, a Schmitt trigger, and a NOT gate. The Schmitt trigger is connected to the NOT gate, the second capacitor, the output terminal B, and the first capacitor. The NOT gate is also connected to the second capacitor and the OUT terminal. The second capacitor is also connected to the first capacitor, the source terminal of the fifth PM transistor, the source terminal of the second NM transistor, the source terminal of the first NM transistor, and the GND terminal.
[0023] Furthermore, when the first capacitor is charged to the preset threshold value (second VT), the OUT terminal flips to the VREF terminal.
[0024] Furthermore, the second capacitor is a capacitor to ground.
[0025] This invention provides a bootstrap capacitor initialization circuit with noise reduction function, including a VREF voltage detection circuit, a timer circuit, and a noise filtering circuit. The VREF voltage detection circuit is connected to the timer circuit, and the timer circuit is also connected to the noise filtering circuit. This bootstrap capacitor initialization circuit with noise reduction function is used to force the low-side power transistor to turn on when the electrode drive system power supply is powered on, allowing the bootstrap capacitor to charge to a certain voltage, thereby improving the system's response speed and increasing the bootstrap capacitor charging efficiency after power-on. It can be applied to systems with higher operating frequencies. The VREF voltage detection circuit can provide a fixed signal for the high and low side outputs during chip power-on, avoiding logic confusion such as uncertain states. The timer circuit can calculate the bootstrap capacitor charging time, and the noise filtering circuit can reduce the impact of overshoot voltage and noise during power-on, improving reliability. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0027] Figure 1 This is a circuit diagram of the bootstrap capacitor initialization circuit with noise reduction function of this utility model.
[0028] Figure 2 The waveform diagram shows the working process of the bootstrap capacitor initialization circuit with noise reduction function of this utility model. Detailed Implementation
[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0030] It should be noted that the descriptions involving "first," "second," etc., in this utility model are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.
[0031] Please refer to Figure 1 and Figure 2 This utility model provides a bootstrap capacitor initialization circuit with noise reduction function, including a VREF voltage detection circuit, a timer circuit and a noise filtering circuit. The VREF voltage detection circuit is connected to the timer circuit, and the timer circuit is also connected to the noise filtering circuit.
[0032] Because chips using bootstrap circuits to power the high side typically only charge the bootstrap capacitor after power-on and upon the arrival of the low-side signal, the system response time is slow, making it unsuitable for fast-response scenarios. However, the bootstrap capacitor initialization circuit with noise reduction in this embodiment forces the low-side power transistor to power on when the electrode-driven system power supply is turned on, allowing the bootstrap capacitor to charge to a certain voltage, thereby improving the system response speed and increasing the bootstrap capacitor charging efficiency after power-on. This allows for application in systems with higher operating frequencies. The VREF voltage detection circuit provides a fixed signal for the high and low-side outputs during chip power-on, avoiding logical confusion such as uncertain states. The timer circuit calculates the bootstrap capacitor charging time, and the noise filtering circuit reduces the impact of overshoot voltage and noise during power-on, improving reliability.
[0033] Furthermore, the VREF voltage detection circuit includes a VREF terminal, an output terminal A, a first IB terminal, a GND terminal, a first PM transistor PM1, a second PM transistor PM2, a third PM transistor PM3, a first NM transistor NM1, a second NM transistor NM2, a first diode D1, and a second diode D2.
[0034] The VREF terminal is connected to the drain of the first PM transistor PM1, the drain of the second PM transistor PM2, and the timer circuit. The gate terminal is connected to the gate of the second PM transistor PM2 and the drain of the third PM transistor PM3. The s terminal is connected to the drain of the third PM transistor PM3.
[0035] The gate (g) of the second PM tube PM2 is also connected to the d (d) of the third PM tube PM3, and the s (s) is connected to the output terminal A and the d of the second NM tube NM2.
[0036] The gate (g) and source (s) terminals of the third PM transistor PM3 are connected to each other and to the first diode D1; the first diode D1 is also connected to the second diode D2, which is connected to the drain (d) terminal of the first NM transistor NM1.
[0037] The gate of the first NM transistor NM1 is connected to the first IB terminal, and the source is connected to the GND terminal. The source of the second NM transistor NM2 is connected to the timer circuit and the noise filter circuit.
[0038] The drain of the second NM transistor NM2 is connected to the output terminal A, the g terminal is connected to the first IB terminal, and the s terminal is also connected to the GND terminal, the timer circuit, and the noise filter circuit. The output terminal A is also connected to the timer circuit.
[0039] In this embodiment, the NM transistor is an NMOS field-effect transistor, which has an N-type channel and a P-type substrate with the substrate connected to the lowest potential; the PM transistor is a PMOS field-effect transistor, which has a P-type channel and an N-type substrate connected to the highest potential.
[0040] Furthermore, when the voltage at the VREF terminal increases but is less than the preset threshold value of the first VT, the first NM transistor, the second NM transistor, the first PM transistor, and the second PM transistor are turned on, and the output terminal A of the VREF voltage detection circuit is the GND terminal; when the voltage at the VREF terminal is greater than the preset threshold value of the first VT, the output terminal A of the VREF voltage detection circuit is the VREF terminal.
[0041] In this embodiment, as the VREF terminal voltage increases but is less than the preset threshold value of the first VT, the first NM transistor NM1, the second NM transistor NM2, the first PM transistor PM1, and the second PM transistor PM2 are all turned on. At this time, since there are voltage drops in the diode-connected MOS transistor third PM transistor PM3, the first diode D1, and the second diode D2, the first NM transistor NM1 operates in the linear region, while the second NM transistor NM2 operates in the saturation region. Therefore, the output terminal A of the VREF voltage detection circuit is the GND terminal.
[0042] As the VREF terminal voltage continues to rise until it exceeds the preset threshold value of the first VT, the current in the first NM transistor NM1 also continues to increase until the current in the first NM transistor NM1 exceeds the current in the second NM transistor NM2. After current replication by the current mirror, the output of the VREF voltage detection circuit flips from the original GND terminal to the VREF terminal. Different preset threshold values of the first VT can be set by adjusting the aspect ratio of the multiple NMOS and PMOS transistors in the VREF voltage detection circuit, and by adjusting the number of the first diode D1 and the second diode D2 connected in series. In this embodiment, the current mirror is specifically composed of the first PM transistor PM1 and the second PM transistor PM2, and is used to replicate the current.
[0043] Furthermore, the timer circuit includes a second IB terminal, an output terminal B, a third NM transistor NM3, a fourth PM transistor PM4 and a fifth PM transistor PM5, and a first capacitor C1;
[0044] The d-terminal of the fourth PM tube PM4 is connected to the VREF terminal, the d-terminal of the first PM tube PM1, the d-terminal of the second PM tube PM2, the g-terminal is connected to the second IB terminal, and the s-terminal is connected to the d-terminal of the third NM tube NM3.
[0045] The gate of the third NM transistor NM3 is connected to the gate of the fifth PM transistor PM5, and the source is also connected to the output terminal B.
[0046] Output terminal B is also connected to the drain of the fifth PM transistor PM5, the first capacitor C1, and the noise filter circuit;
[0047] The gate of the fifth PM transistor PM5 is also connected to the output terminal A, and the source is also connected to the first capacitor C1, the source of the second NM transistor NM2, the source of the first NM transistor NM1, the GND terminal, and the noise filter circuit.
[0048] The first capacitor C1 is also connected to a noise filtering circuit.
[0049] Furthermore, when the voltage at the VREF terminal exceeds the preset threshold value of the first VT, the third NM transistor NM3 is turned on, the fifth PM transistor PM5 is turned off, and the output terminal B charges the first capacitor C1 through the fourth PM transistor PM4 until the voltage at the VREF terminal reaches the preset threshold value of the second VT.
[0050] In this embodiment, when the voltage at the VREF terminal rises above the preset threshold value VT, the third NM transistor NM3 turns on and the fifth PM transistor PM5 turns off. The timer circuit then outputs to output terminal B and charges the first capacitor C1 through the fourth PM transistor PM4 until the voltage at the VREF terminal reaches the preset threshold value VT2. The time taken for the voltage at the VREF terminal to rise from the preset threshold value VT2 to the VT2 threshold voltage is the turn-on time of the lower power transistor. The lower power transistor is the lower bridge drive power transistor in the half-bridge drive. When the lower power transistor is turned on, it ensures that the bootstrap capacitor can store sufficient charge for use when the upper power transistor is turned on. The function of the fifth PM transistor PM5 is to discharge the charge on the first capacitor C1 to ground after the power supply of the bootstrap capacitor initialization circuit with noise cancellation function is turned off. The timer circuit can obtain the required time by changing the capacitance value of the first capacitor C1.
[0051] Furthermore, the noise filtering circuit includes an OUT terminal, a second capacitor C2, a Schmitt trigger U, and a NOT gate N. The Schmitt trigger U is connected to the NOT gate N, the second capacitor C2, the output terminal B, and the first capacitor C1. The NOT gate N is also connected to the second capacitor C2 and the OUT terminal. The second capacitor C2 is also connected to the first capacitor C1, the source terminal of the fifth PM transistor PM5, the source terminal of the second NM transistor NM2, the source terminal of the first NM transistor NM1, and the GND terminal.
[0052] Furthermore, when the first capacitor C1 is charged to the preset threshold value of the second VT, the OUT terminal flips to the VREF terminal.
[0053] In this embodiment, when the first capacitor C1 of the timer circuit charges to the preset threshold value of the second VT, the output of the noise filtering circuit will switch from the output OUT terminal to the VREF terminal in the VREF voltage detection circuit. At this time, the bootstrap capacitor initialization circuit with noise reduction function will be turned off. Since the output signal of the timer circuit is an analog signal, there will be noise signals during signal transmission. Therefore, the noise filtering circuit needs to convert the analog signal into a digital signal for subsequent transmission. The noise filtering circuit uses a Schmitt trigger U and a second capacitor C2, where the second capacitor C2 is a capacitor to ground. The Schmitt trigger U is an inverter with hysteresis function, which has good noise immunity characteristics. It is connected to a NOT gate N, which can drive the Schmitt trigger U and obtain a signal that is inverted from the output B. At the same time, the second capacitor C2 can filter the output of the Schmitt trigger U, thus improving the noise immunity performance of the noise filtering circuit. The noise immunity can be changed by adjusting the size of the Schmitt trigger and the size of the second capacitor C2 according to actual needs.
[0054] Furthermore, the specific steps of the bootstrap capacitor initialization circuit with noise reduction function in the embodiments of this application are as follows:
[0055] When the voltage at the VREF terminal of the VREF voltage detection circuit rises, if the voltage at the VREF terminal is below the preset threshold value VT, the output of output terminal A of the VREF voltage detection circuit is GND. If the voltage at the VREF terminal rises above the preset threshold value VT, the output of the VREF voltage detection circuit flips from GND to VREF. At this time, the output terminal B of the timer circuit charges the first capacitor C1 through the fourth PM transistor PM4. The time taken for the voltage at the VREF terminal to rise from the preset threshold value VT to the VT2 threshold voltage is the turn-on time of the lower power transistor, ensuring that the bootstrap capacitor can store enough charge for use when the upper power transistor is turned on. When the first capacitor C1 in the timer circuit is charged to the preset threshold value VT, the output of the noise filter circuit will flip from the output OUT terminal to the VREF terminal in the VREF voltage detection circuit. At this time, the bootstrap capacitor initialization circuit with noise reduction function will be turned off, and the charge on the first capacitor C1 in the timer circuit will be discharged to ground.
[0056] The advantages of this application embodiment through the above steps are as follows:
[0057] 1. It can provide a fixed signal for the high and low side outputs during chip power-up, avoiding logic confusion such as uncertain states;
[0058] 2. When the motor drive system is powered on, the low-side power transistor is forcibly turned on for a period of time to charge the bootstrap capacitor to a certain voltage, thereby improving the system's response speed.
[0059] 3. Reduce the impact of process voltage and noise during power-on, and improve reliability;
[0060] 4. Improves the charging efficiency of the bootstrap capacitor after power-on, making it applicable to systems with higher operating frequencies.
[0061] This invention provides a bootstrap capacitor initialization circuit with noise reduction function, including a VREF voltage detection circuit, a timer circuit, and a noise filtering circuit. The VREF voltage detection circuit is connected to the timer circuit, and the timer circuit is also connected to the noise filtering circuit. This bootstrap capacitor initialization circuit with noise reduction function is used to force the low-side power transistor to turn on when the electrode drive system power supply is powered on, allowing the bootstrap capacitor to charge to a certain voltage, thereby improving the system's response speed and the charging efficiency of the bootstrap capacitor after power-on. It can be applied to systems with higher operating frequencies. The VREF voltage detection circuit can provide a fixed signal for the high and low side outputs during chip power-on, avoiding logic confusion such as uncertain states. The timer circuit can calculate the charging time of the bootstrap capacitor, and the noise filtering circuit can reduce the impact of overshoot voltage and noise during power-on, improving reliability.
[0062] It should be noted that the various embodiments in this utility model are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0063] It should also be noted that, in the present invention, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0064] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined in the present invention may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A bootstrap capacitor initialization circuit with noise reduction function, characterized in that, It includes a VREF voltage detection circuit, a timer circuit, and a noise filtering circuit. The VREF voltage detection circuit is connected to the timer circuit, and the timer circuit is also connected to the noise filtering circuit. The VREF voltage detection circuit includes a VREF terminal, an output terminal A, a first IB terminal, a GND terminal, a first PM transistor, a second PM transistor, a third PM transistor, a first NM transistor, a second NM transistor, a first diode, and a second diode. The VREF terminal is connected to the drain (d) terminal of the first PM transistor, the drain (d) terminal of the second PM transistor, and the timer circuit; the g terminal is connected to the g terminal of the second PM transistor and the drain (d) terminal of the third PM transistor; and the s terminal is connected to the drain (d) terminal of the third PM transistor. The gate (g) of the second PM transistor is also connected to the d (d) of the third PM transistor, and the s (s) is connected to the output terminal A and the d of the second NM transistor. The gate (g) and source (s) terminals of the third PM transistor are connected to each other and to the first diode; the first diode is also connected to the second diode, which is connected to the drain (d) terminal of the first NM transistor. The gate (g) of the first NM transistor is connected to the first IB terminal, and the source (s) is connected to the GND terminal and the source (s) of the second NM transistor, as well as the timer circuit and the noise filter circuit. The drain (d) terminal of the second NM transistor is connected to the output terminal A, the g terminal is connected to the first IB terminal, and the s terminal is also connected to the GND terminal, the timer circuit, and the noise filter circuit. The output terminal A is also connected to the timer circuit.
2. The bootstrap capacitor initialization circuit with noise reduction function according to claim 1, characterized in that, When the voltage at the VREF terminal increases but is less than the preset threshold value of the first VT, the first NM transistor, the second NM transistor, the first PM transistor, and the second PM transistor are turned on, and the output terminal A of the VREF voltage detection circuit is the GND terminal; when the voltage at the VREF terminal is greater than the preset threshold value of the first VT, the output terminal A of the VREF voltage detection circuit is the VREF terminal.
3. The bootstrap capacitor initialization circuit with noise reduction function according to claim 2, characterized in that, The timer circuit includes a second IB terminal, an output terminal B, a third NM transistor, a fourth PM transistor, a fifth PM transistor, and a first capacitor; The d-terminal of the fourth PM tube is connected to the VREF terminal, the d-terminal of the first PM tube, and the d-terminal of the second PM tube; the g-terminal is connected to the second IB terminal; and the s-terminal is connected to the d-terminal of the third NM tube. The gate (g) of the third NM transistor is connected to the gate (g) of the output terminal A and the gate (s) of the fifth PM transistor, and the source (s) is also connected to the output terminal B. The output terminal B is also connected to the drain of the fifth PM transistor, the first capacitor, and the noise filtering circuit; The gate (g) of the fifth PM transistor is also connected to the output terminal A, and the source (s) is also connected to the first capacitor, the source (s) of the second NM transistor, the source (s) of the first NM transistor, the GND terminal, and the noise filtering circuit. The first capacitor is also connected to the noise filtering circuit.
4. The bootstrap capacitor initialization circuit with noise reduction function according to claim 3, characterized in that, When the voltage at the VREF terminal exceeds the preset threshold value of the first VT, the third NM transistor is turned on, the fifth PM transistor is turned off, and the output terminal B charges the first capacitor through the fourth PM transistor until the voltage at the VREF terminal reaches the preset threshold value of the second VT.
5. The bootstrap capacitor initialization circuit with noise reduction function according to claim 4, characterized in that, The noise filtering circuit includes an OUT terminal, a second capacitor, a Schmitt trigger, and a NOT gate. The Schmitt trigger is connected to the NOT gate, the second capacitor, the output terminal B, and the first capacitor. The NOT gate is also connected to the second capacitor and the OUT terminal. The second capacitor is also connected to the first capacitor, the source terminal of the fifth PM transistor, the source terminal of the second NM transistor, the source terminal of the first NM transistor, and the GND terminal.
6. The bootstrap capacitor initialization circuit with noise reduction function according to claim 5, characterized in that, When the first capacitor is charged to the preset threshold value of the second VT, the OUT terminal flips to the VREF terminal.
7. The bootstrap capacitor initialization circuit with noise reduction function according to claim 5, characterized in that, The second capacitor is a capacitor to ground.