Display substrate and display device
By introducing a low-resistivity first signal line portion into the gate signal line and performing jumper insulation treatment, the signal attenuation and delay problems caused by the increase in the length of the vehicle screen are solved, the display quality is improved and electrostatic damage is prevented.
Patent Information
- Application Number
- CN202520006977.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-01-02
AI Technical Summary
As the length of the in-vehicle screen increases, the resistance of the gate signal line increases, leading to signal attenuation and delay, which causes display abnormalities.
A first signal line section with lower resistivity is introduced into the gate signal line and connected to the original signal line through a via. The overlapping part of the data signal lines is increased and jumper insulation is performed to reduce the resistance of the gate signal line and improve the signal transmission quality.
It effectively reduces the resistance of the gate signal line, reduces signal attenuation and delay, improves abnormal display problems on the display screen, and reduces static electricity accumulation to prevent transistor damage.
Smart Images
Figure CN223844149U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology
[0002] With the continuous development of the LCD industry, display product forms are becoming increasingly diverse. In order to improve the user experience, all types of display products are trending towards larger sizes, with automotive screens being the most prominent example. Automotive screens are mostly designed in landscape mode, and as automotive screens develop, they are gradually becoming integrated. This results in the length of automotive screens becoming longer and longer. Correspondingly, the resistance of the gate signal lines becomes larger and larger. The gate signal transmitted through the gate signal lines will experience attenuation and delay, leading to abnormal display problems on the screen. Utility Model Content
[0003] The purpose of this utility model embodiment is to provide a display substrate and display device to improve the abnormal display problem of the display screen. The specific technical solution is as follows:
[0004] In a first aspect, embodiments of the present invention provide a display substrate, the display substrate comprising:
[0005] Gate signal line layer, source / drain electrode layer;
[0006] The gate signal line layer includes a second signal line portion of the gate signal line, and the source / drain electrode layer includes a first signal line portion of the gate signal line.
[0007] In the same gate signal line, the second signal line portion in the gate signal line layer is connected to the first signal line portion in the source / drain electrode layer through a first via;
[0008] The resistivity of the material in the first signal line portion is less than the resistivity of the material in the second signal line portion;
[0009] The gate signal line layer further includes a fourth signal line portion of the data signal line, and the source / drain electrode layer further includes a third signal line portion of the data signal line;
[0010] In the same data signal line, the adjacent third signal line portion and the fourth signal line portion are connected through a second via;
[0011] The third signal line portion and the first signal line portion have no overlapping portions in their orthographic projections on the array substrate of the display substrate, while the fourth signal line portion and the first signal line portion have overlapping portions in their orthographic projections on the array substrate.
[0012] In one possible implementation, the same gate signal line includes multiple second signal line portions and a first signal line portion, and each of the second signal line portions of the same gate signal line is connected to the first signal line portion through a first via.
[0013] In one possible implementation,
[0014] In the column direction of the display substrate, the first width of the first signal line portion is smaller than the second width of the first signal line portion; wherein, the first width is the width at the position where the projection of the first signal line portion overlaps with that of the fourth signal line portion, and the second width is the width of the portion of the first signal line portion that does not overlap with that of the fourth signal line portion.
[0015] In one possible implementation,
[0016] The i-th second signal line portion of the Nth gate signal line corresponds to the i-th sub-pixel in the Nth row of pixel units;
[0017] or,
[0018] The i-th second signal line portion of the Nth gate signal line corresponds to the 2i-1th and 2ith sub-pixels in the Nth row of pixel units;
[0019] or,
[0020] The i-th second signal line portion of the Nth gate signal line corresponds to the 3i-2, 3i-1, and 3i-th sub-pixels in the Nth row of pixel units;
[0021] Where N is an integer not less than 1, and i is an integer not less than 1.
[0022] In one possible implementation,
[0023] In the column direction of the display substrate, a preset distance is provided between the drain of the data writing transistor of each sub-pixel in the Nth row pixel unit and the Nth gate signal line.
[0024] In one possible implementation,
[0025] In the row direction of the display substrate, a data writing transistor is provided for each sub-pixel, and the drain and source of the data writing transistor are arranged on both sides of its gate.
[0026] In one possible implementation,
[0027] In the column direction of the display substrate, a data writing transistor is provided for each sub-pixel, and the drain and source of the data writing transistor are arranged on one side of its gate.
[0028] In one possible implementation,
[0029] In the column direction of the display substrate, a data writing transistor is provided for each sub-pixel, with the drain and source of the data writing transistor arranged on both sides of its gate.
[0030] In one possible implementation, the display substrate further includes: an array substrate, a first insulating layer, an active layer, a second insulating layer, and a third insulating layer;
[0031] The first insulating layer is disposed on the array substrate, the active layer is disposed on the side of the first insulating layer away from the array substrate, the second insulating layer is disposed on the side of the active layer away from the array substrate, the gate signal line layer is disposed on the side of the second insulating layer away from the array substrate, the third insulating layer is disposed on the side of the gate signal line layer away from the array substrate, and the source / drain electrode layer is disposed on the side of the third insulating layer away from the array substrate.
[0032] In a second aspect, embodiments of the present invention provide a display device, the display device comprising a display substrate as described in any of the first aspects.
[0033] The beneficial effects of this utility model embodiment are as follows:
[0034] This utility model provides a display substrate and a display device. The display substrate includes: a gate signal line layer and a source / drain electrode layer; the gate signal line layer includes a second signal line portion of the gate signal line, and the source / drain electrode layer includes a first signal line portion of the gate signal line; in the same gate signal line, the second signal line portion in the gate signal line layer is connected to the first signal line portion in the source / drain electrode layer through a first via; the resistivity of the material of the first signal line portion is less than that of the material of the second signal line portion; the gate signal line layer also includes a fourth signal line portion of the data signal line, and the source / drain electrode layer also includes a third signal line portion of the data signal line; in the same data signal line, adjacent third signal line portions and fourth signal line portions are connected through second vias; the orthographic projections of the third signal line portion and the first signal line portion on the array substrate of the display substrate do not overlap, while the orthographic projections of the fourth signal line portion and the first signal line portion on the array substrate do overlap. By incorporating the first signal line portion into the gate signal line, compared to related technologies where the gate signal line is formed solely from the material of the second signal line portion, the resistance of the gate signal line can be reduced, gate signal attenuation and delay can be improved, and abnormal display problems on the display screen can be mitigated. Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above simultaneously. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings.
[0036] Figure 1a This is a schematic diagram of the first structure of a display panel in the related technology;
[0037] Figure 1b This is a schematic diagram of a second structure for a display panel in related technologies;
[0038] Figure 2 This is a waveform diagram illustrating gate signal attenuation in related technologies.
[0039] Figure 3a This is a top view schematic diagram of a display substrate structure in related technologies;
[0040] Figure 3b This is a schematic diagram of a stacked structure of a display substrate in related technologies;
[0041] Figure 4a This is a first top view schematic diagram of a display substrate provided in an embodiment of the present utility model;
[0042] Figure 4b for Figure 4a The diagram shows the stacking structure of the structure shown in the AA' direction;
[0043] Figure 4c for Figure 4a The diagram shows the stacking structure of the structure shown in the BB' direction;
[0044] Figure 5 This is a second top view schematic diagram of the display substrate provided in an embodiment of the present utility model;
[0045] Figure 6 This is a third top view schematic diagram of the display substrate provided in an embodiment of the present utility model;
[0046] Figure 7 A schematic diagram of a stacked structure of a display substrate provided in an embodiment of this utility model;
[0047] Figure 8 This is a schematic diagram of a display device provided in an embodiment of the present utility model. Detailed Implementation
[0048] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art based on the present utility model are within the protection scope of the present utility model.
[0049] With the continuous development of the LCD industry, display product forms are becoming increasingly diverse. In order to improve the user experience, all types of display products are trending towards larger sizes, with automotive screens being the most prominent example. Automotive screens are mostly designed in landscape mode, and as automotive screens develop, they are gradually becoming integrated. This results in the length of automotive screens becoming longer and longer. Correspondingly, the resistance of the gate signal lines becomes larger and larger. The gate signal transmitted through the gate signal lines will experience attenuation and delay, leading to abnormal display problems on the screen.
[0050] Specifically, such as Figure 1a and Figure 1b As shown, the gate signal lines of the liquid crystal display panel are designed in the row direction and controlled by the GOA (Gate Driver on Array) circuit, scanning row by row. The data signal lines of the liquid crystal display panel are designed in the column direction. Typically, when the corresponding row gate signal line is turned on, the data write transistors of each sub-pixel in that row are turned on. The data signal from the data signal line is written to the pixel electrode through the data write transistors. A voltage difference exists between the storage capacitor formed by the pixel electrode and the common electrode, charging the storage capacitor. The corresponding liquid crystal in the pixel deflects, and light is transmitted through the back panel for display on the screen. Therefore, as the screen length increases, the resistance of the gate signal lines increases, causing attenuation and delay in the gate signal transmitted through the gate signal lines. Figure 2 As shown, this can lead to insufficient driving of the data writing transistors for subpixels, meaning the transistors are not effectively turned on, resulting in uneven and abnormal display problems on the screen.
[0051] To ensure good image quality on horizontal displays, reducing the resistance of the gate signal lines is crucial. According to the formula R=ρ×L / S (where ρ is the material resistivity, L is the material length, S is the material cross-sectional area, and R is the material resistance), common methods to reduce the resistance of the gate signal lines include reducing the material resistivity, reducing the trace length, and increasing the trace cross-sectional area. However, all of these methods have limitations. Changing the material of the gate signal lines may increase process complexity and cost; reducing the length of the gate signal lines is limited by the size of the display product; and increasing the cross-sectional area of the gate signal lines is limited by the characteristics of the display product and the pixel aperture ratio.
[0052] Taking an NMOS (Metal-Oxide-Semiconductor Field-Effect Transistor) pixel structure, where the source and drain of the transistor are located on the left and right sides of its own gate, as an example, the sub-pixels in the display area of the display panel are arranged in an array, and the gate signal lines and data signal lines intersect perpendicularly. (See [reference needed]). Figure 3a The sub-pixel's gate and gate signal lines use the same material, achieving an "integrated" connection. The resistivity of the sub-pixel gate material cannot be too low. The data signal lines, however, use a different material. To optimize pixel charging, the resistivity of the data signal line material is significantly lower than that of the gate signal line material. The sub-pixel employs a top-gate structure; see [reference needed]. Figure 3b The gate and gate signal lines (located on the gate signal line layer) are situated above the active layer, while the data signal lines (located on the source / drain electrode layers) are situated above the gate signal lines. An insulating layer separates the gate signal lines and data signal lines. This insulating layer, besides its insulating function, also determines the color of the display panel and is typically made of SiN. X The stacked structure formed by silicon nitride and SiO2 (silicon dioxide) has a thickness of about 5000 angstroms (angstrom is a unit of thickness, 1 nanometer = 10 angstroms), so the flatness effect is limited. In order to reduce the risk of breakage of the data signal line at the intersection with the gate signal line, the thickness of the gate signal line cannot be made very thick.
[0053] Meanwhile, the gate signal line is formed using wet etching. The bias created by wet etching forms the LDD (Lightly Doped Drain) channel of the NMOS. For device robustness, the channel length of the LDD channel must be at least 0.75 micrometers. The channel length of the LDD channel limits the thickness of the gate signal line (the greater the thickness, the greater the bias, and the smaller the channel length). In order to form the correct transistor size, the thickness of the gate signal line cannot be made very thick, generally around 3000 angstroms.
[0054] In summary, due to limitations in material resistivity, thickness, and display product size, the resistance of the gate signal line is relatively fixed. For example, for a 16-inch landscape screen, the resistance of the gate signal line can be tens of kilohms, which is very detrimental to pixel charging. In contrast, the resistance of the data signal line of the same size is much lower, approximately 0.133% of that of the gate signal line. However, if the materials of the gate signal line and data signal line were interchanged, pixel charging would be even worse, approaching a passive state.
[0055] On the other hand, the entire gate signal line of the display area of the display panel has a "high resistance long trace" structure. During the manufacturing process and subsequent product use, there may be problems with static electricity accumulation and slow static electricity discharge. When the static electricity cannot be fully discharged, it may cause transistor damage, which in turn causes a variety of problems.
[0056] In order to reduce the resistance of the gate signal line and improve the abnormal display problem of the display screen, this utility model provides a display substrate and a display device.
[0057] Next, the display substrate provided in the embodiments of this utility model will be described in detail. See [link to relevant documentation]. Figure 4a , Figure 4b and Figure 4c , Figure 4a This is a first top view of the display substrate 1 provided in an embodiment of the present invention (top view based on a stacked structure). Figure 4b for Figure 4a The diagram shows a stacking structure in the AA' direction. Figure 4c for Figure 4a The schematic diagram of the stacked structure in the BB' direction shows that the substrate 1 includes:
[0058] Gate signal line layer 11, source / drain electrode layer 12;
[0059] The gate signal line layer 11 includes a second signal line portion 111 of the gate signal line, and the source / drain electrode layer 12 includes a first signal line portion 121 of the gate signal line.
[0060] In the same gate signal line, the second signal line portion 111 in the gate signal line layer 11 is connected to the first signal line portion 121 in the source / drain electrode layer 12 through the first via 171;
[0061] The resistivity of the material in the first signal line portion 121 is less than that of the material in the second signal line portion 111;
[0062] The gate signal line layer 11 further includes a fourth signal line portion 112 of the data signal line, and the source / drain electrode layer 12 further includes a third signal line portion 122 of the data signal line.
[0063] In the same data signal line, the adjacent third signal line portion 122 and the fourth signal line portion 112 are connected through the second via 172;
[0064] The third signal line portion 122 and the first signal line portion 121 have no overlapping portions in their orthogonal projections on the array substrate 13 of the display substrate 1, while the fourth signal line portion 112 and the first signal line portion 121 have overlapping portions in their orthogonal projections on the array substrate 13.
[0065] In this embodiment of the invention, by incorporating the first signal line portion 121 into the gate signal line, compared to related technologies where the gate signal line is formed solely from the material of the second signal line portion 111, the resistance of the gate signal line can be reduced, improving gate signal attenuation and delay, and mitigating abnormal display issues on the display screen. Furthermore, at the intersection of the first signal line portion 121 and the data signal line, a jumper insulation treatment is applied at that location using the fourth signal line portion 112 of the data signal line, thus improving the problem of short circuits within the same metal layer.
[0066] In one possible implementation, see [link to relevant documentation]. Figure 4a , Figure 4b and Figure 4c The same gate signal line includes multiple second signal line portions 111 and a first signal line portion 121. Each second signal line portion 111 of the same gate signal line is connected to the first signal line portion 121 through a first via 171.
[0067] It should be noted that the projections described below are all orthographic projections on the array substrate 13.
[0068] Each gate signal line in this embodiment of the present invention consists of a first signal line portion 121 and a plurality of second signal line portions 111. The second signal line portion 111 is a trace for transmitting gate signals in the related art. The first signal line portion 121 is a trace for transmitting gate signals newly added in the source-drain electrode layer 12 (during the mask process, the gate signal line portion between sub-pixels in the related art is disconnected to form a plurality of second signal line portions 111. Each second signal line portion 111 is connected to the first signal line portion 121 through the first via 171. The first signal line portion 121 is connected in parallel with the disconnected plurality of second signal line portions 111 as a gate signal compensation line).
[0069] The data signal line in this invention consists of a third signal line portion 122 and a fourth signal line portion 112. The third signal line portion 122 is the trace for transmitting data signals in related technologies, and the fourth signal line portion 112 is a trace for transmitting data signals newly added in the gate signal line layer 11. (Since the first signal line portion 121 is in the source-drain electrode layer 12, if the data signal line is not jumpered, there will be a problem of short circuit in the same layer metal. At the intersection of the first signal line portion 121 and the data signal line, the fourth signal line portion 112 of the data signal line is used for jumper insulation treatment at this position, which can improve the problem of short circuit in the same layer metal. The fourth signal line portion 112 is connected to the adjacent third signal line portion 122 through the second via 172.)
[0070] The material of the first signal line portion 121 can be the same as the material of the third signal line portion 122, or other materials can be selected. The selection principle is based on the premise of not increasing the cost of the mask.
[0071] The material of the fourth signal line portion 112 can be the same as the material of the second signal line portion 111.
[0072] In one possible implementation, the material of the first signal line portion 121 is the same as that of the third signal line portion 122, and the material of the fourth signal line portion 112 is the same as that of the second signal line portion 111. This can ensure that the capacitance at the overlap position of the gate signal line and the data signal line does not change (in related technologies, the gate signal line in the gate signal line layer overlaps with the data signal line in the source / drain electrode layer, while in this invention, the first signal line portion 121 in the source / drain electrode layer 12 overlaps with the fourth signal line portion 112 in the gate signal line layer 11).
[0073] Understandable, Figure 4a , Figure 4b and Figure 4c Therefore, the structure of the data writing transistor with its drain and source arranged on both sides of its gate in the row direction of the display substrate 1 is shown.
[0074] Understandable, Figure 4a , Figure 4b and Figure 4c This is only a partial illustration.
[0075] In this embodiment of the invention, the gate signal line portion between sub-pixels in the related technology is disconnected (the fourth signal line portion 112 is in the gate signal line layer 11; disconnection can improve the problem of short circuit in the same layer metal), forming multiple second signal line portions 111. Each second signal line portion 111 is connected to the first signal line portion 121 through a first via 171. The first signal line portion 121 serves as a gate signal compensation line connected in parallel to the multiple disconnected second signal line portions 111 (the resistivity of the material of the first signal line portion 121 is lower than that of the second signal line portion 111, and the gate signal is transmitted through the first signal line portion 121). This can reduce the resistance of the gate signal line without increasing the mask cost, improve the attenuation and delay of the gate signal, and improve the abnormal display problem of the display screen. Furthermore, the second signal line portion 111 is a short trace structure, which is not easy to accumulate static charge. Although the first signal line portion 121 is a long trace structure, its resistivity is low. The resistance of a long trace structure is small, and its ability to conduct away static charge is strong, which can improve the problem of static charge accumulation in the related technology and reduce transistor damage. Furthermore, at the intersection of the first signal line portion 121 and the data signal line, a jumper insulation treatment is performed at that location by the fourth signal line portion 112 of the data signal line, which improves the problem of short circuit in the same layer of metal.
[0076] In one possible implementation, see Figure 4a ,
[0077] In the column direction of the display substrate 1, the first width d1 of the first signal line portion 121 is smaller than the second width d2 of the first signal line portion 121; wherein, the first width d1 is the width of the first signal line portion 121 at the projection overlap position with the fourth signal line portion 112, and the second width d2 is the width of the first signal line portion 121 at the non-projection overlap position with the fourth signal line portion 112.
[0078] In the column direction of the display substrate 1, the width of the first signal line portion 121 becomes thinner at the position where it overlaps with the projection of the fourth signal line portion 112, and the first signal line portion 121 presents a stepped shape.
[0079] In this embodiment of the invention, by reducing the width at the overlapping position of the projection of the first signal line portion 121 and the fourth signal line portion 112, the short circuit problem between the first signal line portion 121 and the third signal line portion 122 can be further improved, and the usage ratio of the fourth signal line portion 112 can be reduced, ensuring the low resistivity of the data signal line and ensuring the display quality of the display screen.
[0080] In one possible implementation,
[0081] The i-th second signal line portion 111 of the Nth gate signal line corresponds to the i-th sub-pixel in the Nth row of pixel units;
[0082] or,
[0083] The i-th second signal line portion 111 of the Nth gate signal line corresponds to the 2i-1th and 2ith sub-pixels in the Nth row of pixel units;
[0084] or,
[0085] The i-th second signal line portion 111 of the Nth gate signal line corresponds to the 3i-2, 3i-1, and 3i sub-pixels in the Nth row of pixel units;
[0086] Where N is an integer not less than 1, and i is an integer not less than 1.
[0087] There are several ways to disconnect the gate signal line between sub-pixels. The disconnection method can be set according to the pixel size. It can be that the gate signal line between each sub-pixel is disconnected once, or between every two sub-pixels, or between every three sub-pixels, and so on. If space is relatively sufficient, the method of disconnecting the gate signal line between each sub-pixel once can be selected. In the same gate signal line, each second signal line portion 111 is connected to the first signal line portion 121 through the first via 171. The gate 113 of the data write transistor of each sub-pixel is "integrated" with its corresponding second signal line portion 111. That is, each sub-pixel obtains the gate signal from the first signal line portion 121. The gate signal is transmitted using the first signal line portion 121 with very low resistivity, so that each sub-pixel has a sufficient gate voltage, which fully controls the switching of the sub-pixel, and the control effect of the gate signal is in the optimal state.
[0088] With the gate signal line portion disconnected once between every two sub-pixels, each second signal line portion 111 is connected to the first signal line portion 121 through the first via 171, but each second signal line portion 111 is "integrated" with the gate 113 of the data write transistor of the two sub-pixels. In this case, the data signal lines cannot be jumpered using the gate signal line layer 11, but can be jumpered using other film layers.
[0089] With the gate signal line portion disconnected once between every three sub-pixels, each second signal line portion 111 is connected to the first signal line portion 121 through the first via 171, but each second signal line portion 111 is "integrated" with the gate 113 of the data write transistor of the three sub-pixels. In this case, the data signal lines cannot be jumpered using the gate signal line layer 11, but can be jumpered using other film layers.
[0090] In one possible implementation, see [link to relevant documentation]. Figure 4a ,
[0091] In the column direction of the display substrate 1, a preset distance is provided between the drain of the data writing transistor of each sub-pixel in the Nth row pixel unit and the Nth gate signal line.
[0092] The first signal line portion 121 serves as a gate signal compensation line and is designed in the same layer as the third signal line portion 122 of the data signal line and the drain 123 of the data writing transistor (the drain 123 is disposed in the source-drain electrode layer 12). A preset distance must be set between the drain 123 and the first signal line portion 121 to avoid overlapping between the first signal line portion 121 and the drain 123, thereby preventing the formation of coupling capacitance.
[0093] In this embodiment of the invention, by setting a preset distance between the drain 123 and the first signal line portion 121, overlap between the first signal line portion 121 and the drain 123 can be avoided, thereby preventing the formation of coupling capacitance.
[0094] In one possible implementation, see [link to relevant documentation]. Figure 4a In the row direction of the display substrate 1, a data writing transistor is provided for each sub-pixel, and the drain 123 and source 124 of the data writing transistor are arranged on both sides of its gate 113.
[0095] exist Figure 4a In the structure shown, the gate 113 of the data writing transistor and the second signal line portion 111 are integrated in an inverted "F" shape. The drain 123 and source 124 of the data writing transistor are connected through a via and an active layer 15 (the orthographic projection of the active layer 15 on the array substrate 13 intersects with the orthographic projection of the gate 113 on the array substrate 13). The source 124 (the source 124 is disposed in the source-drain electrode layer 12) is connected to the data signal line, and the drain 123 is connected to the relevant transistor.
[0096] Understandable, Figure 4a The diagram illustrates the writing of data from a target sub-pixel to a transistor.
[0097] In one possible implementation, see Figure 5In the column direction of the display substrate 1, a data writing transistor is provided for each sub-pixel, and the drain 123 and source 124 of the data writing transistor are arranged on one side of its gate 113.
[0098] exist Figure 5 In the structure shown, the gate 113 of the data writing transistor and the second signal line portion 111 are integrated in a "I" shape. The orthographic projection of the gate 113 on the array substrate 13 is included in the orthographic projection of the first signal line portion 121 on the array substrate 13. The drain 123 and the source 124 of the data writing transistor are connected through a via and an active layer 15 (the orthographic projection of the active layer 15 on the array substrate 13 intersects with the orthographic projection of the gate 113 on the array substrate 13). The source 124 (the source 124 is disposed in the source-drain electrode layer 12) is connected to the data signal line, and the drain 123 is connected to the relevant transistor.
[0099] Understandable, Figure 5 The diagram illustrates the writing of data from a target sub-pixel to a transistor.
[0100] In one possible implementation, see Figure 6 In the column direction of the display substrate 1, a data writing transistor is provided for each sub-pixel, and the drain 123 and source 124 of the data writing transistor are arranged on both sides of its gate 113.
[0101] exist Figure 6 In the structure shown, the gate 113 of the data writing transistor and the second signal line portion 111 are integrated in a "T" shape. A portion of the orthographic projection of the gate 113 onto the array substrate 13 is included within the orthographic projection of the first signal line portion 121 onto the array substrate 13. The drain 123 and source 124 of the data writing transistor are connected through vias and an active layer 15 (the orthographic projection of the active layer 15 onto the array substrate 13 intersects with the orthographic projection of the gate 113 onto the array substrate 13). The source 124 (the source 124 is disposed in the source-drain electrode layer 12) is connected to the data signal line, and the drain 123 is connected to the relevant transistor.
[0102] Understandable, Figure 6 The diagram illustrates the writing of data from a target sub-pixel to a transistor.
[0103] In one possible implementation, see Figure 7 The display substrate 1 further includes: an array substrate 13, a first insulating layer 14, an active layer 15, a second insulating layer 16, and a third insulating layer 17;
[0104] The first insulating layer 14 is disposed on the array substrate 13, the active layer 15 is disposed on the first insulating layer 14 on the side away from the array substrate 13, the second insulating layer 16 is disposed on the active layer 15 on the side away from the array substrate 13, the gate signal line layer 11 is disposed on the second insulating layer 16 on the side away from the array substrate 13, the third insulating layer 17 is disposed on the gate signal line layer 11 on the side away from the array substrate 13, and the source / drain electrode layer 12 is disposed on the third insulating layer 17 on the side away from the array substrate 13.
[0105] In one possible implementation, based on the gate signal line provided by this invention, the film thickness of the gate signal line can be appropriately reduced according to actual conditions to decrease the intensity of the electric field at the edge of the LDD channel and improve the lifespan of the pixel electrode.
[0106] This utility model embodiment also provides a display device 2, see [link]. Figure 8 The display device 2 includes a display substrate 1 as described in any of the above embodiments.
[0107] The display device 2 can be a vehicle display screen, a computer display screen, or other types of display screens, etc. This utility model does not specifically limit it in this regard.
[0108] The above description is merely a preferred embodiment of this utility model and is not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model are included within the scope of protection of this utility model.
Claims
1. A display substrate, characterized in that, The display substrate includes: Gate signal line layer, source / drain electrode layer; The gate signal line layer includes a second signal line portion of the gate signal line, and the source / drain electrode layer includes a first signal line portion of the gate signal line. In the same gate signal line, the second signal line portion in the gate signal line layer is connected to the first signal line portion in the source / drain electrode layer through a first via; The resistivity of the material in the first signal line portion is less than the resistivity of the material in the second signal line portion; The gate signal line layer further includes a fourth signal line portion of the data signal line, and the source / drain electrode layer further includes a third signal line portion of the data signal line; In the same data signal line, the adjacent third signal line portion and the fourth signal line portion are connected through a second via; The third signal line portion and the first signal line portion have no overlapping portions in their orthographic projections on the array substrate of the display substrate, while the fourth signal line portion and the first signal line portion have overlapping portions in their orthographic projections on the array substrate.
2. The display substrate according to claim 1, characterized in that, The same gate signal line includes multiple second signal line portions and a first signal line portion. Each second signal line portion of the same gate signal line is connected to the first signal line portion through a first via.
3. The display substrate according to claim 2, characterized in that, In the column direction of the display substrate, the first width of the first signal line portion is smaller than the second width of the first signal line portion; wherein, the first width is the width at the position where the projection of the first signal line portion overlaps with that of the fourth signal line portion, and the second width is the width of the portion of the first signal line portion that does not overlap with that of the fourth signal line portion.
4. The display substrate according to claim 2, characterized in that, The i-th second signal line portion of the Nth gate signal line corresponds to the i-th sub-pixel in the Nth row of pixel units; or, The i-th second signal line portion of the Nth gate signal line corresponds to the 2i-1th and 2ith sub-pixels in the Nth row of pixel units; or, The i-th second signal line portion of the Nth gate signal line corresponds to the 3i-2, 3i-1, and 3i-th sub-pixels in the Nth row of pixel units; Where N is an integer not less than 1, and i is an integer not less than 1.
5. The display substrate according to claim 4, characterized in that, In the column direction of the display substrate, a preset distance is provided between the drain of the data writing transistor of each sub-pixel in the Nth row pixel unit and the Nth gate signal line.
6. The display substrate according to claim 5, characterized in that, In the row direction of the display substrate, a data writing transistor is provided for each sub-pixel, and the drain and source of the data writing transistor are arranged on both sides of its gate.
7. The display substrate according to claim 5, characterized in that, In the column direction of the display substrate, a data writing transistor is provided for each sub-pixel, and the drain and source of the data writing transistor are arranged on one side of its gate.
8. The display substrate according to claim 5, characterized in that, In the column direction of the display substrate, a data writing transistor is provided for each sub-pixel, with the drain and source of the data writing transistor arranged on both sides of its gate.
9. The display substrate according to claim 2, characterized in that, The display substrate further includes: an array substrate, a first insulating layer, an active layer, a second insulating layer, and a third insulating layer; The first insulating layer is disposed on the array substrate, the active layer is disposed on the side of the first insulating layer away from the array substrate, the second insulating layer is disposed on the side of the active layer away from the array substrate, the gate signal line layer is disposed on the side of the second insulating layer away from the array substrate, the third insulating layer is disposed on the side of the gate signal line layer away from the array substrate, and the source / drain electrode layer is disposed on the side of the third insulating layer away from the array substrate.
10. A display device, characterized in that, The display device includes a display substrate as described in any one of claims 1-9.