TBC solar cell, photovoltaic module and photovoltaic system
By optimizing the passivation structure of TBC solar cells and using multilayer stacked materials for passivation, the problem of increased surface recombination rate in TBC solar cells was solved, thereby improving the photoelectric conversion efficiency and stability of the cells.
Patent Information
- Application Number
- CN202520092003.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-15
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-01-15
AI Technical Summary
The increased recombination rate on the N-type substrate silicon surface of TBC solar cells leads to a decrease in Voc and Jsc, and the inversion and parasitic leakage problems caused by the existing alumina/silicon nitride passivation structure have not been effectively solved.
The first silicon oxide layer and the first silicon nitride layer are sequentially stacked on the front side of the N-type substrate silicon for passivation. The P-region is passivated with an aluminum oxide layer and a silicon oxide mask layer. The N-region is passivated with a second silicon nitride layer. The isolation region is passivated with a second silicon oxide layer. The passivation structure of each region is optimized to avoid inversion and parasitic leakage.
It effectively alleviates the problem of increased surface recombination rate caused by traditional alumina/silicon nitride passivation structure, improves Voc and Jsc of TBC solar cells, and enhances the photoelectric conversion efficiency and UV stability of the cells.
Smart Images
Figure CN223844152U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of solar cell technology, specifically to TBC solar cells, photovoltaic modules, and photovoltaic systems. Background Technology
[0002] Tunneling oxide passivated interdigitated back contact (TBC) cells are novel solar cell structures that combine the Tunneling Oxide Passivated Contact (TOPCon) and Interdigitated Back Contact (IBC) structures. This combination of advantages from both IBC and TOPCon results in high short-circuit current and excellent passivation characteristics, leading to higher photoelectric conversion efficiency. The front and back surfaces of TBC cells are typically passivated using an alumina / silicon nitride structure. In the alumina / silicon nitride structure, alumina contains a significant amount of hydrogen atoms, exhibiting excellent chemical passivation properties. Additionally, alumina contains a certain amount of fixed negative charge, providing a certain field passivation effect on p-type silicon. Silicon nitride, containing hydrogen atoms, provides chemical passivation, while its fixed positive charge provides field passivation for n-type silicon. When passivated with an aluminum oxide / silicon nitride structure, it exhibits electronegativity, and for the back p-poly-Si of TBC cells, it has both chemical passivation and field passivation effects.
[0003] When the silicon substrate of a TBC cell is an N-type substrate silicon, the front surface of the TBC cell is an N-type substrate silicon, and the back surface of the TBC cell includes a p-poly-Si region, an n-poly-Si region, and an isolation region. The minority carriers in the N-type substrate silicon on the front side, the isolation substrate silicon on the back side, and the n-poly-Si on the back side of the TBC cell are holes. By using an alumina / silicon nitride structure to passivate the front and back sides of the TBC cell, the negative charges in the alumina / silicon nitride structure will attract holes to the silicon wafer surface, leading to an increase in the surface recombination rate, which in turn leads to a decrease in the cell's Voc (open-circuit voltage) and Jsc (short-circuit current).
[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the Invention
[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide TBC solar cells, photovoltaic modules, and photovoltaic systems. The front side of the N-type silicon substrate is passivated using a first silicon oxide layer and a first silicon nitride layer stacked sequentially; the P-region is passivated using an aluminum oxide layer and a silicon oxide mask layer stacked sequentially; the N-region is passivated using a second silicon nitride layer; and the isolation region is passivated using a second silicon oxide layer. This optimizes the passivation structure of each region in the TBC solar cell, avoiding inversion caused by the passivation structure, reducing parasitic leakage current, and effectively alleviating the problem of increased surface recombination rate caused by traditional aluminum oxide / silicon nitride passivation structures. This results in TBC solar cells with higher Voc and Jsc.
[0006] To achieve the above objectives, this application adopts the following technical solution:
[0007] A TBC solar cell includes an N-type silicon substrate, a positive electrode, and a negative electrode;
[0008] The front side of the N-type substrate silicon includes a first silicon oxide layer and a first silicon nitride layer stacked sequentially.
[0009] The back side of the N-type substrate silicon includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region.
[0010] The P region includes a second tunneling silicon oxide layer, a P-type polysilicon layer, an aluminum oxide layer, and a silicon oxide mask layer stacked sequentially.
[0011] The N region comprises a first tunneling silicon oxide layer, an N-type polycrystalline silicon layer, and a second silicon nitride layer stacked sequentially.
[0012] A second silicon oxide layer is disposed on the isolation area;
[0013] The positive electrode forms an ohmic contact with the P-type polysilicon layer through the silicon oxide mask layer and the aluminum oxide layer; the negative electrode forms an ohmic contact with the N-type polysilicon layer through the second silicon nitride layer.
[0014] In some embodiments, the thickness of the first tunneling silicon oxide layer is 1-2 nm; and / or
[0015] The thickness of the N-type polycrystalline silicon layer is 70~300 nm; and / or
[0016] The thickness of the second silicon nitride layer is 50~120nm.
[0017] In some embodiments, the total thickness of the N-type polysilicon layer and the second silicon nitride layer is 150~250 nm.
[0018] In some embodiments, the thickness of the second tunneling silicon oxide layer is 1-2 nm; and / or
[0019] The thickness of the P-type polycrystalline silicon layer is 50~300 nm; and / or
[0020] The thickness of the alumina layer is 30~100nm; and / or
[0021] The thickness of the silicon oxide mask layer is 20~80nm.
[0022] In some embodiments, the total thickness of the P-type polysilicon layer, the alumina layer, and the silicon oxide mask layer is 150~250 nm.
[0023] In some embodiments, the thickness of the first silicon oxide layer is 2-3 nm; and / or
[0024] The thickness of the first silicon nitride layer is 50~100nm.
[0025] In some embodiments, the thickness of the second silicon oxide layer is 2-3 nm.
[0026] In some embodiments, the width of the isolation region is 10~80μm.
[0027] This application also provides a photovoltaic module, which includes at least the aforementioned TBC solar cell.
[0028] This application also provides a photovoltaic system, including the photovoltaic module described above.
[0029] In this technical solution, the front side of the N-type substrate silicon is passivated by sequentially stacked first silicon oxide layer and first silicon nitride layer, the P-region is passivated by sequentially stacked aluminum oxide layer and silicon oxide mask layer, the N-region is passivated by second silicon nitride layer, and the isolation region is passivated by second silicon oxide layer. This optimizes the passivation structure of each region of the TBC solar cell, avoids inversion caused by the passivation structure, reduces the parasitic leakage rate, and effectively alleviates the problem of increased surface recombination rate caused by traditional aluminum oxide / silicon nitride passivation structure, resulting in TBC solar cells with higher Voc and Jsc. Attached Figure Description
[0030] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.
[0031] Figure 1This is a schematic diagram of the structure of the TBC solar cell in an embodiment of this application.
[0032] Figure 2 This is a first intermediate state diagram of the TBC solar cell fabricated according to an embodiment of this application.
[0033] Figure 3 This is a second intermediate state diagram of the TBC solar cell fabricated according to an embodiment of this application.
[0034] Figure 4 This is a diagram of the third intermediate state of the TBC solar cell fabricated according to an embodiment of this application.
[0035] Figure 5 This is a fourth intermediate state diagram of the TBC solar cell fabricated according to an embodiment of this application.
[0036] In the figure, the following labels are used: 100, N-type substrate silicon; 101, first silicon oxide layer; 102, first silicon nitride layer; 202, second tunneling silicon oxide layer; 302, P-type polycrystalline silicon layer; 501, aluminum oxide layer; 601, silicon oxide mask layer; 201, first tunneling silicon oxide layer; 301, N-type polycrystalline silicon layer; 401, second silicon nitride layer; 701, second silicon oxide layer; 901, positive electrode; 902, negative electrode. Detailed Implementation
[0037] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings. In the drawings, for clarity, the dimensions of layers, regions, and elements, as well as their relative dimensions, may be exaggerated. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.
[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0039] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0041] In this application, when numerical intervals (i.e., numerical ranges) are involved, unless otherwise specified, the distribution of selectable numerical values within the numerical interval is considered continuous, and includes the two endpoints of the numerical interval (i.e., the minimum and maximum values), as well as every numerical value between these two endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that numerical interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed in this application should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. The term "numerical interval" can be broadly included to include percentage intervals, ratio intervals, proportion intervals, etc.
[0042] This application provides a TBC solar cell, photovoltaic module, and photovoltaic system. The front side of the N-type substrate silicon is passivated by sequentially stacked first silicon oxide layer and first silicon nitride layer, the P-region is passivated by sequentially stacked aluminum oxide layer and silicon oxide mask layer, the N-region is passivated by second silicon nitride layer, and the isolation region is passivated by second silicon oxide layer. The passivation structure of each region of the TBC solar cell is optimized to avoid inversion caused by the passivation structure, reduce the parasitic leakage rate, and effectively alleviate the problem of increased surface recombination rate caused by traditional aluminum oxide / silicon nitride passivation structure, so that the prepared TBC solar cell has higher Voc and Jsc.
[0043] A TBC solar cell includes an N-type silicon substrate, a positive electrode, and a negative electrode;
[0044] The front side of the N-type substrate silicon includes a first silicon oxide layer and a first silicon nitride layer stacked sequentially.
[0045] The back side of the N-type substrate silicon includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region.
[0046] The P region includes a second tunneling silicon oxide layer, a P-type polysilicon layer, an aluminum oxide layer, and a silicon oxide mask layer stacked sequentially.
[0047] The N region comprises a first tunneling silicon oxide layer, an N-type polycrystalline silicon layer, and a second silicon nitride layer stacked sequentially.
[0048] A second silicon oxide layer is disposed on the isolation area;
[0049] The positive electrode forms an ohmic contact with the P-type polysilicon layer through the silicon oxide mask layer and the aluminum oxide layer; the negative electrode forms an ohmic contact with the N-type polysilicon layer through the second silicon nitride layer.
[0050] In this embodiment, the thickness of the first silicon oxide layer can be 1~50nm (e.g., 1nm, 5nm, 10nm, 15nm, 20nm, 30nm, 40nm, 50nm); the thickness of the first silicon nitride layer can be 30~200nm (e.g., 30nm, 50nm, 70nm, 90nm, 120nm, 140nm, 160nm, 180nm, 200nm); the thickness of the second tunneling silicon oxide layer can be 1~20nm (e.g., 1nm, 5nm, 10nm, 15nm, 20nm); and the thickness of the P-type polycrystalline silicon layer can be 30~500nm (e.g., 30nm, 50nm). The thickness of the alumina layer can be 10~200nm (e.g., 10nm, 30nm, 50nm, 70nm, 90nm, 120nm, 140nm, 160nm, 180nm, 200nm, 220nm, 240nm, 260nm, 280nm, 300nm, 350nm, 400nm, 450nm, 500nm); the thickness of the silicon oxide mask layer can be 10~150nm (e.g., 10nm, 30nm, 50nm, 70nm, 90nm, 120nm, 140nm, 160nm, 180nm, 200nm); the thickness of the silicon oxide mask layer can be 10~150nm (e.g., 10nm, 30nm, 50nm, 70nm, 90nm, 120nm, 120nm, 140nm, 160nm, 180nm, 200nm). The thickness of the first tunneling silicon oxide layer can be 1~20nm (e.g., 1nm, 5nm, 10nm, 15nm, 20nm); the thickness of the N-type polycrystalline silicon layer can be 30~500nm (e.g., 30nm, 50nm, 70nm, 90nm, 120nm, 140nm, 160nm, 180nm, 200nm, 220nm, 240nm, 260nm, 280nm, 300nm, 350nm, 400nm, 450nm, 500nm); the thickness of the second silicon nitride layer can be 30~200nm (e.g., 30nm, 140nm, 150nm); the thickness of the first tunneling silicon oxide layer can be 1~20nm (e.g., 1nm, 5nm, 10nm, 15nm, 2 ..., 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, 20nm, The thickness of the second silicon oxide layer can be 1~50nm (e.g., 1nm, 5nm, 10nm, 15nm, 20nm, 30nm, 40nm, 50nm); the width of the isolation region can be 5~100μm (e.g., 5μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm). It should be noted that the thickness of each layer can be set according to actual needs, and the width of the isolation region can also be set according to actual needs.
[0051] In the embodiments of this application, the preparation methods of the first silicon oxide layer, the first tunneling silicon oxide layer, the second tunneling silicon oxide layer, the silicon oxide mask layer, and the second silicon oxide layer can all be selected from one or more of thermal oxidation, plasma-enhanced chemical vapor deposition, and electrochemical anodizing. The preparation methods of the first silicon nitride layer and the second silicon nitride layer can all be selected from one or more of plasma-enhanced chemical vapor deposition, thermal oxidation, low-pressure chemical vapor deposition, and atomic layer deposition. The preparation methods of the P-type polycrystalline silicon layer and the N-type polycrystalline silicon layer can all be selected from one or more of plasma-enhanced chemical vapor deposition, chemical vapor deposition, low-pressure chemical vapor deposition, and physical vapor deposition. The preparation method of the alumina layer can be selected from one or more of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.
[0052] In this embodiment, the front side of the N-type substrate silicon is passivated using a first silicon oxide layer and a first silicon nitride layer stacked sequentially; the P-region is passivated using an aluminum oxide layer and a silicon oxide mask layer stacked sequentially; the N-region is passivated using a second silicon nitride layer; and the isolation region is passivated using a second silicon oxide layer. This optimized passivation structure in each region of the TBC solar cell avoids inversion caused by the passivation structure, reduces parasitic leakage current, and effectively alleviates the problem of increased surface recombination rate caused by traditional aluminum oxide / silicon nitride passivation structures. This results in a TBC solar cell with higher Voc and Jsc. Furthermore, after optimizing the passivation structure in each region of the TBC solar cell, the front side of the TBC solar cell exhibits superior UV (ultraviolet) stability.
[0053] In an optional embodiment, the thickness of the first tunneling silicon oxide layer is 1-2 nm (e.g., 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm); and / or
[0054] The thickness of the N-type polycrystalline silicon layer is 70~300nm (e.g., 70nm, 90nm, 120nm, 140nm, 160nm, 180nm, 200nm, 220nm, 240nm, 260nm, 280nm, 300nm); and / or
[0055] The thickness of the second silicon nitride layer is 50~120nm (e.g., 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm).
[0056] In this embodiment, the thickness of each layer in the N region is optimized, resulting in better passivation. This helps to reduce the reflectivity of the cell and improve the photoelectric conversion efficiency. At the same time, it can avoid the inversion caused by the passivation structure, reduce the parasitic leakage rate, and effectively alleviate the problem of increased surface recombination rate caused by traditional alumina / silicon nitride passivation structure. This results in TBC solar cells with higher Voc and Jsc.
[0057] In an optional embodiment, the total thickness of the N-type polycrystalline silicon layer and the second silicon nitride layer is 150~250nm (e.g., 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm). In this embodiment, controlling the total thickness of the N-type polycrystalline silicon layer and the second silicon nitride layer helps to reduce the reflectivity of the battery and improve the photoelectric conversion efficiency.
[0058] In an optional embodiment, the thickness of the second tunneling silicon oxide layer is 1-2 nm (e.g., 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm); and / or
[0059] The thickness of the P-type polycrystalline silicon layer is 50~300nm (e.g., 50nm, 70nm, 90nm, 120nm, 140nm, 160nm, 180nm, 200nm, 220nm, 240nm, 260nm, 280nm, 300nm); and / or
[0060] The thickness of the alumina layer is 30~100nm (e.g., 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm); and / or
[0061] The thickness of the silicon oxide mask layer is 20~80nm (e.g., 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm).
[0062] In this embodiment, the thickness of each layer in the P region is optimized, resulting in better passivation. This helps to reduce the reflectivity of the battery and improve the photoelectric conversion efficiency. At the same time, it can avoid the inversion caused by the passivation structure, reduce the parasitic leakage rate, and effectively alleviate the problem of increased surface recombination rate caused by traditional alumina / silicon nitride passivation structure. This results in TBC solar cells with higher Voc and Jsc.
[0063] In optional embodiments, the total thickness of the P-type polycrystalline silicon layer, the alumina layer, and the silicon oxide mask layer is 150~250nm (e.g., 150nm, 170nm, 190nm, 200nm, 220nm, 240nm, 250nm). In this embodiment, controlling the total thickness of the P-type polycrystalline silicon layer, the alumina layer, and the silicon oxide mask layer helps to reduce the reflectivity of the battery and improve the photoelectric conversion efficiency.
[0064] In optional embodiments, the thickness of the first silicon oxide layer is 2-3 nm (e.g., 2 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm, 3 nm); and / or
[0065] The thickness of the first silicon nitride layer is 50~100nm (e.g., 50nm, 60nm, 70nm, 80nm, 90nm, 100nm).
[0066] In this embodiment, optimizing the thickness of the first silicon oxide layer and the first silicon nitride layer can avoid inversion caused by the passivation structure, reduce the parasitic leakage rate, and effectively alleviate the problem of increased surface recombination rate caused by the traditional alumina / silicon nitride passivation structure, so that the prepared TBC solar cell has higher Voc and Jsc.
[0067] In an optional embodiment, the thickness of the second silicon oxide layer is 2-3 nm (e.g., 2 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm, 3 nm). In this embodiment, optimizing the thickness of the second silicon oxide layer can effectively reduce carrier recombination on the battery surface, thereby improving the photoelectric conversion efficiency of the battery.
[0068] In optional embodiments, the width of the isolation region is 10~80μm (e.g., 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm). In this embodiment, optimizing the width of the isolation region can reduce the risk of short circuits and suppress leakage current, and also improve the passivation effect of the battery, thereby improving the photoelectric conversion efficiency.
[0069] The following specific embodiments provide a more detailed description of this application, but should not be construed as limiting the application. Any modifications or substitutions made to the methods, steps, or conditions of this application without departing from the spirit and substance of this application are within the scope of this application. Specific Implementation
[0071] Example 1
[0072] A type of TBC solar cell, such as Figure 1 As shown, it includes an N-type substrate silicon 100, a positive electrode 901, and a negative electrode 902;
[0073] The front side of the N-type substrate silicon 100 includes a first silicon oxide layer 101 and a first silicon nitride layer 102 stacked sequentially; the thickness of the first silicon oxide layer 101 is 1 nm; the thickness of the first silicon nitride layer 102 is 30 nm.
[0074] The back side of the N-type substrate silicon 100 includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; the width of the isolation region is 5 μm.
[0075] The P-region comprises a second tunneling silicon oxide layer 202, a P-type polysilicon layer 302, an aluminum oxide layer 501, and a silicon oxide mask layer 601 stacked sequentially. The thickness of the second tunneling silicon oxide layer 202 is 1 nm; the thickness of the P-type polysilicon layer 302 is 30 nm; the thickness of the aluminum oxide layer 501 is 10 nm; the thickness of the silicon oxide mask layer 601 is 10 nm; and the total thickness of the P-type polysilicon layer 302, the aluminum oxide layer 501, and the silicon oxide mask layer 601 is 50 nm.
[0076] The N-region comprises a first tunneling silicon oxide layer 201, an N-type polycrystalline silicon layer 301, and a second silicon nitride layer 401 stacked sequentially; the thickness of the first tunneling silicon oxide layer 201 is 1 nm; the thickness of the N-type polycrystalline silicon layer 301 is 30 nm; the thickness of the second silicon nitride layer 401 is 30 nm; the total thickness of the N-type polycrystalline silicon layer 301 and the second silicon nitride layer 401 is 60 nm.
[0077] A second silicon oxide layer 701 is disposed on the isolation area; the thickness of the second silicon oxide layer 701 is 1 nm;
[0078] The positive electrode 901 forms an ohmic contact with the P-type polysilicon layer 302 through the silicon oxide mask layer 601 and the aluminum oxide layer 501; the negative electrode 902 forms an ohmic contact with the N-type polysilicon layer 301 through the second silicon nitride layer 401.
[0079] Example 2
[0080] A type of TBC solar cell, such as Figure 1 As shown, it includes an N-type substrate silicon 100, a positive electrode 901, and a negative electrode 902;
[0081] The front side of the N-type substrate silicon 100 includes a first silicon oxide layer 101 and a first silicon nitride layer 102 stacked sequentially; the thickness of the first silicon oxide layer 101 is 50 nm; the thickness of the first silicon nitride layer 102 is 200 nm.
[0082] The back side of the N-type substrate silicon 100 includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; the width of the isolation region is 100 μm.
[0083] The P-region comprises a second tunneling silicon oxide layer 202, a P-type polysilicon layer 302, an aluminum oxide layer 501, and a silicon oxide mask layer 601 stacked sequentially. The thickness of the second tunneling silicon oxide layer 202 is 20 nm; the thickness of the P-type polysilicon layer 302 is 500 nm; the thickness of the aluminum oxide layer 501 is 200 nm; and the thickness of the silicon oxide mask layer 601 is 150 nm. The total thickness of the P-type polysilicon layer 302, the aluminum oxide layer 501, and the silicon oxide mask layer 601 is 850 nm.
[0084] The N-region comprises a first tunneling silicon oxide layer 201, an N-type polycrystalline silicon layer 301, and a second silicon nitride layer 401 stacked sequentially; the thickness of the first tunneling silicon oxide layer 201 is 20 nm; the thickness of the N-type polycrystalline silicon layer 301 is 500 nm; the thickness of the second silicon nitride layer 401 is 200 nm; the total thickness of the N-type polycrystalline silicon layer 301 and the second silicon nitride layer 401 is 700 nm.
[0085] A second silicon oxide layer 701 is disposed on the isolation area; the thickness of the second silicon oxide layer 701 is 50 nm;
[0086] The positive electrode 901 forms an ohmic contact with the P-type polysilicon layer 302 through the silicon oxide mask layer 601 and the aluminum oxide layer 501; the negative electrode 902 forms an ohmic contact with the N-type polysilicon layer 301 through the second silicon nitride layer 401.
[0087] Example 3
[0088] A type of TBC solar cell, such as Figure 1 As shown, it includes an N-type substrate silicon 100, a positive electrode 901, and a negative electrode 902;
[0089] The front side of the N-type substrate silicon 100 includes a first silicon oxide layer 101 and a first silicon nitride layer 102 stacked sequentially; the thickness of the first silicon oxide layer 101 is 2 nm; the thickness of the first silicon nitride layer 102 is 50 nm.
[0090] The back side of the N-type substrate silicon 100 includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; the width of the isolation region is 10 μm.
[0091] The P-region comprises a second tunneling silicon oxide layer 202, a P-type polysilicon layer 302, an aluminum oxide layer 501, and a silicon oxide mask layer 601 stacked sequentially. The thickness of the second tunneling silicon oxide layer 202 is 1 nm; the thickness of the P-type polysilicon layer 302 is 50 nm; the thickness of the aluminum oxide layer 501 is 30 nm; and the thickness of the silicon oxide mask layer 601 is 20 nm. The total thickness of the P-type polysilicon layer 302, the aluminum oxide layer 501, and the silicon oxide mask layer 601 is 100 nm.
[0092] The N-region comprises a first tunneling silicon oxide layer 201, an N-type polycrystalline silicon layer 301, and a second silicon nitride layer 401 stacked sequentially; the thickness of the first tunneling silicon oxide layer 201 is 1 nm; the thickness of the N-type polycrystalline silicon layer 301 is 70 nm; the thickness of the second silicon nitride layer 401 is 50 nm; the total thickness of the N-type polycrystalline silicon layer 301 and the second silicon nitride layer 401 is 120 nm.
[0093] A second silicon oxide layer 701 is disposed on the isolation area; the thickness of the second silicon oxide layer 701 is 2 nm;
[0094] The positive electrode 901 forms an ohmic contact with the P-type polysilicon layer 302 through the silicon oxide mask layer 601 and the aluminum oxide layer 501; the negative electrode 902 forms an ohmic contact with the N-type polysilicon layer 301 through the second silicon nitride layer 401.
[0095] Example 4
[0096] A type of TBC solar cell, such as Figure 1 As shown, it includes an N-type substrate silicon 100, a positive electrode 901, and a negative electrode 902;
[0097] The front side of the N-type substrate silicon 100 includes a first silicon oxide layer 101 and a first silicon nitride layer 102 stacked sequentially; the thickness of the first silicon oxide layer 101 is 3 nm; the thickness of the first silicon nitride layer 102 is 100 nm.
[0098] The back side of the N-type substrate silicon 100 includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; the width of the isolation region is 80 μm.
[0099] The P-region comprises a second tunneling silicon oxide layer 202, a P-type polysilicon layer 302, an aluminum oxide layer 501, and a silicon oxide mask layer 601 stacked sequentially. The thickness of the second tunneling silicon oxide layer 202 is 2 nm; the thickness of the P-type polysilicon layer 302 is 300 nm; the thickness of the aluminum oxide layer 501 is 100 nm; and the thickness of the silicon oxide mask layer 601 is 80 nm. The total thickness of the P-type polysilicon layer 302, the aluminum oxide layer 501, and the silicon oxide mask layer 601 is 480 nm.
[0100] The N-region comprises a first tunneling silicon oxide layer 201, an N-type polycrystalline silicon layer 301, and a second silicon nitride layer 401 stacked sequentially; the thickness of the first tunneling silicon oxide layer 201 is 2 nm; the thickness of the N-type polycrystalline silicon layer 301 is 300 nm; the thickness of the second silicon nitride layer 401 is 120 nm; the total thickness of the N-type polycrystalline silicon layer 301 and the second silicon nitride layer 401 is 420 nm.
[0101] A second silicon oxide layer 701 is disposed on the isolation area; the thickness of the second silicon oxide layer 701 is 3 nm;
[0102] The positive electrode 901 forms an ohmic contact with the P-type polysilicon layer 302 through the silicon oxide mask layer 601 and the aluminum oxide layer 501; the negative electrode 902 forms an ohmic contact with the N-type polysilicon layer 301 through the second silicon nitride layer 401.
[0103] Example 5
[0104] A type of TBC solar cell, such as Figure 1 As shown, it includes an N-type substrate silicon 100, a positive electrode 901, and a negative electrode 902;
[0105] The front side of the N-type substrate silicon 100 includes a first silicon oxide layer 101 and a first silicon nitride layer 102 stacked sequentially; the thickness of the first silicon oxide layer 101 is 3 nm; the thickness of the first silicon nitride layer 102 is 100 nm.
[0106] The back side of the N-type substrate silicon 100 includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; the width of the isolation region is 80 μm.
[0107] The P-region comprises a second tunneling silicon oxide layer 202, a P-type polysilicon layer 302, an aluminum oxide layer 501, and a silicon oxide mask layer 601 stacked sequentially. The thickness of the second tunneling silicon oxide layer 202 is 2 nm; the thickness of the P-type polysilicon layer 302 is 50 nm; the thickness of the aluminum oxide layer 501 is 50 nm; the thickness of the silicon oxide mask layer 601 is 50 nm; and the total thickness of the P-type polysilicon layer 302, the aluminum oxide layer 501, and the silicon oxide mask layer 601 is 150 nm.
[0108] The N-region comprises a first tunneling silicon oxide layer 201, an N-type polycrystalline silicon layer 301, and a second silicon nitride layer 401 stacked sequentially; the thickness of the first tunneling silicon oxide layer 201 is 2 nm; the thickness of the N-type polycrystalline silicon layer 301 is 300 nm; the thickness of the second silicon nitride layer 401 is 120 nm; the total thickness of the N-type polycrystalline silicon layer 301 and the second silicon nitride layer 401 is 420 nm.
[0109] A second silicon oxide layer 701 is disposed on the isolation area; the thickness of the second silicon oxide layer 701 is 3 nm;
[0110] The positive electrode 901 forms an ohmic contact with the P-type polysilicon layer 302 through the silicon oxide mask layer 601 and the aluminum oxide layer 501; the negative electrode 902 forms an ohmic contact with the N-type polysilicon layer 301 through the second silicon nitride layer 401.
[0111] Example 6
[0112] A type of TBC solar cell, such as Figure 1 As shown, it includes an N-type substrate silicon 100, a positive electrode 901, and a negative electrode 902;
[0113] The front side of the N-type substrate silicon 100 includes a first silicon oxide layer 101 and a first silicon nitride layer 102 stacked sequentially; the thickness of the first silicon oxide layer 101 is 3 nm; the thickness of the first silicon nitride layer 102 is 100 nm.
[0114] The back side of the N-type substrate silicon 100 includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; the width of the isolation region is 80 μm.
[0115] The P-region comprises a second tunneling silicon oxide layer 202, a P-type polysilicon layer 302, an aluminum oxide layer 501, and a silicon oxide mask layer 601 stacked sequentially. The thickness of the second tunneling silicon oxide layer 202 is 2 nm; the thickness of the P-type polysilicon layer 302 is 100 nm; the thickness of the aluminum oxide layer 501 is 100 nm; and the thickness of the silicon oxide mask layer 601 is 50 nm. The total thickness of the P-type polysilicon layer 302, the aluminum oxide layer 501, and the silicon oxide mask layer 601 is 250 nm.
[0116] The N-region comprises a first tunneling silicon oxide layer 201, an N-type polycrystalline silicon layer 301, and a second silicon nitride layer 401 stacked sequentially; the thickness of the first tunneling silicon oxide layer 201 is 2 nm; the thickness of the N-type polycrystalline silicon layer 301 is 300 nm; the thickness of the second silicon nitride layer 401 is 120 nm; the total thickness of the N-type polycrystalline silicon layer 301 and the second silicon nitride layer 401 is 420 nm.
[0117] A second silicon oxide layer 701 is disposed on the isolation area; the thickness of the second silicon oxide layer 701 is 3 nm;
[0118] The positive electrode 901 forms an ohmic contact with the P-type polysilicon layer 302 through the silicon oxide mask layer 601 and the aluminum oxide layer 501; the negative electrode 902 forms an ohmic contact with the N-type polysilicon layer 301 through the second silicon nitride layer 401.
[0119] Example 7
[0120] A type of TBC solar cell, such as Figure 1 As shown, it includes an N-type substrate silicon 100, a positive electrode 901, and a negative electrode 902;
[0121] The front side of the N-type substrate silicon 100 includes a first silicon oxide layer 101 and a first silicon nitride layer 102 stacked sequentially; the thickness of the first silicon oxide layer 101 is 3 nm; the thickness of the first silicon nitride layer 102 is 100 nm.
[0122] The back side of the N-type substrate silicon 100 includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; the width of the isolation region is 80 μm.
[0123] The P-region comprises a second tunneling silicon oxide layer 202, a P-type polysilicon layer 302, an aluminum oxide layer 501, and a silicon oxide mask layer 601 stacked sequentially. The thickness of the second tunneling silicon oxide layer 202 is 2 nm; the thickness of the P-type polysilicon layer 302 is 300 nm; the thickness of the aluminum oxide layer 501 is 100 nm; and the thickness of the silicon oxide mask layer 601 is 80 nm. The total thickness of the P-type polysilicon layer 302, the aluminum oxide layer 501, and the silicon oxide mask layer 601 is 480 nm.
[0124] The N-region comprises a first tunneling silicon oxide layer 201, an N-type polycrystalline silicon layer 301, and a second silicon nitride layer 401 stacked sequentially; the thickness of the first tunneling silicon oxide layer 201 is 2 nm; the thickness of the N-type polycrystalline silicon layer 301 is 100 nm; the thickness of the second silicon nitride layer 401 is 50 nm; the total thickness of the N-type polycrystalline silicon layer 301 and the second silicon nitride layer 401 is 150 nm.
[0125] A second silicon oxide layer 701 is disposed on the isolation area; the thickness of the second silicon oxide layer 701 is 3 nm;
[0126] The positive electrode 901 forms an ohmic contact with the P-type polysilicon layer 302 through the silicon oxide mask layer 601 and the aluminum oxide layer 501; the negative electrode 902 forms an ohmic contact with the N-type polysilicon layer 301 through the second silicon nitride layer 401.
[0127] Example 8
[0128] A type of TBC solar cell, such as Figure 1 As shown, it includes an N-type substrate silicon 100, a positive electrode 901, and a negative electrode 902;
[0129] The front side of the N-type substrate silicon 100 includes a first silicon oxide layer 101 and a first silicon nitride layer 102 stacked sequentially; the thickness of the first silicon oxide layer 101 is 3 nm; the thickness of the first silicon nitride layer 102 is 100 nm.
[0130] The back side of the N-type substrate silicon 100 includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; the width of the isolation region is 80 μm.
[0131] The P-region comprises a second tunneling silicon oxide layer 202, a P-type polysilicon layer 302, an aluminum oxide layer 501, and a silicon oxide mask layer 601 stacked sequentially. The thickness of the second tunneling silicon oxide layer 202 is 2 nm; the thickness of the P-type polysilicon layer 302 is 300 nm; the thickness of the aluminum oxide layer 501 is 100 nm; and the thickness of the silicon oxide mask layer 601 is 80 nm. The total thickness of the P-type polysilicon layer 302, the aluminum oxide layer 501, and the silicon oxide mask layer 601 is 480 nm.
[0132] The N-region comprises a first tunneling silicon oxide layer 201, an N-type polycrystalline silicon layer 301, and a second silicon nitride layer 401 stacked sequentially; the thickness of the first tunneling silicon oxide layer 201 is 2 nm; the thickness of the N-type polycrystalline silicon layer 301 is 150 nm; the thickness of the second silicon nitride layer 401 is 100 nm; the total thickness of the N-type polycrystalline silicon layer 301 and the second silicon nitride layer 401 is 250 nm.
[0133] A second silicon oxide layer 701 is disposed on the isolation area; the thickness of the second silicon oxide layer 701 is 3 nm;
[0134] The positive electrode 901 forms an ohmic contact with the P-type polysilicon layer 302 through the silicon oxide mask layer 601 and the aluminum oxide layer 501; the negative electrode 902 forms an ohmic contact with the N-type polysilicon layer 301 through the second silicon nitride layer 401.
[0135] Example 9
[0136] A type of TBC solar cell, such as Figure 1 As shown, it includes an N-type substrate silicon 100, a positive electrode 901, and a negative electrode 902;
[0137] The front side of the N-type substrate silicon 100 includes a first silicon oxide layer 101 and a first silicon nitride layer 102 stacked sequentially; the thickness of the first silicon oxide layer 101 is 3 nm; the thickness of the first silicon nitride layer 102 is 100 nm.
[0138] The back side of the N-type substrate silicon 100 includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; the width of the isolation region is 80 μm.
[0139] The P-region comprises a second tunneling silicon oxide layer 202, a P-type polysilicon layer 302, an aluminum oxide layer 501, and a silicon oxide mask layer 601 stacked sequentially. The thickness of the second tunneling silicon oxide layer 202 is 2 nm; the thickness of the P-type polysilicon layer 302 is 100 nm; the thickness of the aluminum oxide layer 501 is 100 nm; and the thickness of the silicon oxide mask layer 601 is 50 nm. The total thickness of the P-type polysilicon layer 302, the aluminum oxide layer 501, and the silicon oxide mask layer 601 is 250 nm.
[0140] The N-region comprises a first tunneling silicon oxide layer 201, an N-type polycrystalline silicon layer 301, and a second silicon nitride layer 401 stacked sequentially; the thickness of the first tunneling silicon oxide layer 201 is 2 nm; the thickness of the N-type polycrystalline silicon layer 301 is 150 nm; the thickness of the second silicon nitride layer 401 is 100 nm; the total thickness of the N-type polycrystalline silicon layer 301 and the second silicon nitride layer 401 is 250 nm.
[0141] A second silicon oxide layer 701 is disposed on the isolation area; the thickness of the second silicon oxide layer 701 is 3 nm;
[0142] The positive electrode 901 forms an ohmic contact with the P-type polysilicon layer 302 through the silicon oxide mask layer 601 and the aluminum oxide layer 501; the negative electrode 902 forms an ohmic contact with the N-type polysilicon layer 301 through the second silicon nitride layer 401.
[0143] Comparative Example 1
[0144] A type of TBC solar cell, such as Figure 1 As shown, it includes an N-type substrate silicon 100, a positive electrode 901, and a negative electrode 902;
[0145] The front side of the N-type substrate silicon 100 includes an aluminum oxide layer and a silicon nitride layer stacked sequentially; the aluminum oxide layer has a thickness of 3 nm; and the silicon nitride layer has a thickness of 100 nm.
[0146] The back side of the N-type substrate silicon 100 includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; the width of the isolation region is 80 μm.
[0147] The P-region comprises a second tunneling silicon oxide layer 202, a P-type polycrystalline silicon layer 302, an aluminum oxide layer 501, and a silicon nitride layer stacked sequentially; the thickness of the second tunneling silicon oxide layer 202 is 2 nm; the thickness of the P-type polycrystalline silicon layer 302 is 100 nm; the thickness of the aluminum oxide layer 501 is 100 nm; and the thickness of the silicon nitride layer is 50 nm.
[0148] The N region comprises a first tunneling silicon oxide layer 201, an N-type polycrystalline silicon layer 301, an aluminum oxide layer, and a silicon nitride layer stacked sequentially; the thickness of the first tunneling silicon oxide layer 201 is 2 nm; the thickness of the N-type polycrystalline silicon layer 301 is 150 nm; the thickness of the aluminum oxide layer is 50 nm; and the thickness of the silicon nitride layer is 50 nm.
[0149] An aluminum oxide layer is disposed on the isolation area; the thickness of the aluminum oxide layer is 3 nm.
[0150] In this configuration, the positive electrode 901 forms an ohmic contact with the P-type polycrystalline silicon layer 302 through the silicon oxide mask layer 601 and the aluminum oxide layer 501; the negative electrode 902 forms an ohmic contact with the N-type polycrystalline silicon layer 301 through the second silicon nitride layer 401. That is, the passivation structure of each region in the TBC solar cell in Comparative Example 1 is a conventional aluminum oxide / silicon nitride passivation structure.
[0151] It should be noted that in the above embodiments 1-9, the preparation method of the TBC solar cell can be as follows:
[0152] (1) Polishing of N-type substrate silicon 100; the concentration of alkaline solution is 2-4wt%, the temperature is 60-80℃, and the time is 150s-400s;
[0153] (2) A first tunneling silicon oxide layer 201, an N-type polycrystalline silicon layer 301, and a second silicon nitride layer 401 are sequentially formed on the back side of an N-type substrate silicon 100 by PECVD; the first tunneling silicon oxide layer 201 is made of silicon oxide and has the following structure: Figure 2 As shown;
[0154] (3) Using a green picosecond laser for patterning, a portion of the second silicon nitride layer 401 is melted. The exposed first tunneling silicon oxide layer 201 and N-type polysilicon layer 301 are removed by alkaline etching to form the second region. A single-sided cleaning machine is used to remove the silicon nitride layers deposited on the front and sides. An alkaline solution is used to remove the doped polysilicon layer exposed on the front side. The structure is as follows: Figure 3 As shown;
[0155] (4) A second tunneling silicon oxide layer 202 and a P-type polysilicon layer 302 are deposited on the back side using PECVD. After high-temperature annealing, the N-type polysilicon layer 301 and the P-type polysilicon layer 302 are transformed into n-type polysilicon and p-type polysilicon, respectively. An aluminum oxide layer 501 and a silicon oxide mask layer 601 are then deposited on the back surface. The structure is as follows: Figure 4 As shown;
[0156] (5) The uppermost N-type polysilicon layer 301 and the silicon oxide mask layer 601 of the isolation region are thermally melted using a green picosecond laser, and the exposed aluminum oxide layer 501, P-type polysilicon layer 302, and N-type substrate silicon 100 of the isolation region are etched using alkaline etching; the structure is as follows. Figure 5 As shown;
[0157] (6) Remove the silicon oxide mask layer 601 from the front side, texturize the front side, and oxidize the N-type substrate silicon 100 on the front side and the isolation region on the back side using hydrogen peroxide to form a second silicon oxide layer 701 and a first silicon oxide layer 101. Deposit a first silicon nitride layer 102 on the front side using PECVD. Metallize to form a positive electrode 901 and a negative electrode 902. The structure is as follows. Figure 1 As shown.
[0158] The device performance data of the above embodiments and comparative examples are shown in Table 1 below.
[0159] Table 1
[0160]
[0161] As can be seen from the detection data of the TBC solar cells in Examples 1-9 and Comparative Example 1, optimizing the passivation structure of each region of the TBC solar cell, avoiding the inversion caused by the passivation structure, and reducing the parasitic leakage rate can effectively alleviate the problem of increased surface recombination rate caused by the traditional alumina / silicon nitride passivation structure. This results in the TBC solar cell having higher Voc (open circuit voltage) and Jsc (short circuit current), thereby improving the Eta (photovoltaic conversion efficiency) of the TBC solar cell to a certain extent.
[0162] As can be seen from the detection data of Examples 1-2 and Examples 3-4 above, optimizing the thickness of each layer in the P region and each layer in the N region results in a better passivation effect, which helps to reduce the reflectivity of the battery and improve the photoelectric conversion efficiency. At the same time, it can avoid the inversion caused by the passivation structure, reduce the parasitic leakage rate, and effectively alleviate the problem of increased surface recombination rate caused by the traditional alumina / silicon nitride passivation structure, so that the prepared TBC solar cell has higher Voc and Jsc.
[0163] As can be seen from the detection data of Examples 4 and 5-6 above, controlling the total thickness of the P-type polycrystalline silicon layer 302, the alumina layer 501 and the silicon oxide mask layer 601 helps to reduce the reflectivity of the battery and improve the photoelectric conversion efficiency.
[0164] As can be seen from the detection data of Examples 4 and 7-8 above, controlling the total thickness of the N-type polycrystalline silicon layer 301 and the second silicon nitride layer 401 helps to reduce the reflectivity of the battery and improve the photoelectric conversion efficiency.
[0165] As can be seen from the detection data of Examples 4 and 9 above, controlling the total thickness of the N-type polycrystalline silicon layer 301 and the second silicon nitride layer 401, and then controlling the total thickness of the P-type polycrystalline silicon layer 302, the aluminum oxide layer 501 and the silicon oxide mask layer 601, can further improve the Voc, Jsc and photoelectric conversion efficiency of TBC solar cells.
[0166] In summary, the optimized passivation structure of each region of the TBC solar cell in the embodiments avoids inversion caused by the passivation structure, reduces the parasitic leakage rate, and effectively alleviates the problem of increased surface recombination rate caused by traditional alumina / silicon nitride passivation structure. This results in TBC solar cells with higher Voc and Jsc, thereby improving the photoelectric conversion efficiency of TBC solar cells.
[0167] This application embodiment can provide a photovoltaic module (not shown), which includes at least the TBC solar cell in any of the above embodiments.
[0168] This application provides a photovoltaic system including the photovoltaic modules described in any of the above embodiments. The advantages of the aforementioned photovoltaic modules are also present in this photovoltaic system, and will not be repeated here. The application fields of the aforementioned photovoltaic system are wide, not limited to photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants, but also including various devices and apparatuses that utilize solar energy for power generation, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy for power generation. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic modules; for example, multiple photovoltaic modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.
[0169] It should be noted that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The directional terms "inner" and "outer" refer to the inside or outside relative to the outline of the component itself. For example, if a device in the drawings is inverted, a device described as "above" or "on top of" other devices or structures will subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.
[0170] It should also be noted that the terms "one embodiment," "another embodiment," and "embodiment" used in this application refer to specific features, structures, or characteristics described in connection with that embodiment, which are included in at least one embodiment described in the general description of this application. The appearance of the same expression in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in connection with any embodiment, the intention is to suggest that implementing such a feature, structure, or characteristic in conjunction with other embodiments also falls within the scope of this application.
[0171] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0172] It should also be noted that the above are merely preferred embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.
Claims
1. A TBC solar cell, characterized in that, Includes N-type silicon substrate, positive electrode, and negative electrode; The front side of the N-type substrate silicon includes a first silicon oxide layer and a first silicon nitride layer stacked sequentially. The back side of the N-type substrate silicon includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region. The P region includes a second tunneling silicon oxide layer, a P-type polysilicon layer, an aluminum oxide layer, and a silicon oxide mask layer stacked sequentially. The N region comprises a first tunneling silicon oxide layer, an N-type polycrystalline silicon layer, and a second silicon nitride layer stacked sequentially. A second silicon oxide layer is disposed on the isolation area; The positive electrode forms an ohmic contact with the P-type polysilicon layer through the silicon oxide mask layer and the aluminum oxide layer; the negative electrode forms an ohmic contact with the N-type polysilicon layer through the second silicon nitride layer.
2. The TBC solar cell according to claim 1, characterized in that, The thickness of the first tunneling silicon oxide layer is 1~2 nm; and / or The thickness of the N-type polycrystalline silicon layer is 70~300 nm; and / or The thickness of the second silicon nitride layer is 50~120nm.
3. The TBC solar cell according to claim 2, characterized in that, The total thickness of the N-type polycrystalline silicon layer and the second silicon nitride layer is 150~250nm.
4. The TBC solar cell according to claim 1, characterized in that, The thickness of the second tunneling silicon oxide layer is 1~2 nm; and / or The thickness of the P-type polycrystalline silicon layer is 50~300 nm; and / or The thickness of the alumina layer is 30~100nm; and / or The thickness of the silicon oxide mask layer is 20~80nm.
5. The TBC solar cell according to claim 4, characterized in that, The total thickness of the P-type polycrystalline silicon layer, the alumina layer, and the silicon oxide mask layer is 150~250nm.
6. The TBC solar cell according to claim 1, characterized in that, The thickness of the first silicon oxide layer is 2-3 nm; and / or The thickness of the first silicon nitride layer is 50~100nm.
7. The TBC solar cell according to claim 1, characterized in that, The thickness of the second silicon oxide layer is 2~3 nm.
8. The TBC solar cell according to claim 1, characterized in that, The width of the isolation area is 10~80μm.
9. A photovoltaic module, characterized in that, The photovoltaic module includes at least the TBC solar cell as described in any one of claims 1-8.
10. A photovoltaic system, characterized in that, Including the photovoltaic module as described in claim 9.