Display device

Abstract

A display device includes a silicon substrate including: a display area including a light emitting element and a pixel circuit portion inside the silicon substrate and connected to the light emitting element; and a non-display area adjacent to the display area. The non-display area includes: a driving circuit portion inside the silicon substrate and supplying an electric signal to the display area through the driving circuit portion; and an electrostatic shielding layer covering the driving circuit portion.

Description

Technical Field

[0001] The embodiments generally provide a display device. More specifically, the embodiments relate to a display device that provides visual information. Background Technology

[0002] With the development of information technology, the importance of display devices as communication media between users and information is becoming increasingly prominent. Therefore, the use of display devices such as liquid crystal displays, organic light-emitting diode displays, and plasma displays is increasing.

[0003] A display device using high-resolution micro-organic light-emitting diodes (OLEDs) has been developed. The high-resolution micro-OLED can be an OLEDoS (Organic Light-Emitting Diode on Silicon) formed (or provided) using a silicon wafer-based semiconductor process. For example, the display device using a high-resolution micro-OLED can be a head-mounted display (HMD) device, which is a glasses-type monitor device for virtual reality (VR) or augmented reality (AR) worn in the form of glasses or a helmet and focused at close range in front of the user's eyes. The head-mounted display device can provide the user's eyes with the image displayed on the display device through lenses. Utility Model Content

[0004] An embodiment provides a display device in which defects caused by electrostatic discharge are improved.

[0005] The display device according to an embodiment of the present disclosure includes: a silicon substrate including a display area and a non-display area surrounding the display area; a pixel circuit portion disposed inside the silicon substrate in the display area; a driving circuit portion disposed inside the silicon substrate in the non-display area; and a shielding layer disposed on the driving circuit portion and covering the driving circuit portion in a plan view.

[0006] In this embodiment, the shielding layer may include a metallic material.

[0007] In an embodiment, the display device may further include: a pixel electrode disposed on a silicon substrate and electrically connected to a pixel circuit portion; a light-emitting layer disposed on the pixel electrode; and a common electrode disposed on the light-emitting layer.

[0008] In an embodiment, the shielding layer may comprise the same material as the common electrode.

[0009] In one embodiment, the shielding layer may be spaced apart from the common electrode.

[0010] In one embodiment, the common electrode may extend continuously from the display area to at least a portion of the non-display area, and the shielding layer may include a portion of the common electrode that overlaps with the non-display area.

[0011] In one embodiment, the shielding layer may comprise the same material as the pixel electrode.

[0012] In one embodiment, the shielding layer may be spaced apart from the pixel electrode.

[0013] In this embodiment, the shielding layer may include inorganic materials.

[0014] In one embodiment, the shielding layer may include glass.

[0015] In an embodiment, the display device may further include: a light-emitting element disposed on a silicon substrate in a display area; an encapsulation layer disposed on the light-emitting element and including an inorganic layer and an organic layer; and an encapsulation substrate facing the encapsulation layer and formed of glass.

[0016] In this embodiment, the shielding layer may comprise the same material as the encapsulation layer.

[0017] In this embodiment, the shielding layer may comprise the same material as the encapsulation substrate.

[0018] In an embodiment, the display device may further include: a dummy pattern disposed within the silicon substrate in a non-display area; and a protective ring pattern (i.e., an electrostatic discharge pattern) disposed within the silicon substrate in the non-display area and adjacent to the dummy pattern.

[0019] In an embodiment, the shielding layer may be connected to a dummy pattern or a protective ring pattern.

[0020] In one embodiment, the shielding layer may have a planar shape in which a plurality of openings spaced apart from each other are defined.

[0021] A display device according to an embodiment of the present disclosure includes: a silicon substrate including a display area and a non-display area, the non-display area including a pad area spaced apart from one side of the display area in a first direction and located around the display area; a pixel circuit portion disposed inside the silicon substrate in the display area; a driving circuit portion disposed in the area of ​​the non-display area other than the pad area; a plurality of signal pads arranged in the pad area of ​​the silicon substrate along a second direction intersecting the first direction; a circuit board electrically connected to the signal pads; a timing controller directly disposed on the circuit board; and a shielding layer disposed on the driving circuit portion and covering the driving circuit portion in a plan view.

[0022] In an embodiment, the display device may further include: a pixel electrode disposed on a silicon substrate and electrically connected to a pixel circuit portion; a light-emitting layer disposed on the pixel electrode; and a common electrode disposed on the light-emitting layer. The shielding layer may comprise the same material as the pixel electrode or the common electrode.

[0023] In an embodiment, the display device may further include: a light-emitting element disposed on a silicon substrate in a display area; an encapsulation layer disposed on the light-emitting element and comprising at least one inorganic layer and at least one organic layer; and an encapsulation substrate comprising glass. The shielding layer may comprise the same material as the encapsulation layer or the encapsulation substrate.

[0024] In an embodiment, the display device may further include: a dummy pattern disposed within a silicon substrate in a non-display area; and a guard ring pattern disposed within the silicon substrate and located in a planar view between the dummy pattern and the signal pads in the pad area. A shielding layer may be connected to the dummy pattern or the guard ring pattern.

[0025] A display device according to an embodiment of the present disclosure may include: a substrate comprising a silicon wafer; a driving circuit portion disposed within the substrate in a non-display area; and a shielding layer disposed on the driving circuit portion and covering the entire driving circuit portion in a plan view. Therefore, the shielding layer can block or prevent external electrostatic discharge from flowing into the driving circuit portion. In this case, defects in the display device due to electrostatic discharge can be prevented. Attached Figure Description

[0026] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0029] Figure 3 It shows along Figure 1 A cross-sectional view of an example section taken from line II-II' in the diagram.

[0030] Figure 4 It is shown Figure 3 A plan view of the driving circuit section and the shielding layer.

[0031] Figure 5 , Figure 6 and Figure 7 It is shown Figure 3 A plan view of an example of the planar shape of the shielding layer.

[0032] Figure 8 It shows along Figure 1 A cross-sectional view of an example section taken from line II-II' in the diagram.

[0033] Figure 9 It shows along Figure 1A cross-sectional view of an example section taken from line II-II' in the diagram.

[0034] Figure 10 It shows along Figure 1 A cross-sectional view of an example section taken from line II-II' in the diagram.

[0035] Figure 11 It shows along Figure 1 A cross-sectional view of an example section taken from line II-II' in the diagram. Detailed Implementation

[0036] Hereinafter, a display device according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0037] It will be understood that when an element is referred to as being associated with another element (such as "on" another element), the element may be directly on the other element or an intermediary element may exist between the element and the other element. Conversely, when an element is referred to as being associated with another element (such as "directly on" another element), there is no intermediary element.

[0038] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or segment from another. Therefore, without departing from the teachings herein, the terms “first element,” “first component,” “first area,” “first layer,” or “first segment” discussed below may be referred to as a second element, second component, second area, second layer, or second segment.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation on quantity and are intended to include both singular and plural forms. Thus, reference to an element as “a” followed by reference to an element as “the” in a claim includes one element and multiple elements. For example, unless the context clearly indicates otherwise, “an element” and “at least one element” have the same meaning. In the drawings and text of this disclosure, reference numerals indicating elements in the singular form may also be used for multiple singular elements. “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprises and / or comprising” or “including and / or include” indicate the presence of the stated features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or groups thereof.

[0040] Furthermore, as illustrated in the accompanying drawings, spatially relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship of one element to another. It will be understood that, in addition to the orientations depicted in the drawings, the spatially relative terms are also intended to encompass different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “below” the other elements will then be oriented to be “above” the other elements. Thus, depending on the specific orientation of the drawing, the term “below” can encompass both “below” and “above” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other elements will then be oriented to be “above” the other elements. Thus, the terms “below” or “under” can encompass both “above” and “below” orientations.

[0041] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, “approximately” or “about” includes stated values ​​and means the average value within an acceptable range of deviations from a particular value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations or within ±30%, ±20%, ±10%, or ±5% of said value.

[0042] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their context in the relevant field and their meaning in this disclosure, and shall not be interpreted in an idealized or overly formal sense.

[0043] The embodiments described herein are illustrated with reference to cross-sectional views of schematic diagrams as idealized embodiments. Therefore, variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region shown as or described as flat may generally have rough and / or non-linear characteristics. Furthermore, acute angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show precise shapes of the regions and are not intended to limit the scope of the claims.

[0044] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0045] refer to Figure 1 According to embodiments of the present disclosure, the display device DD may include a substrate BS, a driving circuit portion DDI, a plurality of signal pads SPD (including multiple signal pads SPD), a circuit board CB, and a timing controller TCL.

[0046] The substrate BS may include a display area DA and a non-display area NDA. The display area DA may be an area (e.g., a planar area) that displays an image by generating light or by adjusting the transmittance of light provided from an external light source. The non-display area NDA may be an area that does not display an image. The non-display area NDA may be positioned adjacent to the display area DA (e.g., extending along the display area DA or surrounding the display area DA). For example, the non-display area NDA may completely surround the display area DA.

[0047] The display area DA may include a plurality of pixel regions (including multiple pixel regions). The pixel regions may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the pixel regions may include a first pixel region PX1, a second pixel region PX2, and a third pixel region PX3.

[0048] Each of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 can represent an area where light emitted from the light-emitting element is emitted to the outside of the display device DD. For example, the first pixel region PX1 can emit a first light, the second pixel region PX2 can emit a second light, and the third pixel region PX3 can emit a third light. In an embodiment, the first light can be red light, the second light can be green light, and the third light can be blue light. However, this disclosure is not limited thereto. For example, the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 can be combined to emit yellow light, cyan light, and magenta light.

[0049] The first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 can emit four or more colors of light. For example, the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 can be combined to emit at least one of yellow, cyan, and magenta light, in addition to red, green, and blue light. Alternatively, the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 can be combined to emit white light.

[0050] In the planar diagram, each of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 can have a triangular planar shape, a square planar shape, a circular planar shape, or an elliptical planar shape, etc. In an embodiment, each of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 can have a rectangular planar shape. However, the embodiments of this disclosure are not limited, and each of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 can have different planar shapes from each other.

[0051] The non-display area NDA may include a sub-region SA. The sub-region SA may be positioned spaced apart from the display area DA on one side in a direction opposite to the second direction DR2. For example, the sub-region SA may have a shape that extends in the first direction DR1.

[0052] The sub-region SA may include a pad region PDA. The pad region PDA may be positioned spaced apart from the display region DA on one side in the direction opposite to the second direction DR2. For example, the pad region PDA may have a shape that extends in the first direction DR1. That is, the pad region PDA may be elongated or have a main dimension in the first direction DR1 to be considered as "extending" in the first direction DR1.

[0053] The driver can be located in the non-display area NDA. The driver can provide signals (e.g., electrical signals) and / or voltages to the pixel area. For example, the driver can include a data driver, a scan driver, and a light-emitting driver, etc.

[0054] Multiple lines (e.g., signal lines, conductive lines, etc.) can be disposed in the portion of the non-display area NDA outside the pad area PDA and sub-area SA, and multiple signal pads SPDs can be disposed in the pad area PDA. These lines enable electrical connections between the signal pads SPDs and the pixel areas. For example, these lines may include data voltage lines, scan signal lines, light emission control signal lines, and power supply voltage lines, etc.

[0055] Signal pads (SPDs) can be arranged to be spaced apart from each other along a first direction DR1. For example, each of the signal pads (SPDs) may include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These can be used individually or in combination with each other.

[0056] The drive circuit section DDI can be disposed within the sub-region SA. Specifically, the drive circuit section DDI can be disposed in the sub-region SA excluding the pad region PDA. In an embodiment, the drive circuit section DDI can be disposed inside the substrate BS. That is, the drive circuit section DDI can be embedded in the sub-region SA. Here, the thickness of the drive circuit section DDI can be within the thickness of the substrate BS.

[0057] The drive circuit section DDI can convert the digital data signal in the drive signal provided by the circuit board CB into an analog data signal as the converted data signal, and provide the converted data signal to the pixel area. For example, the drive circuit section DDI (e.g., drive circuit) can be a data drive section (e.g., a data driver). However, the embodiments of this disclosure are not limited thereto.

[0058] The circuit board CB can be electrically connected to the signal pad SPD at one end (e.g., the first side or first end). Additionally, the circuit board CB can be electrically connected to an external device (not shown) at the other end (e.g., the second side or second end). The circuit board CB can receive drive signals generated from the external device (e.g., data voltage, scan signal, light control signal, and power supply voltage, etc.). For example, the circuit board CB can include a flexible printed circuit board (FPCB) or a printed circuit board (PCB). The external device can be an electronic component such as a circuit board, but is not limited thereto.

[0059] The timing controller TCL can be mounted on the circuit board CB. Specifically, the timing controller TCL can be directly placed on the circuit board CB. The timing controller TCL can generate electrical signals such as scan control signals for controlling the scan driver, data control signals for controlling the data driver, and light emission control signals for controlling the light emission driver. In addition, the timing controller TCL can generate digital data signals and provide these digital data signals to the data driver.

[0060] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 may be perpendicular to the second direction DR2. Additionally, a third direction DR3 may intersect the plane (e.g., perpendicular to the plane). The thickness of the display device DD and its various components or layers may be defined along the third direction DR3 (e.g., the thickness direction).

[0061] The display device DD according to embodiments of the present disclosure may include an organic light-emitting display device, a liquid crystal display device, an organic light-emitting diode on silicon (OLEDoS), a liquid crystal on silicon (LCoS), or a light-emitting diode on silicon (LEDoS). In embodiments, the display device DD may be a display device such as an OLEDoS. Hereinafter, an example of a display device DD being an OLEDoS will be used for description.

[0062] For example, if the display device DD is a display device such as an OLEDoS, then the display device DD can be a head-mounted display, which is a glasses-type monitor device for virtual reality or augmented reality that is worn in the form of glasses and helmets and forms a focal point at close range in front of a body part such as the user's eyes. However, the embodiments of this disclosure are not limited to this, and the display device DD can be configured with various displays.

[0063] Figure 2 It is along Figure 1 A cross-sectional view taken by line I-I'. For example, Figure 2 It is shown that it includes Figure 1 A cross-sectional view of the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3 in the display area DA.

[0064] refer to Figure 1 and Figure 2According to embodiments of the present disclosure, a display device DD may include a display panel DP and an encapsulation substrate ES disposed on the display panel DP. The display panel DP may include a substrate BS, a plurality of pixel circuit portions PXC in a pixel circuit layer, an insulating layer IL, a first light-emitting element LED1, a second light-emitting element LED2, and a third light-emitting element LED3 connected to the pixel circuit layer in a light-emitting element layer, a partition wall PW in a pixel defining layer, an encapsulation layer TFE, a first color filter layer CF1, a second color filter layer CF2, and a third color filter layer CF3 together with a light-blocking layer BM in a color filter layer, and a lens layer.

[0065] Here, the first light-emitting element LED1 may include a first pixel electrode PE1, a light-emitting layer EML and a common electrode CE, the second light-emitting element LED2 may include a second pixel electrode PE2, a light-emitting layer EML and a common electrode CE, and the third light-emitting element LED3 may include a third pixel electrode PE3, a light-emitting layer EML and a common electrode CE.

[0066] In an embodiment, the substrate BS may include a silicon wafer formed (or provided) using semiconductor processes. The substrate BS may be a support member or substrate layer for supporting other components of the display device DD. In this specification, the substrate BS may be referred to as a silicon substrate.

[0067] Multiple pixel circuit sections (PXCs) can be disposed within the substrate BS. The pixel circuit sections (PXCs) can overlap with a first pixel region (PX1), a second pixel region (PX2), and a third pixel region (PX3) along the thickness direction, respectively. Because they are "within" the substrate BS, and each of the pixel circuit sections (PXCs) and the substrate BS has a thickness along the third direction DR3, the overall thickness of the pixel circuit sections (PXCs) is within the thickness of the substrate BS. Reference Figure 2 For example, the upper surface of the pixel circuit portion PXC may be substantially coplanar with the upper surface of the substrate BS, but is not limited thereto.

[0068] Each of the pixel circuit portions (PXC) may include various driving elements and lines for driving the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3. For example, each of the pixel circuit portions (PXC) may include various components such as transistors, storage capacitors, scan signal lines, and data signal lines. However, embodiments of this disclosure are not limited thereto. In embodiments, the non-display area NDA may include a driving circuit portion (DDI) within the silicon substrate, and electrical signals are provided to the display area DA through the driving circuit portion DDI.

[0069] An insulating layer IL can be disposed on the pixel circuit portion PXC. The insulating layer IL can reduce or effectively prevent undesirable contact (e.g., electrical short circuit) between the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 and the pixel circuit portion PXC. The insulating layer IL can comprise organic and / or inorganic materials. For example, the insulating layer IL can comprise materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y Inorganic materials such as ) can be used individually or in combination with each other.

[0070] A first pixel electrode PE1, a second pixel electrode PE2, and a third pixel electrode PE3 can be disposed on an insulating layer IL. The first pixel electrode PE1 can overlap with a first pixel region PX1, the second pixel electrode PE2 can overlap with a second pixel region PX2, and the third pixel electrode PE3 can overlap with a third pixel region PX3. The first pixel electrode PE1 can be electrically connected to a pixel circuit portion PXC through a contact hole penetrating the insulating layer IL in the first pixel region PX1, the second pixel electrode PE2 can be electrically connected to the pixel circuit portion PXC through a contact hole penetrating the insulating layer IL in the second pixel region PX2, and the third pixel electrode PE3 can be electrically connected to the pixel circuit portion PXC through a contact hole penetrating the insulating layer IL in the third pixel region PX3. The solid portion of the insulating layer IL can define various contact holes.

[0071] Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials, etc. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may include the same material as each other and be formed by the same process (e.g., in the same layer). For example, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a multilayer structure including ITO / Ag / ITO. However, embodiments of this disclosure are not limited thereto. Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be an anode electrode. Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be a reflective electrode. However, embodiments of this disclosure are not limited thereto. Because they are in the same layer, the elements can be formed in the same process and / or include the same material as each other; the elements can be corresponding portions or corresponding patterns of the same material layer; the elements can be on the same layer by forming interfaces with the same lower or upper layer, etc., but are not limited thereto.

[0072] The separator wall PW can be disposed on the insulating layer IL. The separator wall PW can cover the edge of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. Additionally, the separator wall PW can define a pixel opening that exposes at least a portion of the upper surface of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 to the outside of the separator wall PW. For example, the separator wall PW can comprise inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride. These can be used individually or in combination with each other. In embodiments, the separator wall PW can have a multilayer structure, but embodiments of this disclosure are not limited thereto.

[0073] The light-emitting layer (EML) can be disposed on the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the separator wall PW. The EML can be a common layer formed in the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3. That is, the EML can extend continuously throughout the entire display area DA, passing through the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3. For example, the EML can include a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron injection layer, and an electron transport layer. In an embodiment, the organic light-emitting layer can include a light-emitting material that emits white light. For example, the white light can be a mixture of blue, green, and red light. Optionally, the white light can be a mixture of blue and yellow light.

[0074] However, embodiments of this disclosure are not limited thereto, and the light-emitting layer EML may include: a first light-emitting layer as a separation pattern, the first light-emitting layer overlapping with a first pixel region PX1 and including a light-emitting material emitting red light; a second light-emitting layer as a separation pattern, the second light-emitting layer overlapping with a second pixel region PX2 and including a light-emitting material emitting green light; and a third light-emitting layer as a separation pattern, the third light-emitting layer overlapping with a third pixel region PX3 and including a light-emitting material emitting blue light. In this case, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer may be separated from each other in a direction along the substrate BS (e.g., separation pattern), and the first color filter layer CF1, the second color filter layer CF2, the third color filter layer CF3, and the light-blocking layer BM may be omitted.

[0075] The common electrode CE can be disposed on the light-emitting layer EML. The common electrode CE can be a common layer formed in the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3. That is, the common electrode CE can extend continuously throughout the entire display area DA, passing through the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3. For example, the common electrode CE can include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These can be used individually or in combination. The common electrode CE can be a cathode electrode. The common electrode CE can be a transmissive or semi-transmissive electrode.

[0076] Therefore, the first pixel electrode PE1, the light-emitting layer EML, and the common electrode CE can together form the first light-emitting element LED1 in the first pixel region PX1, the second pixel electrode PE2, the light-emitting layer EML, and the common electrode CE can together form the second light-emitting element LED2 in the second pixel region PX2, and the third pixel electrode PE3, the light-emitting layer EML, and the common electrode CE can together form the third light-emitting element LED3 in the third pixel region PX3.

[0077] The encapsulation layer TFE can be disposed on the common electrode CE. The encapsulation layer TFE can extend continuously throughout the entire display area DA, passing through the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3. The encapsulation layer TFE can prevent impurities and moisture from penetrating into the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3 from the outside.

[0078] The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2 disposed on the first inorganic encapsulation layer TFE1, and a second inorganic encapsulation layer TFE3 disposed on the organic encapsulation layer TFE2. The organic encapsulation layer TFE2 may have a substantially flat upper surface.

[0079] For example, the first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may include silicon oxide, silicon nitride, and silicon oxynitride, etc. These may be used individually or in combination with each other. The organic encapsulation layer TFE2 may include a cured polymer such as polyacrylate.

[0080] A first color filter layer CF1, a second color filter layer CF2, and a third color filter layer CF3, as patterned color filter layers, can be disposed on an encapsulation layer TFE. The first color filter layer CF1 may overlap with a first pixel region PX1, the second color filter layer CF2 may overlap with a second pixel region PX2, and the third color filter layer CF3 may overlap with a third pixel region PX3. Each of the first color filter layer CF1, the second color filter layer CF2, and the third color filter layer CF3 can selectively transmit only light of a specific wavelength and absorb light of other wavelengths. For example, red light can pass through the first color filter layer CF1, green light can pass through the second color filter layer CF2, and blue light can pass through the third color filter layer CF3. Therefore, the first pixel region PX1 can emit red light, the second pixel region PX2 can emit green light, and the third pixel region PX3 can emit blue light. However, the embodiments of this disclosure are not limited thereto.

[0081] The light-blocking layer BM of the color filter layer can be disposed on the encapsulation layer TFE. The light-blocking layer BM can be disposed between the first color filter layer CF1, the second color filter layer CF2, and the third color filter layer CF3, respectively. That is, the light-blocking layer BM does not overlap with the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3. The light-blocking layer BM blocks light incident on it. Therefore, the light-blocking layer BM prevents color mixing between the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3. For example, the light-blocking layer BM can include organic and / or inorganic materials containing black pigments and black dyes.

[0082] The lens layer can be disposed on a first color filter layer CF1, a second color filter layer CF2, a third color filter layer CF3, and a light-blocking layer BM. The lens layer can include multiple microlenses ML. Microlenses ML can improve light extraction efficiency. Microlenses ML can overlap with a first pixel region PX1, a second pixel region PX2, and a third pixel region PX3, respectively. Each of the multiple microlenses ML can be a separate lens or a lens pattern. Microlenses ML can have a predetermined refractive index relative to visible light. For example, microlenses ML can have a refractive index of about 1.5 or greater to about 1.7 or less relative to visible light. However, embodiments of this disclosure are not limited thereto. For example, each of the microlenses ML can have a convex cross-sectional shape that curves away from the substrate BS.

[0083] The encapsulation substrate ES can be disposed on the lens layer. The encapsulation substrate ES can be attached to the display panel DP via an adhesive layer ADL. The encapsulation substrate ES can protect the display panel DP from moisture penetration or gas ingress. The encapsulation substrate ES may include a transparent insulating substrate. For example, the encapsulation substrate ES may include glass. For example, the adhesive layer ADL may include optically clear adhesive (OCA), pressure-sensitive adhesive (PSA), photocurable resin, or thermosetting resin, etc.

[0084] Figure 3 It shows along Figure 1 A cross-sectional view of an example section taken from line II-II' in the diagram.

[0085] refer to Figure 3 On the insulating layer IL, the display panel DP (see) Figure 2 The signal pad SPD can be located in the pad area PDA. As described above, the circuit board CB can be electrically connected to the display panel DP at the signal pad SPD. Specifically, the pad electrode CPD of the circuit board CB and the signal pad SPD of the display panel DP can be electrically connected to each other via the line WR. In other words, the pad electrode CPD, the line WR, and the signal pad SPD can be connected to each other in a one-to-one correspondence.

[0086] In an embodiment, the display device DD (see...) Figure 1 The device may further include a shielding layer SHL disposed on the insulating layer IL and covering the drive circuit portion DDI in a plan view (e.g., a view along the third direction DR3). That is, the shielding layer SHL may be configured to cover the entire drive circuit portion DDI. In other words, the shielding layer SHL may be configured to overlap with the drive circuit portion DDI in a plan view. Therefore, the shielding layer SHL can block or prevent external electrostatic discharge (ESD) from flowing into the drive circuit portion DDI. The shielding layer SHL may be disposed on a first surface (e.g., the upper surface) of the insulating layer IL, while the drive circuit portion DDI is disposed on a second surface (e.g., the lower surface) opposite the first surface.

[0087] For example, the shielding layer SHL may include a metallic material. In an embodiment, the shielding layer SHL may be combined with... Figure 2 The common electrode CE comprises the same material (i.e., the shielding layer SHL is the same as...). Figure 2 The common electrode CE can be a corresponding pattern of the same material layer. That is, the shielding layer SHL can be... Figure 2 The common electrode CE is formed using the same process (e.g., in the same layer as the common electrode CE). However, embodiments of this disclosure are not limited thereto, and the shielding layer SHL may include other materials. A detailed description of this will be provided later.

[0088] In the embodiment, when the shielding layer SHL and Figure 2 When the common electrode CE is formed using the same process, as shown by the shielding layer SHL spaced apart from the (right) dashed line of the indicator sub-region SA, the shielding layer SHL can be aligned with the insulating layer IL in the direction of the shielding layer IL. Figure 2 The common electrode CE is spaced apart. That is, the shielding layer SHL may not be connected to... Figure 2 The common electrode CE is electrically disconnected or insulated from it. However, the embodiments disclosed herein are not limited thereto. A detailed description of this will be provided later.

[0089] The display device DD may further include a dummy pattern DMP and a guard ring pattern GRP adjacent to the dummy pattern DMP. The dummy pattern DMP and the guard ring pattern GRP are each disposed within the substrate BS and overlap with the pad area PDA. Specifically, the guard ring pattern GRP may be located between the dummy pattern DMP and the signal pad SPD in a plan view. For example, the dummy pattern DMP and the guard ring pattern GRP may include a metallic material. In embodiments, the guard ring pattern GRP and the dummy pattern DMP may be associated with components of the pixel circuit layer (e.g., the pixel circuit portion PXC, see [link to documentation]). Figure 2 In the same layer.

[0090] For example, a protective ring pattern (GRP) can have a surrounding display area in a plan view (e.g., Figure 1 The shape of at least a portion of the display area DA.

[0091] A ground voltage can be applied to the dummy pattern DMP. Additionally, the guard ring pattern GRP disperses electrostatic discharge (ESD) flowing from the outside of the display panel DP into the layered structure of the display panel DP, thereby preventing defects in the display device DD due to ESD. In an embodiment, the display device DD further includes a dummy pattern DMP located within the silicon substrate in the non-display area NDA and receiving a ground voltage, and an ESD pattern (e.g., a guard ring pattern GRP) located within the silicon substrate and adjacent to the dummy pattern DMP.

[0092] In an embodiment, the shielding layer SHL may be connected (e.g., electrically connected) to a dummy pattern DMP or a guard ring pattern GRP. Therefore, electrostatic discharge flowing into the shielding layer SHL from the outside can be induced into the dummy pattern DMP or the guard ring pattern GRP. Thus, defects in the display device DD caused by electrostatic discharge flowing into the display panel DP or its electrical components from the outside can be prevented. However, embodiments of this disclosure are not limited thereto.

[0093] In embodiments, since the shielding layer SHL is in different layers from the dummy pattern DMP and the guard ring pattern GRP, similar to how the light-emitting element layer is connected to the pixel circuit layer at various contact holes as described above, the shielding layer SHL can be connected (e.g., electrically connected) to the dummy pattern DMP or the guard ring pattern GRP at contact holes defined in the insulating layer IL. In this case, a portion of the shielding layer SHL can extend to fill the contact hole. However, embodiments of this disclosure are not limited thereto. In embodiments, the shielding layer SHL can be connected (e.g., electrically connected) to the dummy pattern DMP or the guard ring pattern GRP via another element disposed at a location between the shielding layer SHL and the corresponding patterns in the dummy pattern DMP or the guard ring pattern GRP. As an example, such a location can be defined at... Figure 1 Within the sub-region SA shown.

[0094] Figure 4 It is shown Figure 3 A plan view of the driving circuit section and the shielding layer. Figure 5 , Figure 6 and Figure 7 It is shown Figure 3 A plan view illustrating an example of the planar shape of the shielding layer. Each of the shielding layer SHL and the drive circuit section DDI has a planar shape (or planar region). The entire planar shape (or planar region) of the drive circuit section DDI can be within the planar shape (or planar region) of the shielding layer SHL.

[0095] refer to Figure 4 The shielding layer SHL, serving as an electrostatic shielding layer, can have various planar shapes. In this embodiment, the shielding layer SHL can have a quadrilateral planar shape. For example, the shielding layer SHL can have a rectangular shape. Here, the shielding layer SHL can be a unitary body.

[0096] refer to Figures 5 to 7 In an embodiment, the shielding layers SHL', SHL" and SHL"' may have a planar shape in which a plurality of openings OPN are defined spaced apart from each other.

[0097] In embodiments, the opening OPN may extend completely through the thickness of the shielding layers SHL', SHL" and SHL"' (e.g., openings at both the upper and lower surfaces of the shielding layers SHL', SHL" and SHL"'), but is not limited thereto. Here, reference is made to... Figures 5 to 7 , combined Figure 3The insulating layer IL may be exposed outside the shielding layers SHL', SHL'" and SHL'" at various openings OPN defined as extending through the thickness of the shielding layers SHL', SHL'" and SHL'"". In embodiments, the openings OPN may extend through a portion of the thickness of the shielding layers SHL', SHL'" and SHL'" such that they are recessed from the upper and / or lower surfaces of the shielding layers SHL', SHL'" and SHL'" (and open at the upper and / or lower surfaces of the shielding layers SHL', SHL'" and SHL'"). The openings OPN may be considered to have a separated shape defined within the solid portion of the respective shielding layers SHL', SHL'" and SHL'"".

[0098] For example, such as Figure 5 As shown, each of the openings in the OPN can extend in a first direction DR1 to have a principal plane orientation, and the openings in the OPN can be arranged to be separated from each other along a second direction DR2. That is, the long side defining the principal plane orientation of each of the openings in the OPN can extend in the first direction DR1.

[0099] Optionally, such as Figure 6 As shown, each of the openings in the OPN can extend in the second direction DR2 to have a principal plane orientation, and the openings in the OPN can be arranged to be spaced apart from each other along the first direction DR1. That is, the long side defining the principal plane orientation of each of the openings in the OPN can extend in the second direction DR2.

[0100] Optionally, such as Figure 7 As shown, the openings OPN can be arranged in a matrix along the first direction DR1 and the second direction DR2, and spaced apart from each other in these two directions by the solid portion of the shielding layer SH”’.

[0101] However, embodiments of this disclosure are not limited thereto, and the shielding layers SHL, SHL', SHL" and SHL"' may have the same characteristics as... Figure 4 , Figure 5 , Figure 6 and Figure 7 The planar shapes shown are different.

[0102] Figure 8 It shows along Figure 1 A cross-sectional view of an example section taken by line II-II' in the diagram. In the following text, references will be omitted or simplified. Figure 3 The described content is repeated.

[0103] refer to Figure 1 , Figure 2 and Figure 8The shielding layer SHLa can be disposed on the insulating layer IL and can cover the drive circuit portion DDI in a plan view. Specifically, the shielding layer SHLa can cover the entire drive circuit portion DDI in a plan view. For example, the shielding layer SHLa can include a metallic material. In an embodiment, the shielding layer SHLa can be combined with... Figure 2 The common electrode CE uses the same material. That is, the shielding layer SHLa can be used with... Figure 2 The common electrode CE is formed using the same process.

[0104] Figure 2 The common electrode CE can extend continuously from the display area DA to at least a portion of the non-display area NDA (e.g., at least a portion of the sub-region SA) to define an extension of the common electrode CE in the non-display area NDA. The extension can extend to the driving circuit portion DDI. In an embodiment, the shielding layer SHLa may include... Figure 2 The portion and / or pattern of the common electrode CE that overlaps with the non-display area NDA (e.g., sub-region SA). That is, as shown by the shielding layer SHLa intersecting the (right) dashed line indicating sub-region SA, the shielding layer SHLa can be electrically connected and / or physically connected in the direction along the insulating layer IL. Figure 2 The common electrode CE.

[0105] In an embodiment, the shielding layer SHLa can be connected to a dummy pattern DMP or a guard ring pattern GRP. Therefore, electrostatic discharge flowing into the shielding layer SHLa from the outside can be induced into the dummy pattern DMP or the guard ring pattern GRP. Thus, defects in the display device DD due to electrostatic discharge flowing in from the outside can be prevented. However, embodiments of this disclosure are not limited thereto.

[0106] Figure 9 It shows along Figure 1 A cross-sectional view of an example section taken by line II-II' in the diagram. In the following text, references will be omitted or simplified. Figure 3 The content described is repetitive.

[0107] refer to Figure 1 , Figure 2 and Figure 9 The shielding layer SHLb can be disposed on the insulating layer IL and can cover the drive circuit portion DDI in a plan view. Specifically, the shielding layer SHLb can cover the entire drive circuit portion DDI in a plan view. For example, the shielding layer SHLb can include a metallic material. In an embodiment, the shielding layer SHLb can be combined with... Figure 2 The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 all comprise the same material (i.e., the shielding layer SHLb and Figure 2The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 can be corresponding patterns of the same material layer. That is, the shielding layer SHLb can be... Figure 2 The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are formed using the same process.

[0108] In this embodiment, the shielding layer SHLb can be combined with... Figure 2 The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are spaced apart. That is, as shown by the shielding layer SHLb, which is spaced apart from the (right) dashed line of the indicator sub-region SA, the shielding layer SHLb may not be connected to the insulating layer IL in the direction along which it is located. Figure 2 The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 (e.g., with...) Figure 2 The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are electrically and / or physically disconnected. However, embodiments of this disclosure are not limited thereto, and similar to the shielding layer SHLa intersecting the (right) dashed line indicating the sub-region SA, the shielding layer SHLb can be connected to the insulating layer IL in the direction of the shielding layer IL. Figure 2 The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3.

[0109] In an embodiment, the shielding layer SHLb may be connected to a dummy pattern DMP or a guard ring pattern GRP. Therefore, electrostatic discharge flowing into the shielding layer SHLb from the outside can be induced into the dummy pattern DMP or the guard ring pattern GRP. Thus, defects in the display device DD due to electrostatic discharge flowing from the outside can be prevented. However, embodiments of this disclosure are not limited thereto.

[0110] The shielding layer SHLb can have various planar shapes. For example, the shielding layer SHLb can be combined with... Figure 4 , Figure 5 , Figure 6 and Figure 7 The shielding layers SHL, SHL', SHL" and SHL"' have the same planar shape. However, the embodiments disclosed herein are not limited thereto.

[0111] Figure 10 It shows along Figure 1 A cross-sectional view of an example section taken by line II-II' in the diagram. In the following text, references will be omitted or simplified. Figure 3 The described content is repeated.

[0112] refer to Figure 1 , Figure 2 and Figure 10The shielding layer SHLc can be disposed on the insulating layer IL and can cover the drive circuit portion DDI in a plan view. Specifically, the shielding layer SHLc can cover the entire drive circuit portion DDI in a plan view. For example, the shielding layer SHLc can include an inorganic material. In an embodiment, the shielding layer SHLc can be combined with... Figure 2 The encapsulation layer TFE comprises one or more of the same materials (i.e., the shielding layer SHLc and Figure 2 The encapsulation layer TFE can be a corresponding pattern of the same material layer. In other words, the shielding layer SHLc can be... Figure 2 One or more material layers of the encapsulation layer TFE are formed using the same process.

[0113] Therefore, the shielding layer SHLc can also have the same stacked structure as the encapsulation layer TFE. That is, the shielding layer SHLc can include: a first sublayer SL1 comprising inorganic material; a second sublayer SL2, disposed on the first sublayer SL1 and comprising organic material; and a third sublayer SL3, disposed on the second sublayer SL2 and comprising inorganic material. The first sublayer SL1 can be... Figure 2 The first inorganic encapsulation layer TFE1 comprises the same material, and the second sublayer SL2 can be with... Figure 2 The organic encapsulation layer TFE2 comprises the same material, and the third sublayer SL3 can be with... Figure 2 The second inorganic encapsulation layer, TFE3, comprises the same material.

[0114] Figure 2 The encapsulation layer TFE can extend continuously from the display area DA to at least a portion of the non-display area NDA (e.g., at least a portion of the sub-region SA). In an embodiment, the shielding layer SHLc may include... Figure 2 The portion and / or pattern of the encapsulation layer TFE that overlaps with the non-display area NDA (e.g., sub-area SA). That is, as shown by the shielding layer SHLc intersecting the (right) dashed line indicating sub-area SA, the shielding layer SHLc can be connected along the direction of the insulating layer IL. Figure 2 The encapsulation layer is TFE.

[0115] Figure 11 It shows along Figure 1 A cross-sectional view of an example section taken by line II-II' in the diagram. In the following text, references will be omitted or simplified. Figure 3 The described content is repeated.

[0116] refer to Figure 1 , Figure 2 and Figure 11The shielding layer SHLd can be disposed on the insulating layer IL and can cover the drive circuit portion DDI in a plan view. Specifically, the shielding layer SHLd can cover the entire drive circuit portion DDI in a plan view. For example, the shielding layer SHLd can include glass. In an embodiment, the shielding layer SHLd can be combined with... Figure 2 The packaging substrate ES includes the same materials (i.e., shielding layer SHLd and...). Figure 2 The packaging substrate ES can be a corresponding pattern of the same material layer.

[0117] Figure 2 The encapsulation substrate ES can extend continuously from the display area DA to at least a portion of the non-display area NDA (e.g., at least a portion of the sub-region SA). In an embodiment, the shielding layer SHLd may include... Figure 2 The portion and / or pattern of the encapsulation substrate ES that overlaps with the non-display area NDA (e.g., sub-region SA). That is, as shown by the shielding layer SHLd intersecting the (right) dashed line indicating sub-region SA, the shielding layer SHLd can be connected along the direction of the insulating layer IL. Figure 2 The packaging substrate is ES.

[0118] Refer again Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 According to embodiments of the present disclosure, a display device DD may include: a substrate BS containing a silicon wafer; a driving circuit portion DDI disposed within the substrate BS in a non-display area NDA (e.g., a sub-region SA); and a shielding layer SHL disposed on the driving circuit portion DDI and covering the entire driving circuit portion DDI in a plan view. The shielding layer SHL may correspond to... Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 The shielding layer consists of any one of SHL, SHL', SHL”, SHL”’, SHLa, SHLb, SHLc, and SHLd. Therefore, the shielding layer SHL can block or prevent external electrostatic discharge from flowing into the drive circuit section DDI. In this case, defects in the display device DD caused by electrostatic discharge can be prevented.

[0119] This disclosure can be applied to a variety of display devices. For example, this disclosure applies to various display devices such as those used in vehicles, ships and aircraft, portable communication devices, display devices for exhibitions or information transmission, and medical display devices.

[0120] The foregoing is illustrative of the embodiments and should not be construed as limiting the embodiments. Although several embodiments have been described, it will be readily understood by those skilled in the art that many modifications are possible in the embodiments without departing substantially from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention as defined in the claims. It is therefore to be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting oneself to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, characterized in that, The display device includes: A silicon substrate, the silicon substrate comprising: A display area includes a light-emitting element and a pixel circuit portion, the pixel circuit portion being internal to the silicon substrate and connected to the light-emitting element; and A non-display area, adjacent to the display area, includes: A driving circuit section is located within the silicon substrate and provides electrical signals to the display area via the driving circuit section; and An electrostatic shielding layer covers the drive circuit portion.

2. The display device according to claim 1, characterized in that, The light-emitting element includes: Pixel electrodes are located on the silicon substrate. A light-emitting layer is placed on the pixel electrode; and The common electrode is located on the light-emitting layer.

3. The display device according to claim 2, characterized in that, The electrostatic shielding layer and the common electrode are corresponding patterns of the same material layer.

4. The display device according to claim 2, characterized in that, The electrostatic shielding layer and the pixel electrode are corresponding patterns of the same material layer.

5. The display device according to claim 1, characterized in that, The display device further includes: An encapsulation layer is placed on the light-emitting element and includes an inorganic layer and an organic layer; and The encapsulation substrate faces the encapsulation layer and is formed of glass.

6. The display device according to claim 5, characterized in that, The electrostatic shielding layer and the encapsulation layer are corresponding patterns of the same material layers.

7. The display device according to claim 5, characterized in that, The electrostatic shielding layer and the encapsulation substrate are corresponding patterns of the same material layers.

8. The display device according to claim 1, characterized in that, In the non-display area, the display device further includes: A dummy pattern is disposed within the silicon substrate and receives a ground voltage; and An electrostatic discharge pattern is located inside the silicon substrate and adjacent to the dummy pattern.

9. The display device according to claim 8, characterized in that, The electrostatic shielding layer is connected to the dummy pattern or the electrostatic discharge pattern.

10. The display device according to claim 1, characterized in that, The electrostatic shielding layer has a planar shape in which a plurality of openings spaced apart from each other are defined.

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