Gold bump structure for chip with both pressing area and stability

Abstract

The utility model relates to the technical field of chip application, in particular to a gold bump structure for a chip with both pressing area and stability, which comprises a substrate, a bonding pad, a protective layer and a metal layer. One side of the substrate is connected with a bonding pad, one side of the substrate is connected with a protective layer at equal intervals, and the protective layer is provided with an opening corresponding to the bonding pad; a metal layer is arranged on one side, far away from the substrate, of the bonding pad; by utilizing photoetching exposure (reducing exposure capability and finely adjusting exposure key points), development (prolonging development time or secondary development) and plasma technologies, the bottom of a photoresist window after development is etched outwards and electroplated to form a foundation, so that a gold bump structure can compensate for drilling and etching by using a bottom bump foundation, the aim of miniature bump size is fulfilled, and the cost is reduced. In addition, the bottom foundation of the bump is stable, the gold bump is stable in structure, the gold bump is not prone to toppling and deforming due to chip vibration and shaking and rear-section cutting and washing, and the actual use requirement is met.

Description

Technical Field

[0001] This utility model relates to the field of chip application technology, specifically a gold bump structure for chips that balances bonding area and stability. Background Technology

[0002] Gold and copper-nickel-gold bumping technology is used in the packaging and testing of display driver chips. As display pixels become higher and higher, the number of driver chip pins continues to increase, and the number of bumps per chip also continues to increase, even reaching more than 4,000. Due to the increase in the number of gold bumps, under the requirement of continuous miniaturization of chip size, coupled with the need to reduce costs due to rising gold prices, the spacing and size of gold bumps are also constantly shrinking, and the bumps are becoming more and more slender, which places higher and higher demands on the structural stability of the bumps.

[0003] Under current technology, gold bumps are subject to limitations in photolithography and etching, causing the bottom of the bumps to tilt inward. In addition, etching causes encapsulation drilling, which makes the top of the bumps wide but the bottom narrow, making them prone to instability. During use, as the height of the bumps increases, but the size becomes more and more slender, the gold bump structure becomes more and more unstable. It is easy for the gold bumps to tilt and deform due to chip vibration, shaking, and subsequent cutting and washing, which cannot meet the actual use requirements. Utility Model Content

[0004] The purpose of this invention is to provide a gold bump structure for chips that balances bonding area and stability, in order to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, this utility model provides the following technical solution: a gold bump structure for chips that balances bonding area and stability, comprising a substrate, pads, a protective layer, and a metal layer;

[0006] A pad is connected to one side of the substrate, and a protective layer is equidistantly connected to one side of the substrate, with an opening on the protective layer corresponding to the pad.

[0007] A metal layer is provided on the side of the pad away from the substrate, and the metal layer is connected to an opening on the surface of the protective layer.

[0008] Preferably, the metal layer includes a first connecting layer and a second connecting layer; the first connecting layer is disposed on the side of the metal layer close to the protective layer, and the other side of the first connecting layer is connected to the second connecting layer, and the other side of the second connecting layer is connected to the protective layer.

[0009] Preferably, limiting blocks are equidistantly arranged on the metal layer, and the opening on the side of the metal layer away from the substrate is adapted to and connected to the connecting block at one end of the gold bump body.

[0010] Preferably, the gold bump body has bumps on both the left and right sides, and the bumps are connected to the limiting blocks, and the bumps are triangular.

[0011] Preferably, a cap layer is connected to the other end of the gold bump body, and a connecting layer is connected to the upper surface of the cap layer. The lower surface of the cap layer is partially embedded in the upper surface of the gold bump body, and the connecting layer is partially embedded in the upper surface of the cap layer.

[0012] Preferably, the width of the pad is greater than the width of the opening.

[0013] Compared with the prior art, the beneficial effects of this utility model are:

[0014] This invention proposes a chip gold bump structure that balances bonding area and stability. By utilizing photolithography (reducing exposure power and fine-tuning exposure focus), development (extending development time or double development), and plasma technology, the bottom of the photoresist window is etched outward after development, and a base is formed after electroplating. This allows the gold bump structure to compensate for the drilling with the bottom bump base, achieving both the goal of miniaturizing the bump size and ensuring a more stable bottom base. The stable gold bump structure is less prone to tilting and deformation due to chip vibration, shaking, and subsequent cutting and washing, thus meeting practical application requirements. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the gold bump structure of this utility model;

[0016] Figure 2 This utility model Figure 1 Enlarged schematic diagram of the structure at point A in the middle;

[0017] Figure 3 Schematic diagram of the fabrication of the gold bump structure of this utility model Figure 1 ;

[0018] Figure 4 This is a schematic diagram illustrating the fabrication of the gold bump structure of this utility model. Figure 2 ;

[0019] Figure 5 This is a schematic diagram illustrating the fabrication of the gold bump structure of this utility model. Figure 3 ;

[0020] Figure 6 This is a schematic diagram illustrating the fabrication of the gold bump structure of this utility model. Figure 4 .

[0021] In the figure: substrate 110, pad 120, protective layer 130, metal layer 140, opening 141, limiting block 142, first connecting layer 143, second connecting layer 144, gold bump body 150, cap layer 151, connecting layer 152, connecting block 153, bump 154. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this utility model clear and complete, the embodiments of this utility model will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only some, not all, embodiments of this utility model, and are merely used to explain the embodiments of this utility model. They are not intended to limit the embodiments of this utility model. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0023] Please see Figures 1-6 This utility model provides three technical solutions:

[0024] Example 1: A gold bump structure for chips that balances bonding area and stability, including a substrate 110, a pad 120, a protective layer 130, and a metal layer 140.

[0025] A pad 120 is connected to one side of the substrate 110, and a protective layer 130 is equidistantly connected to one side of the substrate 110, and an opening 141 corresponding to the pad 120 is provided on the protective layer 130.

[0026] The substrate 110 is a conventional chip body structure, such as a common wafer / silicon wafer, whose electrodes are connected to the pads 120, thereby leading out the electrode structure from the pads 120, thus realizing the electrical connection between the substrate 110 and the substrate.

[0027] A metal layer 140 is provided on the side of the pad 120 away from the substrate 110, and the metal layer 140 is connected to the opening 141 on the surface of the protective layer 130.

[0028] Example 2: Based on Example 1, the metal layer 140 includes a first connecting layer 143 and a second connecting layer 144; the first connecting layer 143 is disposed on the side of the metal layer 140 close to the protective layer 130, and the second connecting layer 144 is connected to the other side surface of the first connecting layer 143, and the other side of the second connecting layer 144 is connected to the protective layer 130.

[0029] Limiting blocks 142 are equidistantly arranged on the metal layer 140, and the opening on the side of the metal layer 140 away from the base 110 is adapted to connect with the connecting block 153 at one end of the gold bump body 150.

[0030] Example 3: Based on Example 2, protrusions 154 are provided on the left and right sides of the gold protrusion body 150, and the protrusions 154 are connected to the limiting block 142. The protrusions 154 are set as triangles, and the triangles can increase the stability of the gold protrusion body 150.

[0031] The other end of the gold bump body 150 is connected to a cap layer 151, and the upper surface of the cap layer 151 is connected to a connecting layer 152. The lower surface of the cap layer 151 is partially embedded in the upper surface of the gold bump body 150, and the upper surface of the cap layer 151 is partially embedded in the connecting layer 152.

[0032] The width of pad 120 is greater than the width of opening 141.

[0033] In use, photolithography exposure (reducing exposure power and fine-tuning exposure focus), development (extending development time or secondary development), and plasma technology are used to etch the bottom of the photoresist window outwards after development. After electroplating, a base is formed, which allows the gold bump structure to compensate for the drilling with the bottom bump base, thus achieving the purpose of miniaturizing the bump size and making the bottom base of the bump more stable.

[0034] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A gold bump structure for chips that balances bonding area and stability, characterized in that: It includes a substrate (110), pads (120), a protective layer (130), and a metal layer (140). A pad (120) is connected to one side of the substrate (110), and a protective layer (130) is connected to one side of the substrate (110) at equal intervals, and an opening (141) corresponding to the pad (120) is provided on the protective layer (130). A metal layer (140) is provided on the side of the pad (120) away from the substrate (110), and the metal layer (140) is connected to the opening (141) on the surface of the protective layer (130). Limiting blocks (142) are equidistantly arranged on the metal layer (140), and the opening on the side of the metal layer (140) away from the substrate (110) is adapted to be connected to the connecting block (153) at one end of the gold bump body (150). The gold bump body (150) has bumps (154) on its left and right sides, and the bumps (154) are connected to the limiting block (142), and the bumps (154) are triangular.

2. The chip gold bump structure that balances bonding area and stability according to claim 1, characterized in that: The metal layer (140) includes a first connecting layer (143) and a second connecting layer (144); the first connecting layer (143) is disposed on the side of the metal layer (140) close to the protective layer (130), and the second connecting layer (144) is connected to the other side surface of the first connecting layer (143), and the other side of the second connecting layer (144) is connected to the protective layer (130).

3. The chip gold bump structure that balances bonding area and stability according to claim 1, characterized in that: The other end of the gold bump body (150) is connected to a cap layer (151), and the upper surface of the cap layer (151) is connected to a connecting layer (152). The lower surface of the cap layer (151) is partially embedded in the upper surface of the gold bump body (150), and the upper surface of the cap layer (151) is partially embedded in the connecting layer (152).

4. The chip gold bump structure that balances bonding area and stability according to claim 1, characterized in that: The width of the pad (120) is greater than the width of the opening (141).

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