Shunt monitoring terminal circuit based on building energy consumption test

Abstract

The utility model relates to the technical field of electronic circuits, in particular to a shunt monitoring terminal circuit based on a building energy consumption test, which comprises a field signal generator, a data collector, a master controller and an energy consumption display, the data collector comprises a collection circuit, the collection circuit comprises a collection chip U1, a pin VINA of the collection chip U1 is electrically connected with a resistor R1, and the pin VINA of the collection chip U1 is electrically connected with a resistor R2. The resistor R1 is electrically connected with an operational amplifier U2, and the operational amplifier U2 is provided with a chip U4A and a chip U4B in parallel. Two kinds of reference voltage sources of 1 V and 2 V can be provided in the acquisition chip U1, 2 V reference voltage is adopted, an attenuation circuit is designed at the front end of the acquisition chip U1 by using the operational amplifier U2, the real value of input voltage can be obtained by a digital signal converted by the acquisition chip U1 only through reverse operation according to the requirement of meeting the acquisition voltage range, the structure is simple, and the cost is low. And the operation efficiency and accuracy are greatly improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to monitoring terminal circuit, in particular to based on building energy consumption test's branch monitoring terminal circuit belongs to electronic circuit technical field. BACKGROUND

[0002] In practical application, building energy consumption monitoring system based on LoRa communication technology has been widely applied, the system transmits the energy consumption data of each branch to the monitoring center through LoRa network, realizes real -time monitoring and data analysis to building energy consumption, and simultaneously, through mobile phone APP or cloud platform etc.

[0003] The branch monitoring terminal circuit based on building energy consumption test is a comprehensive engineering, needs to consider multiple factors, and the system architecture design and circuit design points are grasped, but the existing monitoring terminal circuit junction acquisition circuit is more complex, and the reaction is more sluggish, therefore cannot satisfy the demand of use.

[0004] Therefore, it is urgent to improve the monitoring terminal circuit to solve the above -mentioned problems. UTILITY MODEL CONTENT

[0005] The utility model discloses a branch monitoring terminal circuit based on building energy consumption test, and the acquisition chip U1 can provide two kinds of reference voltage sources of 1V and 2V, and the system adopts 2V reference voltage, and an attenuation circuit is designed in the front end of acquisition chip U1 using operational amplifier U2, according to the requirement of satisfying the acquisition voltage range, the digital signal converted by acquisition chip U1 only needs to be reversed to obtain the real value of input voltage, and the structure is simple, and the operation efficiency and accuracy are greatly improved.

[0006] In order to achieve the above object, the main technical scheme of the utility model comprises:

[0007] The branch monitoring terminal circuit based on building energy consumption test includes field signal generator, data collector, main control unit and energy consumption display, and the data collector includes acquisition circuit, and the acquisition circuit includes acquisition chip U1, and the model of acquisition chip U1 is AD9226.

[0008] The pin VINA of acquisition chip U1 is electrically connected with resistance R1, the resistance R1 is electrically connected with operational amplifier U2, chip U4A and chip U4B are arranged in parallel on operational amplifier U2, and chip U4A is connected in series with chip U4B through resistance R9.

[0009] Preferably, the +VS pin of the operational amplifier U2 is connected with +5V voltage, the -VS pin of the operational amplifier U2 is connected with -5V voltage, the +IN pin of the operational amplifier U2 is provided with the resistance R6 and the resistance R8 in parallel, one side of the resistance R8 is electrically connected with the relay J1 away from the operational amplifier U2, and the model of the relay J1 is ADC1N1.

[0010] Preferably, the -IN pin of the operational amplifier U2 is provided with the diode D1 and the diode D2 in parallel between the +IN pin of the operational amplifier U2.

[0011] Preferably, the resistance R1 and the chip U4B are provided with the resistance R11 and the resistance R12 in series, and the models of the chip U4A and the chip U4B are TL072.

[0012] Preferably, the resistance R2 is electrically connected with the pin VINB of the acquisition chip U1, and the capacitor C1 and the capacitor C2 are provided in parallel on the resistance R2.

[0013] Preferably, the capacitor C4 is electrically connected with the pin CAPB of the acquisition chip U1, the capacitor C7 is electrically connected with the pin CAPT of the acquisition chip U1, and the capacitor C5 and the capacitor C6 are provided in parallel between the capacitor C4 and the capacitor C7.

[0014] Preferably, the capacitor C3 is electrically connected with the pin CLK of the acquisition chip U1, and the resistance R3 and the resistance R4 are provided in parallel on one side of the capacitor C3.

[0015] Preferably, the field signal generator comprises a direct current signal generator, an alternating current signal generator and a pulse signal generator.

[0016] The utility model at least has the following beneficial effects:

[0017] 1, the acquisition chip U1 inside can provide 1 V and 2 V two kinds of reference voltage source, and the system in design adopts 2 V reference voltage, utilizes operational amplifier U2 to design a attenuation circuit in acquisition chip U1 front end, according to the requirement of satisfying the acquisition voltage range, the digital signal converted by acquisition chip U1 only needs to be reversed to operate and can obtain the real value of input voltage, and the structure is simple, and the efficiency and accuracy of operation are greatly improved.

[0018] 2, the host controller adopts Virtex-6 FPGA as main control chip, Virtex-6 FPGA is the new generation of high-performance FPGA of Xilinx, multiple gigabit high-speed transceiver is integrated inside, supports multiple IP cores, and performs well in the field of high-speed data acquisition, and the FPGA control module mainly realizes 8-way set chip U1 working time sequence generation, programmable clock circuit control, high-speed optical fiber communication and external trigger signal discrimination. BRIEF DESCRIPTION OF DRAWINGS

[0019] The drawings described herein are used to provide further understanding of the present application, and form part of the present application, the illustrative embodiments of the present application and the description thereof are used to explain the present application, and do not constitute improper limitation on the present application. In the drawings:

[0020] Fig. 1 It is the schematic diagram of the utility model;

[0021] Fig. 2 It is the circuit diagram of the data collector of the utility model.

[0022] In the figure, 1, field signal generator;101, direct current signal generator;102, alternating current signal generator;2, data collector;103, pulse signal generator;201, acquisition circuit;3, host controller;4, energy consumption display. DETAILED DESCRIPTION

[0023] The embodiments of the present application will be described in detail below with the help of drawings and examples, so that the realization process of the present application can be fully understood and implemented by applying technical means to solve technical problems and achieve technical effects.

[0024] As Figs. 1-2 The circuit of the shunt monitoring terminal based on building energy consumption test provided by the embodiment includes a field signal generator 1, a data collector 2, a host controller 3 and an energy consumption display 4. The data collector 2 includes an acquisition circuit 201, and the acquisition circuit 201 includes an acquisition chip U1. The model of the acquisition chip U1 is AD9226. The host controller 3 adopts Virtex-6 FPGA as the main control chip. Virtex-6 FPGA is the new generation of high-performance FPGA of Xilinx, and multiple gigabit high-speed transceivers are integrated inside. It supports multiple IP cores and performs well in the field of high-speed data acquisition. The FPGA control module mainly realizes 8-way set chip U1 working time sequence generation, programmable clock circuit control, high-speed optical fiber communication and external trigger signal discrimination.

[0025] The pin VINA of the acquisition chip U1 is electrically connected with a resistor R1, the resistor R1 is electrically connected with an operational amplifier U2, the operational amplifier U2 is connected in parallel with a chip U4A and a chip U4B, the chip U4A is connected in series with the chip U4B through a resistor R9, the acquisition circuit 201 adopts the model AD9226 chip of the acquisition chip U1, the chip is a single channel, 12 bit, 65MS / s analog-to-digital converter, which can adopt single-ended input or differential input, the acquisition chip U1 can provide two kinds of reference voltage sources of 1 V and 2 V, the system in the design adopts the 2 V reference voltage, since the voltage input range of the acquisition chip U1 is 1.0 V-3.0 V, in order to expand the voltage acquisition range, the system voltage range can reach-5 V~+5 V, an attenuation circuit is designed in front of the acquisition chip U1 by using the operational amplifier U2, according to the requirements of meeting the acquisition voltage range, the attenuation circuit needs to meet:

[0026] Vout=(1 / 5)Vin+2;

[0027] Wherein Vin is the input voltage value, Vout is the output voltage value, the digital signal converted by the acquisition chip U1 only needs to be reversed to obtain the true value of the input voltage, the structure is simple, and the operation efficiency and accuracy are greatly improved.

[0028] Further, as Fig. 2As shown, the +VS pin of the operational amplifier U2 is connected with +5V voltage, the -VS pin of the operational amplifier U2 is connected with -5V voltage, the +IN pin of the operational amplifier U2 is provided with the resistance R6 and the resistance R8 in parallel, the resistance R8 is electrically connected with the relay J1 at the side away from the operational amplifier U2, the model of the relay J1 is ADC1N1, the -IN pin of the operational amplifier U2 is provided with the diode D1 and the diode D2 in parallel between the -IN pin and the +IN pin of the operational amplifier U2, the resistance R11 and the resistance R12 are provided in series between the resistance R1 and the chip U4B, the models of the chip U4A and the chip U4B are both TL072, the resistance R2 is electrically connected with the pin VINB of the acquisition chip U1, the capacitor C1 and the capacitor C2 are provided in parallel on the resistance R2, the capacitor C4 is electrically connected with the pin CAPB of the acquisition chip U1, the capacitor C7 is electrically connected with the pin CAPT of the acquisition chip U1, the capacitor C5 and the capacitor C6 are provided in parallel between the capacitor C4 and the capacitor C7, the capacitor C3 is electrically connected with the pin CLK of the acquisition chip U1, the resistance R3 and the resistance R4 are provided in parallel at the side of the capacitor C3, in the data acquisition process, in order to start the acquisition under certain conditions, the start acquisition command is needed to be sent by the system, and then the specific start acquisition time is controlled by the acquired signal, in order to meet these requirements, the external edge trigger and the gate trigger mode are designed in the system, after the waiting trigger and the trigger type command are sent by the upper computer, the hardware circuit first judges whether the external trigger is needed, and then judges the trigger type, when the trigger type is the external edge trigger, the system starts the acquisition when the first external pulse rising edge comes, and the system stops the acquisition when the next external pulse rising edge comes;

[0029] When the trigger type is the external gate trigger, the acquisition starts when the external pulse is high, and the acquisition stops when the external pulse is low, if the external trigger is not waited, the circuit starts the acquisition directly, the reaction rate is improved, and the timeliness is improved.

[0030] Further, as shown in Fig. 1 The field signal generator 1 includes a direct current signal generator 101, an alternating current signal generator 102 and a pulse signal generator 103, the direct current signal generator 101 mainly outputs a direct current signal, which is used for testing a direct current parameter in a circuit, the alternating current signal generator 102 outputs an alternating current signal, which is used for testing an alternating current parameter and a frequency response in the circuit, and the pulse signal generator 103 generates a pulse signal, which is used for testing a pulse response and a transient characteristic in the circuit, so that the use range and the use flexibility are improved.

[0031] As shown in Figs. 1-2 The principle of the shunt monitoring terminal circuit based on building energy consumption testing provided in the embodiment is as follows:

[0032] It includes field signal generator 1, data collector 2, host 3 and energy consumption display 4, data collector 2 includes acquisition circuit 201, acquisition circuit 201 includes acquisition chip U1, the model of acquisition chip U1 is AD9226, host 3 uses Virtex-6 FPGA as host chip, Virtex-6 FPGA is the new generation of high performance FPGA of Xilinx, internally integrated multiple gigabit high-speed transceiver, supports multiple IP cores, and performs well in the field of high-speed data acquisition, FPGA control module mainly realizes 8-way set chip U1 working time sequence generation, programmable clock circuit control, high-speed optical fiber communication and external trigger signal discrimination;

[0033] The pin VINA of the acquisition chip U1 is electrically connected with the resistor R1, the resistor R1 is electrically connected with the operational amplifier U2, the chip U4A and the chip U4B are arranged in parallel on the operational amplifier U2, the chip U4A is connected in series with the chip U4B through the resistor R9, the acquisition circuit 201 uses the acquisition chip U1 of the model AD9226 chip, the chip is a single-channel, 12-bit, 65MS / s analog-to-digital converter, which can use single-ended input or differential input, the acquisition chip U1 can provide two reference voltage sources of 1 V and 2 V, and the 2 V reference voltage is designed in the system. Since the voltage input range of the acquisition chip U1 is 1.0 V-3.0 V, in order to expand the voltage acquisition range, the system voltage range can reach-5 V~+5 V, an attenuation circuit is designed in front of the acquisition chip U1 by using the operational amplifier U2, which meets the requirements of the acquisition voltage range, has a simple structure, greatly improves the operation efficiency and accuracy.

[0034] As some terms are used in the description and claims to refer to certain components. Those skilled in the art should understand that the same components can be referred to by different names by different hardware manufacturers. The description and claims of this specification do not distinguish components by the difference in name, but by the difference in function. As mentioned throughout the description and claims, "including" is an open term, which should be interpreted as "including but not limited to" or "comprising." "Approximately" means within an acceptable error range, and those skilled in the art can solve technical problems within a certain error range and basically achieve technical effects.

[0035] It should be noted that the terms "include", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the goods or system including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such goods or system. Without more limitation, the element defined by the statement "including a" does not exclude the presence of another identical element in the goods or system including the element.

[0036] The above description shows and describes several preferred embodiments of the present application, but as previously indicated, the present application is not limited to the forms disclosed, but should be accorded the full scope consistent with the patent and principles of patent law, and can be practiced in various other combinations, modifications, and environments, and with the contents of the application concept described herein, by following the teachings or using the knowledge in the relevant art. Any changes and modifications made by those skilled in the art to the present application without departing from the spirit and scope of the present application shall fall within the scope of protection of the claims of the present application.

Claims

1. A branch monitoring terminal circuit based on building energy consumption test, comprising a field signal generator (1), a data collector (2), a main controller (3) and an energy consumption display (4), characterized in that, The data collector (2) comprises a collection circuit (201), and the collection circuit (201) comprises a collection chip U1, and the model of the collection chip U1 is AD9226. A resistor R1 is electrically connected to a pin VINA of the collection chip U1, an operational amplifier U2 is electrically connected to the resistor R1, a chip U4A and a chip U4B are arranged in parallel on the operational amplifier U2, and the chip U4A is connected in series with the chip U4B through a resistor R9.

2. The branch monitoring terminal circuit based on building energy consumption test according to claim 1, characterized in that: A +VS pin of the operational amplifier U2 is connected to +5V voltage, a -VS pin of the operational amplifier U2 is connected to -5V voltage, resistors R6 and R8 are arranged in parallel on a +IN pin of the operational amplifier U2, a relay J1 is electrically connected to a side of the resistor R8 away from the operational amplifier U2, and the model of the relay J1 is ADC1N1.

3. The branch monitoring terminal circuit based on building energy consumption test according to claim 2, characterized in that: Diodes D1 and D2 are arranged in parallel between a -IN pin of the operational amplifier U2 and the +IN pin of the operational amplifier U2.

4. The branch monitoring terminal circuit based on building energy consumption test according to claim 1, characterized in that: Resistors R11 and R12 are arranged in series between the resistor R1 and the chip U4B, and the models of the chip U4A and the chip U4B are TL072.

5. The branch monitoring terminal circuit based on building energy consumption test according to claim 1, characterized in that: A resistor R2 is electrically connected to a pin VINB of the collection chip U1, and capacitors C1 and C2 are arranged in parallel on the resistor R2.

6. The branch monitoring terminal circuit based on building energy consumption test according to claim 1, characterized in that: A capacitor C4 is electrically connected to a pin CAPB of the collection chip U1, a capacitor C7 is electrically connected to a pin CAPT of the collection chip U1, and capacitors C5 and C6 are arranged in parallel between the capacitor C4 and the capacitor C7.

7. The branch monitoring terminal circuit based on building energy consumption test according to claim 1, characterized in that: A capacitor C3 is electrically connected to a pin CLK of the collection chip U1, and a resistor R3 and a resistor R4 are arranged in parallel on one side of the capacitor C3.

8. The branch monitoring terminal circuit based on building energy consumption test according to claim 1, characterized in that: The field signal generator (1) comprises a direct-current signal generator (101), an alternating-current signal generator (102) and a pulse signal generator (103).

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