MOS device

Abstract

The utility model discloses an MOS device which comprises a plurality of source region structures, the source region structures are arranged in an epitaxial layer at intervals in the first direction, the first direction is parallel to the surface, making contact with the epitaxial layer, of a substrate, and the region, located between any two adjacent source region structures, in the epitaxial layer is an epitaxial layer region; the gate structure comprises a first gate structure and at least one second gate structure, the first gate structure comprises a first gate and a first gate oxide layer, the second gate structure comprises a second gate and a second gate oxide layer, and the first gate oxide layer is located on the side, away from the substrate, of the epitaxial layer region and the side, away from the substrate, of part of the source region structure; the first gate is located on the side, away from the substrate, of the first gate oxide layer, the second gate structure is located in the epitaxial layer area, the first gate makes contact with the second gate, and the first gate oxide layer makes contact with the second gate oxide layer. The problem that the on-resistance of a JFET region is large in the prior art is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a MOS device. BACKGROUND

[0002] Compared with traditional Si devices, SiC devices have the characteristics of high voltage, fast frequency and working voltage. For MOSFET in power switching application, one of the most critical device parameters is the on-resistance R DS (on). The R DS (on) measures the effective resistance of the transistor, which directly determines the power efficiency of the MOSFET. In a planar MOSFET, the resistance of the JFET region accounts for a large proportion of the on-resistance. The resistance of the JFET region accounts for a large proportion of the on-resistance. The main way to reduce the JFET region is to increase the implant dose, but too large implant dose will reduce the Vt of the device, and even cause the device to be difficult to turn off. CONTENT OF THE UTILITY MODEL

[0003] The present application provides a MOS device to solve the problem of large on-resistance of the JFET region in the related art.

[0004] According to one aspect of the present application, a MOS device is provided, comprising a substrate and an epitaxial layer located on one side of the substrate, the MOS device further comprising: a plurality of source region structures, the source region structures being spaced apart in the epitaxial layer along a first direction, the first direction being parallel to a surface of the substrate in contact with the epitaxial layer, wherein a region of the epitaxial layer located between any two adjacent source region structures is an epitaxial layer region; a gate structure, the gate structure comprising a first gate structure and at least one second gate structure, the first gate structure comprising a first gate and a first gate oxide layer, the second gate structure comprising a second gate and a second gate oxide layer, the first gate oxide layer being located on a side of the epitaxial layer region away from the substrate and on a side of part of the source region structure away from the substrate, respectively, the first gate being located on a side of the first gate oxide layer away from the substrate, the second gate structure being located in the epitaxial layer region, the first gate being in contact with the second gate, and the first gate oxide layer being in contact with the second gate oxide layer.

[0005] Optionally, a plurality of the second gate structures are spaced apart in a second direction, the second direction being parallel to the surface of the substrate in contact with the epitaxial layer, and the angle between the second direction and the first direction is greater than 0.

[0006] Optionally, the first width of a plurality of the second gate structures along the first direction is the same, and the second width of a plurality of the second gate structures along the second direction is the same.

[0007] Optionally, the first width is 0.1-0.5 μm.

[0008] Optionally, a first interval between any two adjacent second gate structures in the second direction is the same.

[0009] Optionally, the source region structure located on both sides of the second gate structure is a first source region structure and a second source region structure, respectively, a second interval between the second gate structure and the first source region structure in the first direction is the same as a third interval between the second gate structure and the second source region structure in the first direction.

[0010] Optionally, the second gate and the epitaxial layer have the same doping type.

[0011] Optionally, a depth of the second gate structure along a third direction is 0.2-2 μm, the third direction being a direction from the substrate to the gate structure.

[0012] Optionally, the source region structure includes a base region, a first heavily doped region and a second heavily doped region, the first heavily doped region and the second heavily doped region are located on a side of the base region away from the substrate, the first heavily doped region is located on a side of the base region away from the epitaxial layer region, the second heavily doped region is located on a side of the first heavily doped region away from the epitaxial layer region, the base region and the second heavily doped region have the same doping type, the first heavily doped region and the epitaxial layer have the same doping type, wherein the second heavily doped region includes a plurality of sub-heavily doped regions, the plurality of sub-heavily doped regions are arranged at intervals in a fourth direction, the fourth direction being parallel to a surface of the source region structure contacting the epitaxial layer region and perpendicular to the first direction.

[0013] Optionally, a third width of the plurality of sub-heavily doped regions along the first direction is the same, and a fourth width of the plurality of sub-heavily doped regions along the fourth direction is the same.

[0014] The technical scheme of the application provides a MOS device, the MOS device is provided with a second gate structure in the epitaxial layer region in the middle of the adjacent source regions, i.e. the JFET region, the gate in the second gate structure is in contact with the gate of the first gate structure, the gate oxide layer in the second gate structure is in contact with the gate oxide layer of the first gate structure, and then the second gate structure extends to the inside of the JFET region. When the device is normally working, the bottom of the second gate structure induces electrons when the gate applies a positive voltage, because the increase of the electrons will reduce the resistance of the JFET region, and then the electrons induced by the second gate structure can reduce the on-resistance of the device and reduce the resistance of the JFET region. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which form a part of the present application, are intended to provide further understanding of the present application, and are used to interpret the illustrative embodiments of the present application and their descriptions, and do not constitute improper limitations to the present application. In the drawings:

[0016] Figure 1 is a sectional structure schematic diagram of a MOS device according to an embodiment of the present application;

[0017] Figure 2 is a top view structure schematic diagram of a MOS device according to an embodiment of the present application.

[0018] In the above drawings, the following reference signs are included:

[0019] 10, substrate; 20, epitaxial layer; 30, source region structure; 301, first source region structure; 302, second source region structure; 31, base region; 32, first heavily doped region; 33, second heavily doped region; 330, sub heavily doped region; 40, epitaxial layer region; 50, gate structure; 51, first gate structure; 511, first gate; 512, first gate oxide layer; 52, second gate structure; 521, second gate; 522, second gate oxide layer; 61, first conductive layer; 62, second conductive layer. DETAILED DESCRIPTION

[0020] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0021] In order to make the personnel in the technical field better understand the scheme of the present application, the technical scheme in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person of ordinary skill in the art without creative labor should belong to the scope of protection of the present application.

[0022] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, products or devices.

[0023] As described in the background, the resistance of the JFET region in the prior art MOS structure accounts for a large proportion of the on-resistance of the planar MOS device. A large injection dose is usually selected to reduce the resistance, but a large injection dose will cause the voltage of the device to decrease and the device to be difficult to turn off. In order to solve the above problems, the present application provides a MOS device.

[0024] According to one aspect of the present application, a trench power device is provided, as shown in Figure 1 As shown, the MOS device includes a substrate 10 and an epitaxial layer 20 located on one side of the substrate 10. The MOS device further includes: a plurality of source region structures 30, the source region structures 30 being arranged in the epitaxial layer 20 in a first direction A, the first direction A being parallel to the surface of the substrate 10 in contact with the epitaxial layer 20, wherein the region of the epitaxial layer 20 between any two adjacent source region structures 30 is an epitaxial layer region 40; a gate structure 50, the gate structure 50 including a first gate structure 51 and at least one second gate structure 52, the first gate structure 51 including a first gate 511 and a first gate oxide layer 512, the second gate structure 52 including a second gate 521 and a second gate oxide layer 522, the first gate oxide layer 512 being located on one side of the epitaxial layer region 40 away from the substrate 10 and on one side of part of the source region structure 30 away from the substrate 10, the first gate 511 being located on one side of the first gate oxide layer 512 away from the substrate 10, the second gate structure 52 being located in the epitaxial layer region 40, the first gate 511 being in contact with the second gate 521, and the first gate oxide layer 512 being in contact with the second gate oxide layer 522.

[0025] The second gate structure is arranged in the epitaxial layer region between the adjacent source regions of the MOS device, i.e. in the JFET region. The gate of the second gate structure is in contact with the gate of the first gate structure, and the gate oxide layer of the second gate structure is in contact with the gate oxide layer of the first gate structure. The second gate structure extends into the JFET region. When the MOS device is in normal operation, and the gate is applied with a positive voltage, electrons are induced at the bottom of the second gate structure. The JFET region has a higher concentration of electrons, and the resistance of the JFET region is reduced. The electrons induced by the second gate structure can reduce the on-resistance of the MOS device, and reduce the resistance of the JFET region.

[0026] In particular, the JFET region is located between the source and the drain of the MOS device. The JFET region can control the current between the source and the drain. When the MOS device is turned on, the voltage applied to the gate induces electrons under the JFET region, which increases the conductivity of the JFET region, and reduces the on-resistance between the source and the drain. However, the resistance of the JFET region accounts for a large part of the on-resistance of the MOSFET in the on state. Therefore, reducing the resistance of the JFET region is the key to improving the power efficiency of the MOSFET. The charge state of the JFET region is controlled by the gate voltage. When the gate voltage is high enough, it can overcome the depletion effect of the JFET region, and change the JFET region from P-type to N-type or from N-type to P-type, i.e. from depletion state to on state. The MOSFET can control the on-off of the current according to the size of the gate voltage. The presence of the JFET region also helps to maintain the voltage characteristics of the MOSFET, such as the threshold voltage (Vt), and prevents the latch-up effect, which is a common failure mode in high-power devices. When there is a parasitic NPN BJT (bipolar transistor) between the source and the drain, the device may fail under certain conditions. The JFET region can avoid the latch-up effect by ensuring that the source and the P-base region are at the same potential, and increase the stability of the device.

[0027] In some optional embodiments, as shown in FIG. 5, Figure 2 as shown in FIG. 6, Figure 2 as shown in FIG. 7, Figure 1 is a top view of the structure shown in FIG. 7 at the surface of the epitaxial layer region 40 away from the substrate 10. A plurality of second gate structures 52 are arranged at intervals in the second direction B. The second direction B is parallel to the surface of the substrate 10 in contact with the epitaxial layer 20, and the angle between the second direction B and the first direction A is greater than 0. The second gate structure 52 includes a second gate 521 and a second gate oxide layer 522, and the second gate structure 52 is located in the epitaxial layer region 40.

[0028] Specifically, the second gate structure is introduced to induce electrons under the gate oxide, and the increase of the electrons reduces the resistance of the JFET region. However, the second gate structure is located in the JFET region, and the presence of the second gate structure occupies the surface area of the JFET region, reducing the available surface area of the JFET region. The JFET region is an important path for current flow in the MOS device, and when the second gate structure has a large area, the effective current path in the MOS device will also be narrowed, which increases the resistance when the current flows, which will affect the effect of the second gate structure on reducing the resistance of the JFET region. In addition, when the second gate structure has a large area, the large-area second gate structure will change the charge density distribution in the JFET region, especially in the edge region of the second gate structure, which may cause uneven charge aggregation or dispersion, which will also affect the resistance. Therefore, the second gate structure is formed in the second direction with a small hole, which reduces the area of the second gate structure, increases the induced electrons, and reduces the on-resistance of the JFET region as much as possible.

[0029] In some optional embodiments, as shown in FIG. 5, the first width H1 of the plurality of second gate structures 52 along the first direction A is the same, and the second width H2 of the plurality of second gate structures 52 along the second direction B is the same. Figure 2

[0030] Specifically, the plurality of second gate structures have the same first width and second width, which can ensure that each second gate structure has similar conductance characteristics, thereby optimizing the on-resistance of the device and improving the power efficiency. In addition, each second gate structure has the same size, which can ensure the uniformity of the electric field in the device, avoid local changes in the electric field strength, and also avoid the increase of parasitic capacitance and resistance caused by inconsistent sizes of the second gate structure, which affects the switching speed and power loss of the device, thereby improving the switching performance of the device. In addition, in the preparation process of the device, the second gate structure is formed by etching a groove, and consistent sizes of the second gate structure help to improve the processing precision and reduce manufacturing problems caused by inconsistent structure sizes, thereby improving the manufacturing yield and consistency of the device, and maintaining the stability of the manufacturing process.

[0031] In some specific embodiments, the first width is 0.1 μm to 0.5 μm.

[0032] ​Specifically, the second gate structure having a smaller size helps to improve the on-resistance of the device. The first width of the second gate structure is smaller, which can increase the conduction area in the JFET region, reduce the on-resistance, and improve the power efficiency of the device while ensuring more electrons are induced. The smaller first width can result in a lower threshold voltage, which means the device is easier to turn on. In addition, the smaller first width helps to form a shorter path, thereby reducing the parasitic capacitance and inductance in the device, improving the switching speed, and reducing the switching loss. In addition, the width range of 0.1 μm to 0.5 μm is currently controllable by advanced manufacturing processes, which helps to improve the processing precision and reduce the manufacturing difficulty, thereby improving the manufacturing yield.

[0033] In some optional embodiments, as shown in FIG. 2, any two second gate structures 52 adjacent in the second direction B have the same first spacing D1. Figure 2

[0034] Specifically, maintaining the uniform spacing of the second gate structures helps to ensure uniform electric field distribution inside the device, which means that when the device is turned on, the current can be more evenly distributed between the source and the drain, avoiding local overheating and excessive electric field strength, thereby improving the reliability of the device. Since each second gate structure affects the carrier concentration and charge distribution in its surrounding area, uniform spacing can balance these effects inside the device to minimize the on-resistance and improve the power efficiency. In addition, inconsistent second gate structure spacing can introduce parasitic capacitance and resistance, which can affect the switching speed and power loss. Maintaining uniform spacing can reduce these parasitic effects and improve the switching performance and reduce the switching loss of the device. During the preparation of the device, controlling the uniformity of the structure can improve the manufacturing yield and reduce device failures caused by non-uniform structures. Having the same spacing of the second gate structures can reduce the manufacturing difficulty and reduce the process deviation, thereby reducing the production cost.

[0035] In some optional embodiments, as shown in FIG. 2, the source region structure 30 located on both sides of the second gate structure 52 is respectively a first source region structure 301 and a second source region structure 302. The second gate structure 52 and the first source region structure 301 have a second spacing D2 in the first direction A, and the second gate structure 52 and the second source region structure 302 have a third spacing D3 in the first direction A. The second spacing D2 is equal to the third spacing D3. Figure 1

[0036] ​​Specifically, the second spacing is equal to the third spacing, so that the MOS device forms a symmetrical structure, so that the conductive regions formed on both sides of the second gate structure also have symmetry, and the symmetrical conductive regions can form a more uniform electron concentration distribution in the JFET region, reduce the on-resistance of the device, and also avoid the occurrence probability of the latch-up effect, improve the power efficiency and stability of the device. Moreover, the symmetry of the conductive region also helps to form a uniform electric field distribution, which can ensure that the current path between the source and the drain can remain consistent when the device is turned on, avoid local over-high electric field strength, reduce the uneven flow of charge carriers in the device, and improve the stability and reliability of the device. The uniform current distribution and electric field distribution can ensure the consistency of the switching speed, avoid additional energy consumption caused by uneven electric field distribution during the switching process, avoid local overheating, prolong the service life of the device, and improve the thermal stability of the device.

[0037] In some optional embodiments, the second gate has the same doping type as the epitaxial layer.

[0038] Specifically, the second gate has the same doping type as the epitaxial layer. When a positive voltage is applied to the gate during normal operation of the MOS device, electrons will be induced below the second gate structure. Because the second gate and the epitaxial layer have the same doping type, for example, both the second gate and the epitaxial layer are N-type semiconductors, the increase of electrons will reduce the resistance of the region, thereby enabling the induced electrons to reduce the on-resistance of the device.

[0039] In some optional embodiments, as shown in Figure 1 The depth S of the second gate structure 52 along the third direction C is 0.2 μm to 2 μm, and the third direction C is the direction from the substrate 10 to the gate structure 50.

[0040] Specifically, the depth of the second gate structure cannot be too deep or too shallow. A too deep second gate structure will increase the parasitic capacitance and cause the breakdown voltage to decrease, and a too shallow second gate structure will not be able to effectively control the current. The second gate structure is selected to have a depth of 0.2 μm to 2 μm, which ensures that the on-resistance of the JFET region is reduced while ensuring that the electron channel is more effective when turned on, reducing the switching time and switching loss, thereby improving the switching performance of the device. It can also ensure that the device has sufficient blocking ability at high voltage, reduce the leakage current, and improve the off performance and overall efficiency of the device.

[0041] In some optional embodiments, as shown in Figure 1 and Figure 2As shown, the source region structure 30 includes a base region 31, a first heavily doped region 32 and a second heavily doped region 33, the first heavily doped region 32 and the second heavily doped region 33 are both located on the side of the base region 31 away from the substrate 10, the first heavily doped region 32 is located on the side of the base region 31 away from the epitaxial layer region 40, the second heavily doped region 33 is located on the side of the first heavily doped region 32 away from the epitaxial layer region 40, the base region 31 and the second heavily doped region 33 have the same doping type, the first heavily doped region 32 has the same doping type as the epitaxial layer 20, wherein, as shown in Figure 2 As shown, the second heavily doped region 33 includes a plurality of sub-heavily doped regions 330, the plurality of sub-heavily doped regions 330 are arranged in the fourth direction E, the fourth direction E is parallel to the surface of the source region structure 30 in contact with the epitaxial layer region 40 and perpendicular to the first direction A.

[0042] Specifically, in the source region structure, the second heavily doped region can form a long strip type along the fourth direction, or can be arranged in a type of a plurality of small second heavily doped regions arranged at intervals. The first heavily doped region and the second heavily doped region both form an ohmic contact, the first heavily doped region and the base region have different doping types, which can provide additional carriers to reduce the on-resistance. These additional carriers are attracted to the area outside the channel by the gate voltage, increasing the conductivity of the channel, so in the source region structure, the first heavily doped region has the effect of providing carriers to reduce the resistance of the device. While in the source region, the second heavily doped region includes a plurality of sub-heavily doped regions arranged at intervals, which increases the area of the first heavily doped region, while reducing the area of the second heavily doped region forming the ohmic contact, reducing the resistance of the ohmic contact, and further reducing the on-resistance of the device. In addition, the sub-heavily doped regions arranged at intervals can form a depletion layer to provide an additional blocking layer to prevent a direct current path between the source and the drain, thereby reducing the risk of latch-up effect, helping to improve the blocking capability of the device in the off state, reducing the leakage current, thereby improving the off performance and the reliability of the device.

[0043] For example, the epitaxial layer and the first heavily doped region have an N-type doping type, the second heavily doped region and the base region have a P-type doping type, as shown in Figure 1 As shown, the P-type base region 31 can ensure that the device forms an I-depletion layer with the epitaxial layer 20 when off and protects the first gate oxide layer 512; when the device is on, the appropriate surface doping concentration of the P-base region 31 can ensure the required turn-on voltage. The N-type first heavily doped region 32 forms the source, high doping ensures the formation of an ohmic contact and reduces the on-resistance; the P-type second heavily doped region 33 controls the P-type base region 31 and the N-type first heavily doped region 32 at the same potential, avoiding the latch-up effect, wherein the latch-up effect is a parasitic NPN BJT between the source and the drain electrode, under certain conditions, the NPN can be turned on, causing the device to fail. By controlling the N + type first heavily doped region and the P-type base region at the same potential, the NPN can be prevented from being turned on.

[0044] In some specific embodiments, as shown in FIG. 3, the plurality of sub- heavily doped regions 330 have the same third width H3 along the first direction A and the same fourth width H4 along the fourth direction E. Figure 2

[0045] Specifically, when the plurality of sub-heavily doped regions have the same third width and fourth width, i.e., each sub-heavily doped region has the same size, a more uniform electric field distribution can be formed when the device is turned on, the current path can be optimized, the problem of local over-high electric field strength can be reduced, which helps to ensure that the contribution of each base region to the performance of the device is consistent, the balance between the switching speed, leakage current and power loss of the device can be better controlled, and the overall performance of the device can be improved. Moreover, in the preparation process of the device, the consistency of the size of the base region helps to improve the manufacturing precision and repeatability, reduces the performance variation caused by size difference, and thus improves the manufacturing yield and the consistency of the device.

[0046] In some optional embodiments, as shown in FIG. 4, the MOS device further comprises a first conductive layer 61 and a second conductive layer 62, wherein the first conductive layer 61 is located on the side of the second heavily doped region 33 and part of the second heavily doped region 33 away from the substrate, and the second conductive layer 62 is located on the side of the substrate 10 away from the epitaxial layer 20. Figure 1

[0047] Specifically, the first conductive layer can serve as the source electrode of the MOS device, and the second conductive layer can serve as the drain electrode of the MOS device, so as to import or export current for the MOS device, wherein the first conductive layer forms an ohmic contact with the first heavily doped region and the second heavily doped region, respectively, and the second conductive layer forms an ohmic contact with the substrate. In addition, the first gate and the second gate constitute the gate electrode, and the formation of the conduction current in the channel can be realized by adjusting the size of the gate voltage.

[0048] Further, the conductive part and the conductive layer both comprise a conductive material, which includes but is not limited to any one of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium metal or an alloy material. The conductive part comprises one layer of conductive material or multiple layers of conductive material, which can be reasonably selected by those skilled in the art according to actual needs, and is not specifically limited by the application. In addition, the conductive layer and the conductive part of the present application can also comprise a multi-layer conductive structure, which is not specifically limited by the present application.

[0049] ​​It is also to be noted that the terms "comprising", "including", and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0050] The above embodiments of the present application are only used to illustrate the technical solutions of the present application, and not intended to limit the present application. Although the present application is described in detail, it should not be seen as limited to the above. On the contrary, it is the technical solutions of the present application. Within the scope of the spirit and principles, modifications, equivalent replacements, improvements, etc. made by those skilled in the art, should be included in the scope of protection of the present application.

Claims

1. A MOS device, characterized by, The MOS device comprises a substrate and an epitaxial layer on one side of the substrate, and further comprises: a plurality of source region structures, which are arranged in the epitaxial layer in a first direction, the first direction being parallel to a surface of the substrate in contact with the epitaxial layer, wherein a region in the epitaxial layer between any two adjacent source region structures is an epitaxial layer region; a gate structure, which comprises a first gate structure and at least one second gate structure, the first gate structure comprising a first gate and a first gate oxide layer, the second gate structure comprising a second gate and a second gate oxide layer, the first gate oxide layer being located on a side of the epitaxial layer region and part of the source region structure away from the substrate respectively, the first gate being located on a side of the first gate oxide layer away from the substrate, the second gate structure being located in the epitaxial layer region, the first gate being in contact with the second gate, and the first gate oxide layer being in contact with the second gate oxide layer.

2. The MOS device of claim 1, wherein, A plurality of the second gate structures are arranged in a second direction, the second direction being parallel to the surface of the substrate in contact with the epitaxial layer, and the angle between the second direction and the first direction is greater than 0.

3. The MOS device of claim 2, wherein, The first width of a plurality of the second gate structures in the first direction is the same, and the second width of a plurality of the second gate structures in the second direction is the same.

4. The MOS device of claim 3, wherein, The first width is 0.1 μm to 0.5 μm.

5. The MOS device of claim 2, wherein, The first spacing between any two adjacent second gate structures in the second direction is the same.

6. The MOS device of claim 1, wherein, The source region structures located on both sides of the second gate structure are a first source region structure and a second source region structure respectively, the second gate structure and the first source region structure have a second spacing in the first direction, the second gate structure and the second source region structure have a third spacing in the first direction, and the second spacing is equal to the third spacing.

7. The MOS device of claim 1, wherein, The second gate and the epitaxial layer have the same doping type.

8. The MOS device of claim 1, wherein, The depth of the second gate structure in a third direction is 0.2 μm to 2 μm, the third direction being a direction from the substrate to the gate structure.

9. The MOS device of any of claims 1 to 8, wherein, The source region structure comprises a base region, a first heavily doped region and a second heavily doped region, the first heavily doped region and the second heavily doped region are both located on a side of the base region away from the substrate, the first heavily doped region is located on a side of the base region away from the epitaxial layer region, the second heavily doped region is located on a side of the first heavily doped region away from the epitaxial layer region, the base region and the second heavily doped region have the same doping type, the first heavily doped region and the epitaxial layer have the same doping type, and the second heavily doped region comprises a plurality of sub-heavily doped regions, a plurality of the sub-heavily doped regions being arranged in a fourth direction, the fourth direction being parallel to a surface of the source region structure in contact with the epitaxial layer region and perpendicular to the first direction.

10. The MOS device of claim 9, wherein, The third width of a plurality of the sub-heavily doped regions in the first direction is the same, and the fourth width of a plurality of the sub-heavily doped regions in the fourth direction is the same.

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