Display device and electronic device

Abstract

A display device and an electronic device are provided. The display device includes a first sub-pixel and a second sub-pixel, in which each of the first sub-pixel and the second sub-pixel includes a first electrode including a recessed portion, a protective layer in the recessed portion of the first electrode, an electrode layer on the first electrode and the protective layer, a light emitting structure on the electrode layer, and a second electrode on the light emitting structure, wherein the display device includes a trench between the first electrode of the first sub-pixel and the first electrode of the second sub-pixel, and wherein a width of the electrode layer in the first direction is greater than a width of the first electrode in the first direction.

Description

TECHNICAL FIELD

[0001] Aspects of some embodiments of the disclosure relate generally to display devices and electronic devices including the same. BACKGROUND

[0002] Recently, as interest in information display has increased, research and development of display devices has been continuously ongoing.

[0003] The above information disclosed in this Background section is only for enhancing the understanding of the background of the disclosure, and therefore it can not necessarily constitute the prior art. SUMMARY

[0004] Aspects of some embodiments of the disclosure include display devices having relatively improved reliability and methods of manufacturing the same.

[0005] According to some embodiments of the disclosure, a display device includes a first sub-pixel and a second sub-pixel, wherein each of the first sub-pixel and the second sub-pixel includes a first electrode including a recessed portion, a protection layer in the recessed portion of the first electrode, an electrode layer on the first electrode and the protection layer, a light emitting structure on the electrode layer, and a second electrode on the light emitting structure, wherein the display device includes a trench between the first electrode of the first sub-pixel and the first electrode of the second sub-pixel, and wherein a width of the electrode layer in a first direction is greater than a width of the first electrode in the first direction.

[0006] According to some embodiments, the electrode layer can partially protrude on the trench.

[0007] According to some embodiments, the light emitting structure of the first sub-pixel and the light emitting structure of the second sub-pixel can be at least partially separated by the trench.

[0008] According to some embodiments, the first electrode can include a first conductive layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer.

[0009] According to some embodiments, the protection layer can be directly on the third conductive layer.

[0010] According to some embodiments, the first conductive layer and the third conductive layer can include the same material.

[0011] According to some embodiments, the electrode layer can be in contact with the first conductive layer, the second conductive layer, and the third conductive layer.

[0012] According to some embodiments, the electrode layer can include the same material as the third conductive layer.

[0013] According to some embodiments, the trench can at least partially expose the first conductive layer.

[0014] According to some embodiments, the protective layer may include an insulating material. For example, the protective layer may have insulating properties.

[0015] According to some embodiments of the present disclosure, in a method of manufacturing a display device, the method includes: forming an insulating pattern in a boundary region between a first sub-pixel and a second sub-pixel; forming a first electrode in the first sub-pixel, the second sub-pixel, and the boundary region; forming a protective layer on the first electrode; polishing the first electrode and the protective layer in the boundary region; forming an electrode layer on the first electrode and the protective layer; and forming a trench in the boundary region by removing the insulating pattern exposed by the electrode layer.

[0016] According to some embodiments, the trench may at least partially expose the first electrode.

[0017] According to some embodiments, the first electrode may include a recessed portion overlapping with a first sub-pixel and a second sub-pixel. According to some embodiments, a protective layer may be formed in the recessed portion of the first electrode.

[0018] According to some embodiments, the first electrode may include a first conductive layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer. According to some embodiments, the first conductive layer, the third conductive layer, and / or the electrode layer may be formed of the same material.

[0019] According to some embodiments, the width of the electrode layer in the first direction may be formed to be greater than the width of the first electrode in the first direction.

[0020] According to some embodiments, the electrode layer may partially cover the edge of the insulating pattern.

[0021] According to some embodiments, the method may also include forming an insulating layer on the trench and the electrode layer.

[0022] According to some embodiments, the method may also include partially removing the insulating layer formed on the electrode layer.

[0023] According to some embodiments, the insulating layer may be partially formed on the side surface of the trench.

[0024] According to some embodiments, the width of the electrode layer in the first direction may be formed to be equal to the width of the first electrode in the first direction.

[0025] According to some embodiments of this disclosure, an electronic device includes: a processor that provides input image data; and a display device that displays an image based on the input image data. The display device includes sub-pixel regions, wherein the display device includes a first sub-pixel and a second sub-pixel, wherein each of the first sub-pixel and the second sub-pixel includes: a first electrode including a recessed portion; a protective layer in the recessed portion of the first electrode; an electrode layer on the first electrode and the protective layer; a light-emitting structure on the electrode layer; and a second electrode on the light-emitting structure. The display device includes a trench between the first electrode of the first sub-pixel and the first electrode of the second sub-pixel, and wherein the width of the electrode layer in a first direction is greater than the width of the first electrode in the first direction. Attached Figure Description

[0026] A number of exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0027] In drawings, sizes may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, that element can be the only element between the two elements, or there may be one or more intervening elements. Similar reference numerals always refer to similar elements.

[0028] Figure 1 This is a block diagram illustrating various aspects of a display device according to some embodiments.

[0029] Figure 2 This illustrates some embodiments. Figure 1 The diagram shows a block diagram of various aspects of one of the sub-pixels.

[0030] Figure 3 This illustrates some embodiments. Figure 2 The circuit diagram shows further details of the sub-pixels.

[0031] Figure 4 This illustrates some embodiments. Figure 1 A plan view showing further details of the display panel.

[0032] Figure 5 This illustrates some embodiments. Figure 4 An exploded perspective view of a portion of the display panel shown.

[0033] Figure 6 This illustrates some embodiments. Figure 5Plan view of aspects of one of the pixels shown in FIG. 1.

[0034] Figure 7 Cross-sectional view showing further details of the pixel shown in FIG. 1. Figure 6 Cross-sectional view showing further details of the pixel shown in FIG. 1.

[0035] Figure 8 Cross-sectional view showing further details of the pixel shown in FIG. 1. Figure 7 Cross-sectional view showing further details of the pixel shown in FIG. 1.

[0036] Figure 9 Cross-sectional view showing further details of the pixel shown in FIG. 1. Figure 7 Cross-sectional view showing further details of the pixel shown in FIG. 1.

[0037] Figure 10 Cross-sectional view showing further details of the pixel shown in FIG. 1. Figure 7 Cross-sectional view showing further details of the pixel shown in FIG. 1.

[0038] Figure 11 Cross-sectional view showing further details of the pixel shown in FIG. 1. Figure 7 Cross-sectional view showing further details of the pixel shown in FIG. 1.

[0039] Figure 12 Cross-sectional view showing further details of the pixel shown in FIG. 1. Figure 7 Cross-sectional view showing further details of the pixel shown in FIG. 1.

[0040] Figure 13 Cross-sectional view showing further details of the pixel shown in FIG. 1. Figure 5 Plan view of aspects of one of the pixels shown in FIG. 1.

[0041] Figure 14 Plan view of aspects of one of the pixels shown in FIG. 1. Figure 5 Plan view of aspects of one of the pixels shown in FIG. 1.

[0042] Figure 15 Block diagram showing aspects of a display system according to some embodiments.

[0043] Figure 16 Perspective view showing an application instance of the display system shown in FIG. 1. Figure 15 Perspective view showing an application instance of the display system shown in FIG. 1.

[0044] Figure 17 View showing the head-mounted display device shown in FIG. 1 as worn by a user. Figure 16 View showing the head-mounted display device shown in FIG. 1 as worn by a user.

[0045] Figures 18 to 27is a cross-sectional view illustrating aspects of process operations of a method of manufacturing a display apparatus, according to some embodiments.

[0046] Figures 28 to 32 is a cross-sectional view illustrating aspects of process operations of a method of manufacturing a display apparatus, according to some embodiments. DETAILED DESCRIPTION

[0047] Hereinafter, aspects of the disclosed embodiments are described in more detail with reference to the accompanying drawings. In the following description, aspects of some embodiments are described for the purpose of facilitating further understanding of features according to embodiments of the present disclosure, and description of some other parts can be omitted so as not to unnecessarily obscure the subject matter of the present disclosure. Also, embodiments according to the present disclosure are not limited to the disclosed embodiments specifically described herein, but can be implemented in various different forms. Instead, the disclosed embodiments described herein are provided as more thorough and complete description of aspects of some embodiments according to the present disclosure and to impart an ample idea of the ideas of the present disclosure to one of ordinary skill in the art.

[0048] Throughout the specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or be indirectly connected or coupled to the other element through one or more intervening elements. Technical terms used herein are used only for the purpose of illustrating specific embodiments, and are not intended to limit the embodiments. It will be understood that when a component "includes" an element, unless otherwise described to the contrary, it should be understood that the component does not exclude another element, but can further include another element. It will be understood that, for the purpose of the present disclosure, "at least one of X, Y, and Z" can be interpreted as any one of X, Y, and Z, only X, only Y, only Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, XZ). Similarly, for the purpose of the present disclosure, "at least one selected from the group consisting of X, Y, and Z" can be interpreted as any one of X, Y, and Z, only X, only Y, only Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, XZ).

[0049] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a "first" element discussed below could also be termed a "second" element without departing from the teachings of the present disclosure.

[0050] For convenience in description, spatial relative terms, such as "below," "above," and the like, can be used herein for the purpose of describing one element's or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0051] In addition, embodiments of the disclosure are described herein with reference to idealized illustrations (and intermediate structures) of the disclosed embodiments to make such disclosure as comprehensible as possible. It will thus be appreciated that variations in the depicted shapes of the regions can occur. Therefore, embodiments of the disclosure should not be limited to the specific shapes of regions illustrated herein but include any deviation in shapes that can arise from manufacturing techniques and / or tolerances. The regions illustrated in the drawings are schematic in nature and their shapes are not intended to represent the actual shape of a region of a device and do not limit the scope of embodiments according to the disclosure.

[0052] Figure 1 is a block diagram illustrating aspects of a display device according to some embodiments.

[0053] Referring to Figure 1 , the display device 100 can include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0054] The display panel 110 can include sub-pixels SP. The sub-pixels SP can be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The sub-pixels SP can be connected to the data driver 130 through first to n-th data lines DL1 to DLn.

[0055] Each of the sub-pixels SP can include at least one light emitting element configured to generate light. Accordingly, each of the sub-pixels SP can generate light of a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more of the sub-pixels SP can constitute one pixel PXL. For example, as shown in Figure 1 , three sub-pixels SP can constitute one pixel PXL.

[0056] The gate driver 120 can be connected to the sub-pixels SP arranged in a row direction through first to m-th gate lines GL1 to GLm. The gate driver 120 can output a gate signal to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. According to some embodiments, the gate control signal GCS can include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with a timing at which a data signal is applied, and the like.

[0057] According to some embodiments, first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction can also be provided. The gate driver 120 can include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm, and the emission control driver can operate under the control of the controller 150.

[0058] The gate driver 120 can be positioned at one side of the display panel 110. However, embodiments according to the disclosure are not limited thereto. For example, the gate driver 120 can be divided into two or more drivers that are physically and / or logically divided, and the drivers can be positioned at one side of the display panel 110 and another side of the display panel 110 opposite the one side. Thereby, in some embodiments, the gate driver 120 can be arranged in various forms at the periphery of the display panel 110.

[0059] The data driver 130 can be connected to the sub-pixels SP arranged in a column direction through first to n-th data lines DL1 to DLn. The data driver 130 can receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. According to some embodiments, the data control signal DCS can include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0060] The data driver 130 can apply a data signal having a gray voltage corresponding to the image data DATA to the first to n-th data lines DL1 to DLn by using a voltage from the voltage generator 140. When a gate signal is applied to each of the first to m-th gate lines GL1 to GLm, a data signal corresponding to the image data DATA can be applied to the first to n-th data lines DL1 to DLn. Accordingly, a corresponding sub-pixel SP can generate light corresponding to the data signal. Accordingly, an image can be displayed on the display panel 110.

[0061] According to some embodiments, the gate driver 120 and the data driver 130 can include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0062] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 can be configured to generate a plurality of voltages and provide the generated voltages to components of the display apparatus 100. For example, the voltage generator 140 can be configured to generate a plurality of voltages by receiving an input voltage from the outside of the display apparatus 100, adjusting the received voltage, and adjusting the adjusted voltage.

[0063] The voltage generator 140 can generate a first power voltage VDD and a second power voltage VSS, and the generated first power voltage VDD and second power voltage VSS can be provided to the sub-pixels SP. The first power voltage VDD can have a relatively high voltage level, and the second power voltage VSS can have a voltage level lower than that of the first power voltage VDD. According to some embodiments, the first power voltage VDD or the second power voltage VSS can be provided by an external device of the display apparatus 100.

[0064] In addition, the voltage generator 140 can generate various voltages. For example, the voltage generator 140 can generate an initialization voltage applied to the sub-pixels SP. For example, in a sensing operation for sensing electrical characteristics of a transistor and / or a light emitting element of the sub-pixel SP, a reference voltage (e.g., a set or predetermined reference voltage) can be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 can generate the reference voltage.

[0065] The controller 150 can control the overall operation of the display apparatus 100. The controller 150 can receive input image data IMG and a control signal CTRL for controlling the display of the display apparatus 100 from the outside. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0066] The controller 150 can convert the input image data IMG to be suitable for the display apparatus 100 or the display panel 110, thereby outputting image data DATA. According to some embodiments, the controller 150 can align the input image data IMG to be suitable for the sub-pixels SP in units of rows, thereby outputting the image data DATA.

[0067] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 can be mounted on one integrated circuit. As Figure 1As shown in FIG. 1, the data driver 130, the voltage generator 140, and the controller 150 can be included in a driver integrated circuit DIC. The data driver 130, the voltage generator 140, and the controller 150 can be components functionally divided in one driver integrated circuit DIC. According to some embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 can be provided as a component distinguished from the driver integrated circuit DIC.

[0068] The display apparatus 100 can include at least one temperature sensor 160. The temperature sensor 160 can be configured to sense a temperature of its surroundings and to generate temperature data TEP indicative of the sensed temperature. According to some embodiments, the temperature sensor 160 can be arranged adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0069] The controller 150 can control various operations of the display apparatus 100 in response to the temperature data TEP. According to some embodiments, the controller 150 can adjust a luminance of an image output from the display apparatus 100 in response to the temperature data TEP. For example, the controller 150 can control components such as the data driver 130 and / or the voltage generator 140 to adjust data signals as well as the first power voltage VDD and the second power voltage VSS.

[0070] Figure 2 is a block diagram illustrating aspects of one of the sub-pixels shown in FIG. 1 according to some embodiments. Figure 1 is a block diagram illustrating aspects of one of the sub-pixels shown in FIG. 1 according to some embodiments. Figure 2 may be shown in FIG. 1. Figure 1 may be shown in FIG. 1.

[0071] Referring to FIG. 1, Figure 2 The sub-pixel SPijmay include a sub-pixel circuit SPC and a light emitting element LD.

[0072] The light emitting element LD can be connected between a first power voltage node VDDN and a second power voltage node VSSN. The first power voltage node VDDN can be a node through which the first power voltage VDD shown in FIG. 1 is delivered, and the second power voltage node VSSN can be a node through which the second power voltage VSS shown in FIG. 1 is delivered. Figure 1 The light emitting element LD can be connected between a first power voltage node VDDN and a second power voltage node VSSN. The first power voltage node VDDN can be a node through which the first power voltage VDD shown in FIG. 1 is delivered, and the second power voltage node VSSN can be a node through which the second power voltage VSS shown in FIG. 1 is delivered. Figure 1 The light emitting element LD can be connected between a first power voltage node VDDN and a second power voltage node VSSN. The first power voltage node VDDN can be a node through which the first power voltage VDD shown in FIG. 1 is delivered, and the second power voltage node VSSN can be a node through which the second power voltage VSS shown in FIG. 1 is delivered.

[0073] The anode AE ​​of the light-emitting element LD can be connected to the first power voltage node VDDN via the sub-pixel circuit SPC, and the cathode CE of the light-emitting element LD can be connected to the second power voltage node VSSN. For example, the anode AE ​​of the light-emitting element LD can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0074] Sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GL1 to the m-th gate line GLm shown in the figure, Figure 1 The first transmit control line EL1 to the m-th transmit control line ELm shown in the figure are the i-th transmit control line ELi and Figure 1 The j-th data line DLj is shown among the first data lines DL1 to the nth data line DLn. The sub-pixel circuit SPC can be configured to control the light-emitting element LD based on the signals received through these signal lines.

[0075] The sub-pixel circuit (SPC) can operate in response to a gate signal received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. According to some embodiments, such as Figure 2 As shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Thus, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to gate signals received through the corresponding sub-gate lines.

[0076] The sub-pixel circuit SPC can operate in response to a transmission control signal received via the i-th transmission control line ELi. According to some embodiments, the i-th transmission control line ELi may include one or more sub-transmission control lines. When the i-th transmission control line ELi includes two or more sub-transmission control lines, the sub-pixel circuit SPC can operate in response to a transmission control signal received via the corresponding sub-transmission control line.

[0077] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC can control the current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN according to the stored voltage, in response to the emission control signal received via the i-th emission control line ELi. Accordingly, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0078] Figure 3 is a circuit diagram illustrating aspects (e.g., further details) of the sub-pixel shown in Figure 2 Although various components are illustrated in Figure 3 , the structure of the sub-pixel is not limited thereto, and according to some embodiments, the sub-pixel can include additional components or fewer components without departing from the spirit and scope of embodiments according to the present disclosure.

[0079] Referring to Figure 3 , the sub-pixel SPij can include a sub-pixel circuit SPC and a light emitting element LD.

[0080] The sub-pixel circuit SPC can be connected to an i-th gate line GLi', an i-th emission control line ELi', and a j-th data line DLj. The i-th gate line GLi' can further include a third sub-gate line SGL3 when compared to the i-th gate line GLi illustrated in Figure 2 The i-th emission control line ELi' can include a first sub-emission control line SEL1 and a second sub-emission control line SEL2 when compared to the i-th emission control line ELi illustrated in Figure 2

[0081] The sub-pixel circuit SPC can include a first transistor T1 to a sixth transistor T6 and a first capacitor C1 and a second capacitor C2.

[0082] The first transistor T1 can be connected between a first power voltage node VDDN and a first node N1. A gate of the first transistor T1 can be connected to a second node N2, and accordingly, the first transistor T1 can be turned on according to a voltage level of the second node N2. The first transistor T1 can be designated as a driving transistor.

[0083] The second transistor T2 can be connected between the j-th data line DLj and the second node N2. A gate of the second transistor T2 can be connected to a first sub-gate line SGL1, and accordingly, the second transistor T2 can be turned on in response to a gate signal of the first sub-gate line SGL1. The second transistor T2 can be designated as a switching transistor.

[0084] The third transistor T3 can be connected between the first node N1 and the second node N2. A gate of the third transistor T3 can be connected to a second sub-gate line SGL2, and accordingly, the third transistor T3 can be turned on in response to a gate signal of the second sub-gate line SGL2.

[0085] ​The fourth transistor T4 can be connected between the first node N1 and the anode electrode AE of the light emitting element LD. The gate of the fourth transistor T4 can be connected to the second sub emission control line SEL2, and accordingly, the fourth transistor T4 can be turned on in response to an emission control signal of the second sub emission control line SEL2.

[0086] The fifth transistor T5 can be connected between the anode electrode AE of the light emitting element LD and an initialization voltage node VINTN. The initialization voltage node VINTN can be configured to deliver an initialization voltage. According to some embodiments, the initialization voltage can be provided by a voltage generator 140 as shown in FIG. 1B. According to some embodiments, the initialization voltage can be provided by an external device of the display apparatus 100 (e.g., refer to FIG. 1A). Figure 1 Figure 1 The gate of the fifth transistor T5 can be connected to the third sub gate line SGL3, and accordingly, the fifth transistor T5 can be turned on in response to a gate signal of the third sub gate line SGL3.

[0087] The sixth transistor T6 can be connected between the first power voltage node VDDN and the first transistor T1. The gate of the sixth transistor T6 can be connected to the first sub emission control line SEL1, and accordingly, the sixth transistor T6 can be turned on in response to an emission control signal of the first sub emission control line SEL1.

[0088] The first capacitor C1 can be connected between the second transistor T2 and the second node N2. The second capacitor C2 can be connected between the first power voltage node VDDN and the second node N2.

[0089] Thus, the sub-pixel circuit SPC can include the first to sixth transistors T1 to T6 and the first and second capacitors C1 and C2. However, embodiments are not limited thereto. The sub-pixel circuit SPC can be implemented as any one of various types of circuits including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC can include two transistors and one capacitor. According to embodiments of the sub-pixel circuit SPC, the number of sub gate lines included in the i-th gate line GLi' and the number of sub emission control lines included in the i-th emission control line ELi' can vary.

[0090] The first to sixth transistors T1 to T6 can be P-type transistors. Each of the first to sixth transistors T1 to T6 can be a metal oxide semiconductor field effect transistor (MOSEFT). However, embodiments are not limited thereto. For example, at least one of the first to sixth transistors T1 to T6 can be replaced with an N-type transistor.

[0091] According to some embodiments, the first to sixth transistors T1 to T6 can include amorphous silicon semiconductors, single crystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, and the like.​

[0092] The light emitting element LD can include an anode electrode AE, a cathode electrode CE, and a light emitting layer. The light emitting layer can be positioned between the anode electrode AE and the cathode electrode CE. After a data signal transmitted through the jth data line DLj is reflected on a voltage of the second node N2, the fourth transistor T4 and the sixth transistor T6 can be turned on when the emission control signals of the first sub emission control line SEL1 and the second sub emission control line SEL2 are activated to a low level. The first transistor T1 can be turned on according to the voltage of the second node N2, and accordingly, a current can flow from the first power voltage node VDDN to the second power voltage node VSSN. The light emitting element LD can emit light according to an amount of current flowing from the first power voltage node VDDN to the second power voltage node VSSN.

[0093] Figure 4 is a plan view illustrating aspects (e.g., further details) of the display panel shown in Figure 1

[0094] Referring to Figure 4 , as an example of the display panel 110 shown in Figure 1 The display panel DP, as an example of the display panel 110 shown in

[0095] The display panel DP can include a substrate SUB, subpixels SP, and a pad PD.

[0096] When the display panel DP is used as a display screen of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, and the like, the display panel DP can be positioned very close to the eyes of a user. The subpixels SP can be required to have a relatively high integration. To increase the integration of the subpixels SP, the substrate SUB can be provided as a silicon substrate. The subpixels SP and / or the display panel DP can be formed on the substrate SUB as a silicon substrate. The display device 100 (see Figure 1 ) including the display panel DP formed on the substrate SUB as a silicon substrate can be designated as an OLED on silicon (OLEDoS) display device.

[0097] The subpixels SP can be positioned in the display area DA on the substrate SUB. The subpixels SP can be arranged in a matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, embodiments are not limited thereto. For example, the subpixels SP can be arranged in a zigzag form along the first direction DR1 and the second direction DR2. For example, the subpixels SP can be arranged in a form or​ The arrangement. The first direction DR1 can be a row direction, and the second direction DR2 can be a column direction.

[0098] Two or more sub-pixels among the sub-pixels SP can constitute one pixel PXL.

[0099] The components for controlling the sub-pixels SP can be positioned in the non-display area NDA on the substrate SUB. For example, the lines connected to the sub-pixels SP, such as the first data line DL1 to the nth data line DLn shown in FIG. 1, can be positioned in the non-display area NDA. Figure 1 The first gate line GL1 to the mth gate line GLm and the first data line DL1 to the nth data line DLn shown in FIG. 1 can be positioned in the non-display area NDA.

[0100] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 shown in FIG. 1 can be integrated in the non-display area NDA of the display panel DP. According to some embodiments, the gate driver 120 can be mounted on the display panel DP, and can be positioned in the non-display area NDA. According to some embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. According to some embodiments, the temperature sensor 160 can be positioned in the non-display area NDA to sense a temperature of the display panel DP. Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 shown in FIG. 1 can be integrated in the non-display area NDA of the display panel DP. According to some embodiments, the gate driver 120 can be mounted on the display panel DP, and can be positioned in the non-display area NDA. According to some embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. According to some embodiments, the temperature sensor 160 can be positioned in the non-display area NDA to sense a temperature of the display panel DP.

[0101] The pads PD can be positioned in the non-display area NDA on the substrate SUB. The pads PD can be electrically connected to the sub-pixels SP through the lines. For example, the pads PD can be connected to the sub-pixels SP through the first data line DL1 to the nth data line DLn.

[0102] The pads PD can join the display panel DP with other components of the display apparatus 100 (see FIG. 1). According to some embodiments, the voltage and the signal necessary for the operation of the components included in the display panel DP can be provided from the driver integrated circuit DIC through the pads PD. For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit DIC through the pads PD. For example, the first power voltage VDD and the second power voltage VSS can be received from the driver integrated circuit DIC through the pads PD. When the gate driver 120 is mounted in the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pads PD. Figure 1 Figure 5 The pads PD can join the display panel DP with other components of the display apparatus 100 (see FIG. 1). According to some embodiments, the voltage and the signal necessary for the operation of the components included in the display panel DP can be provided from the driver integrated circuit DIC through the pads PD. For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit DIC through the pads PD. For example, the first power voltage VDD and the second power voltage VSS can be received from the driver integrated circuit DIC through the pads PD. When the gate driver 120 is mounted in the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pads PD.

[0103] ​According to some embodiments, the circuit board can be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. The circuit board can be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. The driver integrated circuit DIC can be mounted on the circuit board to be electrically connected to the pad PD.

[0104] According to some embodiments, the display area DA can have various shapes. The display area DA can have a closed loop shape including straight sides and / or curved sides. For example, the display area DA can have shapes such as a polygonal shape, a circular shape, a semi-circular shape, and an elliptical shape.

[0105] According to some embodiments, the display panel DP can have a flat display surface. According to some embodiments, the display panel DP can at least partially have a rounded display surface. According to some embodiments, the display panel DP can be bendable, foldable, or rollable. The display panel DP and / or the substrate SUB can include a material having flexibility.

[0106] Figure 4 is an exploded perspective view showing a portion of the display panel shown in Figure 5 In Figure 4 , for a clear and brief description, portions of the display panel DP corresponding to two pixels PXL1 and PXL2 among the pixels PXL shown in Figure 4 may be schematically shown. Portions of the display panel DP corresponding to other pixels can also be identically configured.

[0107] Referring to Figure 5 and Figure 5 , each of the first pixel PXL1 and the second pixel PXL2 can include the first to third sub-pixels SP1 to SP3. However, embodiments are not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 can include four sub-pixels or include two sub-pixels.

[0108] In Figure 2 , it can be shown that the first to third sub-pixels SP1 to SP3 can have a quadrilateral shape and have the same size when viewed in a third direction DR3 intersecting the first direction DR1 and the second direction DR2. However, embodiments are not limited thereto. The first to third sub-pixels SP1 to SP3 can be modified to have various shapes.

[0109] The display panel DP can include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, a packaging layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0110] According to some embodiments, the substrate SUB can comprise a silicon wafer substrate formed using a semiconductor process. The substrate SUB can comprise a semiconductor material suitable for forming circuit elements. For example, the semiconductor material can comprise silicon, germanium, and / or silicon-germanium. The substrate SUB can be provided from a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like. According to some embodiments, the substrate SUB can comprise a glass substrate. According to some embodiments, the substrate SUB can comprise a polyimide (PI) substrate.

[0111] The pixel circuit layer PCL can be positioned on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL can comprise insulating layers and conductive patterns positioned between the insulating layers. The conductive patterns of the pixel circuit layer PCL can serve as at least some of circuit elements, lines, and the like. The conductive patterns can comprise copper, although embodiments are not limited thereto.

[0112] The circuit elements can comprise sub-pixel circuits SPC of each of the first to third sub-pixels SP1 to SP3 (see Figure 2 ). The sub-pixel circuits SPC can comprise transistors and one or more capacitors. Each transistor can comprise a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. According to some embodiments, when the substrate SUB is provided as a silicon substrate, the semiconductor portion can be included in the substrate SUB, and the gate electrode can be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. According to some embodiments, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode can be included in the pixel circuit layer PCL. Each capacitor can comprise electrodes spaced apart from each other. For example, each capacitor can comprise electrodes spaced apart from each other on a plane defined by the first direction DR1 and the second direction DR2. For example, the capacitors can comprise electrodes spaced apart from each other on the third direction DR3 with an insulating layer therebetween.

[0113] The lines of the pixel circuit layer PCL can comprise signal lines connected to each of the first to third sub-pixels SP1 to SP3, for example, gate lines, emission control lines, data lines, and the like. The lines can further comprise a line connected to the first power voltage node VDDN shown in FIG. 1A. The lines can further comprise a line connected to the second power voltage node VSSN shown in FIG. 1A. Figure 2 Figure 2 The lines of the pixel circuit layer PCL can comprise signal lines connected to each of the first to third sub-pixels SP1 to SP3, for example, gate lines, emission control lines, data lines, and the like. The lines can further comprise a line connected to the first power voltage node VDDN shown in FIG. 1A. The lines can further comprise a line connected to the second power voltage node VSSN shown in FIG. 1A.

[0114] The light-emitting element layer LDL can comprise an anode electrode AE, a light-emitting structure EMS, and a cathode electrode CE.

[0115] The anode electrode AE can be positioned on the pixel circuit layer PCL. The anode electrode AE can be electrically connected to the circuit elements of the pixel circuit layer PCL. The anode electrode AE can comprise an opaque conductive material capable of reflecting light, although embodiments are not limited thereto.​

[0116] The light-emitting structure EMS can be positioned on the anode AE. The light-emitting structure EMS may include a light-emitting layer configured to generate light, an electron transport layer configured to transport electrons, a hole transport layer configured to transport holes, and the like.

[0117] According to some embodiments, the light-emitting structure EMS may extend across the first sub-pixel SP1 to the third sub-pixel SP3. At least some of the layers in the light-emitting structure EMS may be separated (or cut) or bent at the boundary between the first sub-pixel SP1 and the third sub-pixel SP3. However, the embodiments are not limited thereto.

[0118] The cathode CE (or second electrode) can be positioned on the light-emitting structure EMS. The cathode CE can extend across the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Thus, the cathode CE can serve as a common electrode for the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0119] The cathode CE can be a thin metal layer of a thickness sufficient to allow light emitted from the light-emitting structure EMS to pass through it. The cathode CE can be formed of a metallic material to have a relatively thin thickness, or it can be formed of a transparent conductive material. According to some embodiments, the cathode CE may include at least one of various transparent conductive materials comprising indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. According to some embodiments, the cathode CE may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode CE is not limited to these.

[0120] Understandably, any one of the anodes AE, the overlapping portion of the light-emitting structure EMS, and the overlapping portion of the cathode CE constitute a light-emitting element LD (see...). Figure 6 Each of the light-emitting elements in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include an anode AE, a portion of the light-emitting structure EMS overlapping with it, and a portion of the light-emitting structure CE overlapping with it. In each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, holes injected from the anode AE ​​and electrons injected from the cathode CE can be transported to the light-emitting layer of the light-emitting structure EMS to form excitons, and light can be generated when the excitons transition from an excited state to a ground state. The brightness of the light can be determined based on the amount of current flowing through the light-emitting layer. The wavelength band of the generated light can be determined based on the configuration of the light-emitting layer.

[0121] A packaging layer TFE can be positioned on the cathode electrode CE. The packaging layer TFE can cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The packaging layer TFE can be configured to prevent or reduce infiltration of contaminants, such as oxygen and / or moisture, into the light emitting element layer LDL. According to some embodiments, the packaging layer TFE can include a structure in which at least one inorganic layer and at least one organic layer are alternately stacked. For example, the inorganic layer can include silicon nitride, silicon oxide, silicon oxynitride (SiO x N y ) or the like. For example, the organic layer can include an organic insulating material, such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the packaging layer TFE are not limited thereto.

[0122] To relatively increase the packaging efficiency of the packaging layer TFE, the packaging layer TFE can further include a thin film including aluminum oxide (AlO x ) positioned on a top surface of the packaging layer TFE facing the optical function layer OFL and / or a bottom surface of the packaging layer TFE facing the light emitting element layer LDL.

[0123] The thin film including aluminum oxide can be formed through an atomic layer deposition (ALD) process. However, embodiments are not limited thereto. The packaging layer TFE can further include a thin film formed of at least one of various materials suitable for increasing the packaging efficiency.

[0124] The optical function layer OFL can be positioned on the packaging layer TFE. The optical function layer OFL can include a color filter layer CFL and a lens array LA.

[0125] The color filter layer CFL can be positioned between the packaging layer TFE and the lens array LA. The color filter layer CFL can be configured to filter light emitted from the light emitting structure EMS, thereby selectively outputting light of a wavelength band or a color corresponding to each sub-pixel. The color filter layer CFL can include color filters CF corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. Each of the color filters CF can allow light having a wavelength band corresponding to the corresponding sub-pixel to pass therethrough. For example, the color filter corresponding to the first sub-pixel SP1 can allow red light to pass therethrough, the color filter corresponding to the second sub-pixel SP2 can allow green light to pass therethrough, and the color filter corresponding to the third sub-pixel SP3 can allow blue light to pass therethrough. At least some of the color filters CF can be omitted according to light emitted from the light emitting structure EMS in each sub-pixel.

[0126] The lens array LA can be positioned on the color filter layer CFL. The lens array LA can include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS can output light emitted from the light emitting structure EMS along an intended path, thereby relatively improving light emitting efficiency. The lens array LA can have a relatively high refractive index. For example, the lens array LA can have a higher refractive index than that of the outer cover layer OC. According to some embodiments, the lenses LS can include an organic material. According to some embodiments, the lenses LS can include an acryl-based material. However, the material of the lenses LS is not limited thereto.

[0127] The outer cover layer OC can be positioned on the lens array LA. The outer cover layer OC can cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The outer cover layer OC can include various materials suitable for protecting its lower layer from foreign substances such as dust and moisture. For example, the outer cover layer OC can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer cover layer OC can include an epoxy resin, but embodiments are not limited thereto. The outer cover layer OC can have a lower refractive index than that of the lens array LA.

[0128] The cover window CW can be positioned on the outer cover layer OC. The cover window CW can be configured to protect its lower layer. The cover window CW can have a higher refractive index than that of the outer cover layer OC. The cover window CW can include glass, but embodiments are not limited thereto. For example, the cover window CW can be an encapsulation glass configured to protect components positioned on a bottom thereof. According to some embodiments, the cover window CW can be omitted.

[0129] Figure 5 is a plan view illustrating aspects of one of the pixels shown in Figure 6 in FIG. 1A. In Figure 5 in FIG. 1A, for a clear and brief description, the first pixel PXL1 among the first and second pixels PXL1 and PXL2 shown in Figure 5 in FIG. 1A. Other pixels can be configured identically to the first pixel PXL1.

[0130] Referring to Figure 6 and Figure 5 , the first pixel PXL1 can include first to third sub-pixels SP1 to SP3 arranged in a first direction DR1.

[0131] The first sub-pixel SP1 can include a first emission area EMA1 and a non-emission area NEA at a periphery of the first emission area EMA1. The second sub-pixel SP2 can include a second emission area EMA2 and a non-emission area NEA at a periphery of the second emission area EMA2. The third sub-pixel SP3 can include a third emission area EMA3 and a non-emission area NEA at a periphery of the third emission area EMA3.

[0132] The first emission area EMA1 can be an area in which light is emitted from a portion of the light emitting structure EMS (see Figure 7 ) corresponding to the first sub-pixel SP1. The second emission area EMA2 can be an area in which light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 can be an area in which light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3.

[0133] Figure 6 is a cross-sectional view taken along the line I-I' shown in Figure 8 is a cross-sectional view taken along the line I-I' shown in Figure 7 is a cross-sectional view taken along the line I-I' shown in Figure 9 is a cross-sectional view taken along the line I-I' shown in Figure 7 is a cross-sectional view taken along the line I-I' shown in Figure 10 is a cross-sectional view taken along the line I-I' shown in Figure 7 is a cross-sectional view taken along the line I-I' shown in Figure 7 is a cross-sectional view taken along the line I-I' shown in

[0134] Referring to Figure 2 , there can be a substrate SUB and a pixel circuit layer PCL positioned on the substrate SUB.

[0135] The substrate SUB can include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB can include silicon, germanium, and / or silicon-germanium.

[0136] The pixel circuit layer PCL can be positioned on the substrate SUB. The substrate SUB and the pixel circuit layer PCL can include circuit elements of each of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL can include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 can be any one of transistors included in a sub-pixel circuit SPC (see Figure 7 ) of the first sub-pixel SP1, the transistor T_SP2 of the second sub-pixel SP2 can be any one of transistors included in a sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 can be any one of transistors included in a sub-pixel circuit SPC of the third sub-pixel SP3. In Figure 7 , one of the transistors of each sub-pixel is shown for a clear and brief description, and other circuit elements are omitted.

[0137] The transistor T_SP1 of the first sub-pixel SP1 can include a source region SRA, a drain region DRA, and a gate electrode GE.

[0138] The source region SRA and the drain region DRA can be positioned in the substrate SUB. A well WL formed by an ion implantation process can be positioned in the substrate SUB, and the source region SRA and the drain region DRA can be positioned in the well WL and spaced apart from each other. A region between the source region SRA and the drain region DRA in the well WL can be defined as a channel region.

[0139] The gate electrode GE can overlap the channel region between the source region SRA and the drain region DRA and be positioned in the pixel circuit layer PCL. The gate electrode GE can be spaced apart from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE can include a conductive material.

[0140] The multiple layers included in the pixel circuit layer PCL can include insulating layers and conductive patterns positioned between the insulating layers, and the conductive patterns can include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 can be electrically connected to the drain region DRA through a drain connection portion DRC that penetrates one or more insulating layers. The second conductive pattern CP2 can be electrically connected to the source region SRA through a source connection portion SRC that penetrates one or more insulating layers.

[0141] As the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 are connected to other circuit elements and / or lines, the transistor T_SP1 of the first sub-pixel SP1 can be provided as any one of the transistors of the first sub-pixel SP1.

[0142] Each of the transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 can be identically configured as the transistor T_SP1 of the first sub-pixel SP1.

[0143] Thereby, the substrate SUB and / or the pixel circuit layer PCL can include circuit elements of each of the first sub-pixel SP1 to the third sub-pixel SP3.

[0144] A via layer VIAL can be positioned on the pixel circuit layer PCL. The via layer VIAL covers the pixel circuit layer PCL and can have a completely flat surface. The via layer VIAL can be configured to planarize a step difference on the pixel circuit layer PCL. The via layer VIAL can include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon carbonitride (SiCN), but embodiments according to the present disclosure are not limited thereto.

[0145] The light-emitting element layer (LDL) can be positioned on the via layer (VIAL). The LDL may include a first reflective electrode (RE1) to a third reflective electrode (RE3), a planarization layer (PLNL), a first anode (AE1) to a third anode (AE3), a light-emitting structure (EMS), and a cathode (CE).

[0146] The first reflective electrode RE1 to the third reflective electrode RE3 can be respectively positioned in the first sub-pixel SP1 to the third sub-pixel SP3 on the via layer VIAL. Each of the first reflective electrode RE1 to the third reflective electrode RE3 can be electrically connected to a circuit element positioned in the pixel circuit layer PCL through a via penetrating the via layer VIAL.

[0147] The first reflective electrodes RE1 to the third reflective electrodes RE3 can be used as total reflection mirrors to reflect light emitted from the light-emitting structure EMS toward the display surface (or cover window CW). The first reflective electrodes RE1 to the third reflective electrodes RE3 may include metallic materials suitable for reflecting light. The first reflective electrodes RE1 to the third reflective electrodes RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti) and / or alloys of two or more of these materials, but the embodiments are not limited thereto.

[0148] According to some embodiments, the connecting electrode may be positioned at the bottom of each of the first reflective electrodes RE1 to the third reflective electrodes RE3. The connecting electrode may relatively improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuitry layer PCL. The connecting electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), and the like, but the embodiments are not limited thereto. According to some embodiments, the corresponding reflective electrode may be positioned between the multiple layers of the connecting electrode.

[0149] A buffer pattern BFP may be positioned on the bottom of at least one of the first reflective electrodes RE1 to the third reflective electrode RE3. The buffer pattern BFP may comprise an inorganic material such as silicon carbonitride, but embodiments are not limited thereto. As the buffer pattern BFP is formed, the height of the corresponding reflective electrode on the third-direction DR3 can be controlled. For example, the buffer pattern BFP may be positioned between the first reflective electrode RE1 and the via layer VIAL to control the height of the first reflective electrode RE1.

[0150] The first to third reflective electrodes RE1 to RE3 can function as total reflectors, and the cathode electrode CE can function as a half reflector. Light emitted from the light emitting layer of the light emitting structure EMS can be amplified by at least partially reciprocating between the corresponding reflective electrode and the cathode electrode CE, and the amplified light can be output through the cathode electrode CE. Thus, the distance between each reflective electrode and the cathode electrode CE can be understood as a resonance distance of light emitted from the light emitting layer of the corresponding light emitting structure EMS.

[0151] The first sub-pixel SP1 can have a shorter resonance distance than the resonance distance of the other sub-pixels by the buffer pattern BFP. Light in a specific wavelength range (e.g., red) can be effectively and efficiently amplified by the adjusted resonance distance. Accordingly, the first sub-pixel SP1 is capable of effectively and efficiently outputting light in the corresponding wavelength range.

[0152] It is shown in Figure 6 that the buffer pattern BFP is provided to the first sub-pixel SP1 and not provided to the second and third sub-pixels SP2 and SP3. However, embodiments are not limited thereto. The buffer pattern BFP can even be provided in at least one of the second and third sub-pixels SP2 and SP3 to adjust the resonance distance of at least one of the second and third sub-pixels SP2 and SP3. For example, the first to third sub-pixels SP1 to SP3 can correspond to red, green, and blue, respectively. The distance between the first reflective electrode RE1 and the cathode electrode CE can be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE can be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0153] The planarization layer PLNL can be positioned on the via layer VIAL and the first to third reflective electrodes RE1 to RE3 to planarize the step difference between the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL entirely covers the first to third reflective electrodes RE1 to RE3 and the via layer VIAL, and can have a planar surface. According to some embodiments, the planarization layer PLNL can be omitted.

[0154] The first to third anode electrodes AE1 to AE3, which respectively overlap the first to third reflective electrodes RE1 to RE3, can be positioned on the planarization layer PLNL. The first to third anode electrodes AE1 to AE3 can have a planar surface when viewed in the third direction DR3, and can have a step difference with the planarization layer PLNL. Figure 8The first to third emission areas EMA1 to EMA3 can have similar shapes as shown in the middle. The first to third anodes AE1 to AE3 can be electrically connected to the first to third reflective electrodes RE1 to RE3, respectively. The first anode AE1 can be electrically connected to the first reflective electrode RE1 through a first via hole VIA1 penetrating the planarization layer PLNL. The second anode AE2 can be electrically connected to the second reflective electrode RE2 through a second via hole VIA2 penetrating the planarization layer PLNL. The third anode AE3 can be electrically connected to the third reflective electrode RE3 through a third via hole VIA3 penetrating the planarization layer PLNL.

[0155] According to some embodiments, an insulating layer for adjusting a height of at least one of the first to third anodes AE1 to AE3 can also be provided. The insulating layer can be positioned between at least one of the first to third anodes AE1 to AE3 and the corresponding reflective electrode. The planarization layer PLNL and / or the buffer pattern BFP can be omitted. For example, the first to third sub-pixels SP1 to SP3 can correspond to red, green, and blue colors, respectively. A distance between the first anode AE1 and the cathode CE can be shorter than a distance between the second anode AE2 and the cathode CE, and a distance between the second anode AE2 and the cathode CE can be shorter than a distance between the third anode AE3 and the cathode CE.

[0156] A trench TRCH can be provided in a boundary area BDA between the first to third sub-pixels SP1 to SP3 adjacent to each other. The trench TRCH can be provided between the anodes AE of the first to third sub-pixels SP1 to SP3. The trench TRCH can cause a discontinuity in the light emitting structure EMS to be formed in the boundary area BDA. For example, the light emitting structure EMS can be at least partially separated (or cut) or bent by the trench TRCH in the boundary area BDA.

[0157] Referring to Figure 22 The anode AE can include the first electrodes CL1, CL2, and CL3, the protection layer PSV, and / or the electrode layer ETL.

[0158] The first electrodes CL1, CL2, and CL3 can include a recessed portion CL' overlapping each of the first to third sub-pixels SP1 to SP3. In an example, the first electrodes CL1, CL2, and CL3 can include a bottom surface and a side surface formed at an edge of the bottom surface.

[0159] The first electrode CL1, CL2 and CL3 can include a first conductive layer CL1, a second conductive layer CL2 positioned on the first conductive layer CL1, and / or a third conductive layer CL3 positioned on the second conductive layer CL2. The second conductive layer CL2 can be positioned between the first conductive layer CL1 and the third conductive layer CL3. The second conductive layer CL2 can be directly positioned on the first conductive layer CL1. The third conductive layer CL3 can be directly positioned on the second conductive layer CL2.

[0160] The first conductive layer CL1 can include at least one of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), but embodiments are not limited thereto.

[0161] The second conductive layer CL2 can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti), and / or an alloy selected from two or more materials therefrom, but embodiments according to the disclosure are not limited thereto.

[0162] The third conductive layer CL3 can include at least one of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), but embodiments according to the disclosure are not limited thereto. The third conductive layer CL3 can include the same material as the first conductive layer CL1, but embodiments according to the disclosure are not necessarily limited thereto.

[0163] The protective layer PSV can be positioned on the first electrode CL1, CL2 and CL3. The protective layer PSV can be used to protect the first electrode CL1, CL2 and CL3 in a process of forming (or etching) the trench TRCH. The protective layer PSV can be positioned in the recessed portion CL' of the first electrode CL1, CL2 and CL3. The protective layer PSV can be directly positioned on the third conductive layer CL3.

[0164] According to some embodiments, a top surface of the first electrode CL1, CL2 and CL3 and a top surface of the protective layer PSV can be formed to be flat. In an example, the first electrode CL1, CL2 and CL3 and the protective layer PSV can be planarized by chemical mechanical polishing (CMP). This will be described in detail with reference to FIGS. 6A and 6B. Figure 9 This will be described in detail.

[0165] The protective layer PSV can include an insulating material. The protective layer PSV can include a material including silicon oxide (SiO x ), silicon nitride (SiN x), silicon nitride (SiN x , y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), and titanium oxide (TiO x ), but the disclosure is not necessarily limited thereto.

[0166] The electrode layer ETL can be positioned on the first electrodes CL1, CL2, and CL3 and the protective layer PSV. The electrode layer ETL can be positioned on the planar top surfaces of the first electrodes CL1, CL2, and CL3 and the planar top surface of the protective layer PSV. The electrode layer ETL can be electrically connected to the first electrodes CL1, CL2, and CL3. The electrode layer ETL can be positioned directly on the first electrodes CL1, CL2, and CL3. The electrode layer ETL can be positioned directly on the protective layer PSV.

[0167] The electrode layer ETL can include at least one of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), but embodiments according to the disclosure are not limited thereto. The electrode layer ETL can include the same material as the first conductive layer CL1 and / or the third conductive layer CL3, but the disclosure is not necessarily limited thereto.

[0168] According to some embodiments, a width of the electrode layer ETL in the first direction DR1 can be greater than a width of the first electrodes CL1, CL2, and CL3 in the first direction DR1. In an example, side surfaces of the electrode layer ETL can protrude farther than side surfaces of the first electrodes CL1, CL2, and CL3. The electrode layer ETL can partially protrude over the trench TRCH. Thereby, when the electrode layer ETL partially protrudes, the light emitting structure EMS can be easily separated by a tip structure of the electrode layer ETL.

[0169] The trench TRCH can at least partially expose the first conductive layer CL1. The first insulating pattern INP1 can be positioned at a bottom surface of the trench TRCH. The first insulating pattern INP1 can include a material including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x) and titanium oxide (TiO) x Various inorganic insulating materials, but this disclosure is not necessarily limited to them.

[0170] In some embodiments, such as Figure 10 As shown, a first insulating pattern INP1 and a second insulating pattern INP2 can be positioned on the bottom surface of the trench TRCH. The first insulating pattern INP1 may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) and titanium oxide (TiO) x Various inorganic insulating materials, but this disclosure is not necessarily limited to them.

[0171] The second insulating pattern INP2 may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x ), zirconium oxide (ZrO x ), hafnium oxide (HfO) x ) and titanium oxide (TiO) x Various inorganic insulating materials, but this disclosure is not necessarily limited to them.

[0172] According to some embodiments, the first insulating pattern INP1 and the second insulating pattern INP2 may comprise different materials. In one example, when the first insulating pattern INP1 is made of silicon nitride (SiN... x When the second insulating pattern INP2 is formed, it can be formed from silicon oxide (SiO2). x The first insulating pattern INP1 and the second insulating pattern INP2 are formed. Due to the difference in etching selectivity between them, part or all of the second insulating pattern INP2 can be selectively etched. However, the materials constituting the first insulating pattern INP1 and the second insulating pattern INP2 are not necessarily limited to these, and various changes can be made within the range in which the second insulating pattern INP2 can be selectively etched.

[0173] In some embodiments, such as Figure 7As illustrated in FIG. 1, the insulating layer INS can be positioned on the side surface of the trench TRCH. The insulating layer INS can be positioned on the first conductive layer CL1 exposed by the trench TRCH. The insulating layer INS can be spaced apart from the top surface of the first insulating pattern INP1. When the insulating layer INS spaced apart from the first insulating pattern INP1 is formed inside the trench TRCH, the light emitting structure EMS can be easily separated by the separation space. According to some embodiments, the width of the electrode layer ETL in the first direction DR1 can be equal to the width of the first electrodes CL1, CL2, and CL3 in the first direction DR1, but the present disclosure is not necessarily limited thereto.

[0174] The insulating layer INS can include various inorganic insulating materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), and titanium oxide (TiO x ), but the present disclosure is not necessarily limited thereto.

[0175] Referring to Figure 8 , the light emitting structure EMS can be positioned on the anode electrode AE. The light emitting structure EMS can be positioned on the electrode layer ETL (see Figure 11 ). The light emitting structure EMS can be directly positioned on the electrode layer ETL.

[0176] The light emitting structure EMS can be positioned on the trench TRCH. The light emitting structure EMS of each of the first to third sub-pixels SP1 to SP3 can be at least partially separated or bent by the trench TRCH in the boundary area BDA. Some or all of the multiple layers included in the light emitting structure EMS can be separated or bent on the trench TRCH. For example, at least one charge generation layer included in the light emitting structure EMS can be separated by the trench TRCH in the boundary area BDA. Accordingly, in the operation of the display panel DP, the current leaked from each of the first to third sub-pixels SP1 to SP3 to the sub-pixel adjacent to each of the first to third sub-pixels SP1 to SP3 through the layers included in the light emitting structure EMS can be reduced. Accordingly, the first to third light emitting elements LD1 to LD3 can be operated with relatively high reliability.

[0177] The cathode CE can be positioned on the light emitting structure EMS. The cathode CE can be commonly provided in the first to third sub-pixels SP1 to SP3. The cathode CE can function as a half mirror that allows light emitted from the light emitting structure EMS to be partially transmitted therethrough and to be partially reflected therefrom.

[0178] The cathode CE can be connected in the boundary area BDA to be commonly provided in the first to third sub-pixels SP1 to SP3. However, the present disclosure is not necessarily limited thereto. In some embodiments, the cathode CE can be at least partially separated in the boundary area BDA.

[0179] The first anode AE1, a portion of the light emitting structure EMS overlapping the first anode AE1, and a portion of the cathode CE overlapping the first anode AE1 can constitute a first light emitting element LD1. The second anode AE2, a portion of the light emitting structure EMS overlapping the second anode AE2, and a portion of the cathode CE overlapping the second anode AE2 can constitute a second light emitting element LD2. The third anode AE3, a portion of the light emitting structure EMS overlapping the third anode AE3, and a portion of the cathode CE overlapping the third anode AE3 can constitute a third light emitting element LD3.

[0180] The encapsulation layer TFE can be positioned on the cathode CE. The encapsulation layer TFE can prevent or reduce penetration of contaminants such as oxygen and / or moisture into the light emitting element layer LDL.

[0181] The optical function layer OFL can be positioned on the encapsulation layer TFE. According to some embodiments, the optical function layer OFL can be attached to the encapsulation layer TFE through an adhesive layer APL. For example, the optical function layer OFL can be separately manufactured to be attached to the encapsulation layer TFE through the adhesive layer APL. The adhesive layer APL can also perform a function of protecting lower layers including the encapsulation layer TFE.

[0182] The optical function layer OFL can include a color filter layer CFL and a lens array LA. The color filter layer CFL can include first to third color filters CF1 to CF3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third color filters CF1 to CF3 can allow light having different wavelength ranges to pass therethrough. For example, the first to third color filters CF1 to CF3 can allow red light, green light, and blue light, respectively, to pass therethrough.

[0183] According to some embodiments, the first to third color filters CF1 to CF3 can partially overlap each other in the boundary area BDA. According to some embodiments, the first to third color filters CF1 to CF3 can be spaced apart from each other, and a black matrix can be provided between the first to third color filters CF1 to CF3.

[0184] The lens array LA can be positioned on the color filter layer CFL. The lens array LA can include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third lenses LS1 to LS3 can output light emitted from the first to third light emitting elements LD1 to LD3 along the intended path, respectively, thereby relatively improving light emitting efficiency.

[0185] Figure 7 is a cross-sectional view illustrating aspects (e.g., further details) of the light emitting structure in any one of the first to third light emitting elements shown in Figure 11

[0186] Referring to Figure 7 , the light emitting structure EMS can have a series structure in which the first and second light emitting units EU1 and EU2 are stacked. In each of the first to third light emitting elements LD1 to LD3 shown in Figure 12 , the light emitting structure EMS can be configured to be substantially uniform.

[0187] Each of the first and second light emitting units EU1 and EU2 can include at least one light emitting layer generating light according to an applied current. The first light emitting unit EU1 can include a first light emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light emitting layer EML1 can be positioned between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light emitting unit EU2 can include a second light emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light emitting layer EML2 can be positioned between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0188] Each of the first and second hole transport units HTU1 and HTU2 can include at least one of a hole injection layer and a hole transport layer. If necessary, each of the first and second hole transport units HTU1 and HTU2 can further include a hole buffer layer, an electron blocking layer, and the like. The first and second hole transport units HTU1 and HTU2 can have the same configuration or have different configurations.

[0189] Each of the first and second electron transport units ETU1 and ETU2 can include at least one of an electron injection layer and an electron transport layer. If necessary, each of the first and second electron transport units ETU1 and ETU2 can further include an electron buffer layer, a hole blocking layer, and the like. The first and second electron transport units ETU1 and ETU2 can have the same configuration or have different configurations. ​

[0190] A connecting layer, which can be provided in the form of a charge generation layer CGL, can be positioned between a first light-emitting unit EU1 and a second light-emitting unit EU2 to connect the first light-emitting unit EU1 and the second light-emitting unit EU2 to each other. According to some embodiments, the charge generation layer CGL may have a stacked structure of p-doped layers and n-doped layers. For example, the p-doped layer may include a p-type dopant, such as HAT-CN, TCNQ, or NDP-9, and the n-doped layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or any combination thereof. However, the embodiments are not limited thereto.

[0191] According to some embodiments, the first emissive layer EML1 and the second emissive layer EML2 can generate light of different colors. Light emitted from the first emissive layer EML1 and the second emissive layer EML2 respectively can be mixed together to be considered as white light. For example, the first emissive layer EML1 can generate blue light, and the second emissive layer EML2 can generate yellow light. According to some embodiments, the second emissive layer EML2 may include a structure in which a first sub-emissive layer configured to generate red light and a second sub-emissive layer configured to generate green light are stacked. The red light and green light can be mixed together to provide yellow light. An intermediate layer configured to perform the function of transporting holes and / or blocking the transport of electrons may also be positioned between the first sub-emissive layer and the second sub-emissive layer. According to some embodiments, the first emissive layer EML1 and the second emissive layer EML2 can generate light of the same color. The light-emitting structure EMS can be formed by processes such as vacuum deposition or inkjet printing, but the embodiments are not limited thereto.

[0192] Figure 7 It is shown that, according to some embodiments, it includes Figure 12 A cross-sectional view showing further details of the light-emitting structure in one of the first to third light-emitting elements shown.

[0193] Reference Figure 7 The light-emitting structure EMS' can be a series structure in which the first light-emitting unit EU1' to the third light-emitting unit EU3' are stacked. Figure 11 In each of the first light-emitting elements LD1 to the third light-emitting element LD3 shown, the light-emitting structure EMS' can be configured to be substantially identical.

[0194] Each of the first through third light emitting units EU1' through EU3' can include a light emitting layer that generates light according to an applied current. The first light emitting unit EU1' can include a first light emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light emitting layer EML1' can be positioned between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light emitting unit EU2' can include a second light emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light emitting layer EML2' can be positioned between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light emitting unit EU3' can include a third light emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light emitting layer EML3' can be positioned between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0195] Each of the first through third hole transport units HTU1' through HTU3' can include at least one of a hole injection layer and a hole transport layer, and if necessary, a hole buffer layer and an electron blocking layer, and the like. The first through third hole transport units HTU1' through HTU3' can have the same configuration or have different configurations.

[0196] Each of the first through third electron transport units ETU1' through ETU3' can include at least one of an electron injection layer and an electron transport layer, and if necessary, an electron buffer layer, a hole blocking layer, and the like. The first through third electron transport units ETU1' through ETU3' can have the same configuration or have different configurations.

[0197] The first charge generation layer CGL1' can be positioned between the first light emitting unit EU1' and the second light emitting unit EU2'. The second charge generation layer CGL2' can be positioned between the second light emitting unit EU2' and the third light emitting unit EU3'.

[0198] According to some embodiments, the first through third light emitting layers EML1' through EML3' can generate different colors of light. The light emitted from the first through third light emitting layers EML1' through EML3', respectively, can mix together to be perceived as white light. For example, the first light emitting layer EML1' can generate blue light, the second light emitting layer EML2' can generate green light, and the third light emitting layer EML3' can generate red light. According to some embodiments, the light emitting layers of at least two of the first through third light emitting layers EML1' through EML3' can generate the same color of light.

[0199] As described above, the first through third light emitting units EU1' through EU3' can be configured to generate different colors of light. For example, the first light emitting unit EU1' can generate blue light, the second light emitting unit EU2' can generate green light, and the third light emitting unit EU3' can generate red light. According to some embodiments, at least two of the first through third light emitting units EU1' through EU3' can generate the same color of light. Figure 12 and Figure 7different as shown in the middle, Figure 13 The light emitting structure EMS as shown in the middle can include one light emitting unit in each of the first to third light emitting elements LD1 to LD3. The light emitting unit included in each of the first to third light emitting elements LD1 to LD3 can be configured to emit light of a different color. For example, the light emitting unit of the first light emitting element LD1 can emit red light, the light emitting unit of the second light emitting element LD2 can emit green light, and the light emitting unit of the third light emitting element LD3 can emit blue light.

[0200] Figure 5 is a plan view showing further details of one of the pixels according to some embodiments. Figure 13 is a plan view showing further details of one of the pixels according to some embodiments.

[0201] Referring to Figure 14 The first pixel PXL1' can include first to third sub-pixels SP1' to SP3'.

[0202] The first sub-pixel SP1' can include a first emission area EMA1' and a non-emission area NEA' at a periphery of the first emission area EMA1'. The second sub-pixel SP2' can include a second emission area EMA2' and a non-emission area NEA' at a periphery of the second emission area EMA2'. The third sub-pixel SP3' can include a third emission area EMA3' and a non-emission area NEA' at a periphery of the third emission area EMA3'.

[0203] The first sub-pixel SP1' and the second sub-pixel SP2' can be arranged in a second direction DR2. The third sub-pixel SP3' can be positioned in a first direction DR1 with respect to each of the first sub-pixel SP1' and the second sub-pixel SP2'.

[0204] The second sub-pixel SP2' can have an area greater than an area of the first sub-pixel SP1', and the third sub-pixel SP3' can have an area greater than an area of the second sub-pixel SP2'. Accordingly, the second emission area EMA2' can have an area greater than an area of the first emission area EMA1', and the third emission area EMA3' can have an area greater than an area of the second emission area EMA2'. However, embodiments are not limited thereto. For example, the first sub-pixel SP1' and the second sub-pixel SP2' can have substantially the same area, and the third sub-pixel SP3' can have an area greater than an area of each of the first sub-pixel SP1' and the second sub-pixel SP2'. Thereby, in some embodiments, the areas of the first to third sub-pixels SP1' to SP3' can be variously modified.

[0205] Figure 5 is a plan view showing further details of one of the pixels according to some embodiments. Figure 14a plan view of further details of one of the pixels shown in FIGS.

[0206] Referring to Figure 6 , the first pixel PXL1” can include first to third sub-pixels SP1” to SP3”. The first sub-pixel SP1” can include a first emission area EMA1” and a non-emission area NEA” at a periphery of the first emission area EMA1”. The second sub-pixel SP2” can include a second emission area EMA2” and a non-emission area NEA” at a periphery of the second emission area EMA2”. The third sub-pixel SP3” can include a third emission area EMA3” and a non-emission area NEA” at a periphery of the third emission area EMA3”.

[0207] The first to third sub-pixels SP1” to SP3” can have a polygonal shape when viewed in the third direction DR3. For example, the shape of the first to third sub-pixels SP1” to SP3” can be a hexagonal shape.

[0208] The first to third emission areas EMA1” to EMA3” can have a circular shape when viewed in the third direction DR3. However, embodiments are not limited thereto. For example, each of the first to third emission areas EMA1” to EMA3” can have a polygonal shape.

[0209] The first sub-pixel SP1” and the third sub-pixel SP3” can be arranged in the first direction DR1. The second sub-pixel SP2” can be arranged in a direction (or diagonal direction) that is inclined at an acute angle based on the second direction DR2 with respect to the first sub-pixel SP1”.

[0210] Figure 13 , Figure 14 and Figure 15 The arrangement of the sub-pixels shown in FIGS. 1 to 3 is merely illustrative, and embodiments are not limited thereto. Each pixel can include two or more sub-pixels, and the sub-pixels can be arranged in various ways. Each of the sub-pixels can have various shapes, and the emission areas of the sub-pixels can have various shapes.

[0211] Figure 15 is a block diagram illustrating aspects of a display system according to some embodiments.

[0212] Referring to Figure 15 , the display system 1000 can include a processor 1100 and one or more display apparatuses (e.g., a first display apparatus 1210 and a second display apparatus 1220).

[0213] Processor 1100 can perform various tasks and calculations. According to some embodiments, processor 1100 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), and the like. Processor 1100 can be connected to other components of display system 1000 via a bus system to control components of display system 1000.

[0214] exist Figure 1 The diagram shows a display system 1000 including a first display device 1210 and a second display device 1220. A processor 1100 is connected to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0215] Through the first channel CH1, the processor 1100 can send the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can be used with a reference... Figure 1 The described display device 100 is configured uniformly. The first image data IMG1 and the first control signal CTRL1 can be provided respectively as... Figure 1 The input image data IMG and control signal CTRL are shown in the figure.

[0216] Through the second channel CH2, the processor 1100 can send the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 can be used with a reference... Figure 1 The described display device 100 is configured uniformly. The second image data IMG2 and the second control signal CTRL2 can be provided respectively as... Figure 16 The input image data IMG and control signal CTRL are shown in the figure.

[0217] Display system 1000 may include a computing system for providing image display functionality, such as a portable computer, mobile phone, smartphone, tablet PC, smartwatch, watch phone, portable multimedia player (PMP), navigation system, or ultra-mobile computer (UMPC). Display system 1000 may include at least one of head-mounted display (HMD) device, virtual reality (VR) device, mixed reality (MR) device, and augmented reality (AR) device.

[0218] Figure 15 It is shown Figure 16 The image shows a perspective view of an application example of the display system.

[0219] Reference Figure 15 , Figure 15 The display system 1000 shown can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0220] The head-mounted display device 2000 may include a head-mounting strap 2100 and a display device housing 2200. The head-mounting strap 2100 may be connected to the display device housing 2200. The head-mounting strap 2100 may include a lateral strap and / or a longitudinal strap for securing the head-mounted display device 2000 to a user's head. The lateral strap may be configured to surround the side portion of the user's head, and the longitudinal strap may be configured to surround the upper portion of the user's head. However, the embodiments are not limited thereto. For example, the head-mounting strap 2100 may be implemented in the form of an eyeglass frame, a helmet, or the like.

[0221] The display device housing 2200 can accommodate Figure 15 The first display device 1210 and the second display device 1220 are shown. The display device housing 2200 can also accommodate... Figure 17 The processor 1100 shown is shown.

[0222] Figure 16 It shows what the user is wearing. Figure 17 A view of the head-mounted display device shown.

[0223] Reference Figure 15 The first display device 1210 (for example, refer to...) Figure 15 The first display panel DP1 and the second display device 1220 (for example, refer to...) Figures 18 to 27 The second display panel DP2 may be positioned within the head-mounted display device 2000. The head-mounted display device 2000 may also include one or more lenses (e.g., a left lens LLNS and a right lens RLNS).

[0224] Within the display device housing 2200, the right eyeglass lens RLNS can be positioned between the first display panel DP1 and the user's right eye. Within the display device housing 2200, the left eyeglass lens LLNS can be positioned between the second display panel DP2 and the user's left eye.

[0225] The image output from the first display panel DP1 can be viewed by the user's right eye through the right lens RLNS. The right lens RLNS refracts light emitted from the first display panel DP1 towards the user's right eye. The right lens RLNS performs an optical function to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0226] An image output from the second display panel DP2 can be observed by the user's left eye through the left eye lens LLNS. The left eye lens LLNS can refract light emitted from the second display panel DP2 to face the user's left eye. The left eye lens LLNS can perform an optical function for adjusting a viewing distance between the second display panel DP2 and the user's left eye.

[0227] According to some embodiments, each of the right eye lens RLNS and the left eye lens LLNS can include an optical lens having a thin-pie shape cross-section. According to some embodiments, each of the right eye lens RLNS and the left eye lens LLNS can include a multi-channel lens including sub-regions having different optical characteristics. Each display panel can output an image corresponding to the sub-regions of the multi-channel lens, respectively, and the output images can be observed by the user while passing through the corresponding sub-regions, respectively.

[0228] Next, a method of manufacturing the display apparatus according to the above-described embodiments will be described.

[0229] Figures 18 to 27 is a cross-sectional view illustrating aspects of process operations of a method of manufacturing a display apparatus according to some embodiments of the present disclosure. Figures 7 to 9 is a cross-sectional view illustrating a method of manufacturing the display apparatus shown in Figures 18 to 27 For convenience of description, the configuration shown in Figure 18 is briefly shown and detailed reference numerals are omitted.

[0230] Referring to Figure 19 , first, a positive electrode AE is formed on a substrate SUB. The positive electrode AE can be formed to overlap each of the first to third reflective electrodes RE1 to RE3 on a planarization layer PLNL.

[0231] Specifically, referring to Figure 20 , a first insulating pattern INP1 and a second insulating pattern INP2 are formed in a boundary region BDA between the first to third sub-pixels SP1 to SP3.

[0232] The first insulating pattern INP1 can include various inorganic insulating materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), and titanium oxide (TiO x ), but the present disclosure is not necessarily limited thereto.

[0233] The second insulating pattern INP2 can include various inorganic insulating materials including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), and titanium oxide (TiO x ), but the present disclosure is not necessarily limited thereto.

[0234] According to some embodiments, the first insulating pattern INP1 and the second insulating pattern INP2 can include different materials. In an example, when the first insulating pattern INP1 is formed of silicon nitride (SiN x ), the second insulating pattern INP2 can be formed of silicon oxide (SiO x ). However, the present disclosure is not necessarily limited thereto.

[0235] Subsequently, referring to Figure 21 , first to third electrodes CL1, CL2, and CL3 are formed in the first to third sub-pixels SP1 to SP3 and the boundary area BDA. The first to third electrodes CL1, CL2, and CL3 can include a recessed portion CL' overlapping each of the first to third sub-pixels SP1 to SP3. In an example, the first to third electrodes CL1, CL2, and CL3 can include a bottom surface and a side surface formed at an edge of the bottom surface. The side surface of the first to third electrodes CL1, CL2, and CL3 can surround the first insulating pattern INP1 and the second insulating pattern INP2.

[0236] The first to third electrodes CL1, CL2, and CL3 can include a first conductive layer CL1, a second conductive layer CL2 positioned on the first conductive layer CL1, and a third conductive layer CL3 positioned on the second conductive layer CL2. The first conductive layer CL1 can be formed directly on the first insulating pattern INP1 and the second insulating pattern INP2. The second conductive layer CL2 can be formed directly on the first conductive layer CL1. The third conductive layer CL3 can be formed directly on the second conductive layer CL2.

[0237] Referring to Figure 22 , subsequently, a protective layer PSV is formed on the first to third electrodes CL1, CL2, and CL3. The protective layer PSV can be formed directly on the third conductive layer CL3.

[0238] Referring to Figure 23, and then, the first electrodes CL1, CL2, and CL3 and the protective layer PSV are polished. In the process of polishing the first electrodes CL1, CL2, and CL3 and the protective layer PSV, the first electrodes CL1, CL2, and CL3 and the protective layer PSV of the first to third sub-pixels SP1 to SP3 and / or the boundary area BDA can be partially removed. In an example, the first electrodes CL1, CL2, and CL3 and the protective layer PSV can be planarized by chemical mechanical polishing (CMP). Accordingly, top surfaces of the first electrodes CL1, CL2, and CL3 and a top surface of the protective layer PSV can be formed to be flat in the first to third sub-pixels SP1 to SP3 and the boundary area BDA.

[0239] Referring to Figure 24 , and then, an electrode layer ETL is formed on the first electrodes CL1, CL2, and CL3 and the protective layer PSV. The electrode layer ETL can be formed on the flat top surfaces of the first electrodes CL1, CL2, and CL3 and the flat top surface of the protective layer PSV. The electrode layer ETL can be electrically connected to the first electrodes CL1, CL2, and CL3. The electrode layer ETL can be directly formed on the first electrodes CL1, CL2, and CL3. The electrode layer ETL can be directly formed on the protective layer PSV.

[0240] The electrode layer ETL can include an opening at least partially exposing the second insulating pattern INP2. The electrode layer ETL can at least partially cover edges of the second insulating pattern INP2. According to some embodiments, a width of the electrode layer ETL in the first direction DR1 can be formed to be greater than a width of the first electrodes CL1, CL2, and CL3 in the first direction DR1.

[0241] Referring to Figure 25 and Figure 24 , and then, a trench TRCH is formed in the boundary area BDA by etching the second insulating pattern INP2. The second insulating pattern INP2 can be etched through the opening of the electrode layer ETL. The trench TRCH can expose the first electrodes CL1, CL2, and CL3 (e.g., the first conductive layer CL1).

[0242] As shown in Figure 25 , the second insulating pattern INP2 can be partially removed. The second insulating pattern INP2 can remain on the first insulating pattern INP1 at a bottom surface of the trench TRCH. Alternatively, as shown in Figure 26 , the second insulating pattern INP2 can be completely removed. The second insulating pattern INP2 can be selectively etched due to a difference in etching selectivity between the first insulating pattern INP1 and the second insulating pattern INP2. The first insulating pattern INP1 can remain at the bottom surface of the trench TRCH.

[0243] Referring to Figure 27sub-pixels SP1 to SP3 can be separated or bent by the trench TRCH in the boundary area BDA. Some or all of the multiple layers included in the light emitting structure EMS can be separated or bent by the trench TRCH in the boundary area BDA.

[0244] Referring to Figures 7 to 9 , subsequently, a cathode electrode CE is formed on the light emitting structure EMS. The cathode electrode CE can be commonly provided in the first sub-pixel SP1 to the third sub-pixel SP3. The cathode electrode CE can function as a half mirror that allows light emitted from the light emitting structure EMS to be partially transmitted therethrough and to be partially reflected therefrom. The cathode electrode CE can be connected in the boundary area BDA to be commonly provided in the first sub-pixel SP1 to the third sub-pixel SP3.

[0245] Subsequently, a packaging layer TFE, an optical functional layer OFL, an overcoat layer OC, a cover window CW, and the like can be sequentially formed on the light emitting device layer LDL, thereby completing the display device shown in Figures 28 to 32 .

[0246] Hereinafter, aspects of some embodiments of the disclosure will be described in more detail. In the following embodiments, components consistent with the components already described are designated by the same reference numerals, and some overlapping descriptions can be omitted or simplified.

[0247] Figures 28 to 32 is a cross-sectional view illustrating aspects of process operations of a method of manufacturing a display device according to some embodiments of the disclosure. Figure 10 is a cross-sectional view illustrating a method of manufacturing the display device shown in Figures 28 to 32 . For the convenience of description, the configuration shown in Figure 28 is briefly illustrated and detailed reference numerals are omitted.

[0248] Referring to Figures 19 to 22 , an electrode layer ETL is formed on the first electrodes CL1, CL2, and CL3 and the protective layer PSV. The process prior to the process of forming the electrode layer ETL has been described with reference to Figure 29 , and thus the description of the overlapping part will be omitted.

[0249] The electrode layer ETL can be formed on the planar top surfaces of the first electrodes CL1, CL2, and CL3 and the planar top surface of the protective layer PSV. The electrode layer ETL can be electrically connected to the first electrodes CL1, CL2, and CL3. The electrode layer ETL can be directly formed on the first electrodes CL1, CL2, and CL3. The electrode layer ETL can be directly formed on the protective layer PSV.

[0250] The electrode layer ETL can include an opening that at least partially exposes the second insulating pattern INP2 in the boundary area BDA. According to some embodiments, a width of the electrode layer ETL in the first direction DR1 can be formed to be equal to a width of the first electrodes CL1, CL2, and CL3.

[0251] Referring to Figure 30 Subsequently, a trench TRCH is formed by partially etching the second insulating pattern INP2 in the boundary area BDA. The second insulating pattern INP2 can be etched through the opening of the electrode layer ETL. The trench TRCH can expose the first electrodes CL1, CL2, and CL3 (e.g., the first conductive layer CL1). The second insulating pattern INP2 can be partially removed to remain on the first insulating pattern INP1 at a bottom surface of the trench TRCH.

[0252] Referring to Figure 31 Subsequently, an insulating layer INS is formed in the first to third sub-pixels SP1 to SP3 and the boundary area BDA. The insulating layer INS can be formed on the electrode layer ETL and the trench TRCH. The insulating layer INS can be directly formed on the electrode layer ETL. The insulating layer INS can be directly formed on the first conductive layer CL1 exposed by the trench TRCH.

[0253] Referring to Figure 32 Subsequently, the insulating layer INS is partially etched. The insulating layer INS formed on the electrode layer ETL and / or the second insulating pattern INP2 can be partially removed. Accordingly, the insulating layer INS can be partially formed on a side surface of the trench TRCH.

[0254] Referring to ​ Subsequently, the second insulating pattern INP2 exposed by the insulating layer INS is etched. Due to a difference in etching selectivity between the first insulating pattern INP1 and the second insulating pattern INP2, the second insulating pattern INP2 can be selectively etched, and the first insulating pattern INP1 can remain at a bottom surface of the trench TRCH. As a result, when the second insulating pattern INP2 is selectively etched, the insulating layer INS can be spaced apart from a top surface of the first insulating pattern INP1. When the insulating layer INS spaced apart from the first insulating pattern INP1 is formed inside the trench TRCH, the light emitting structure EMS can be easily separated by the separation space, as described above.

[0255] According to some embodiments of the disclosure, the light emitting structure can be separated at least in part by a trench formed in a boundary area between adjacent sub-pixels. Accordingly, a current leaking to an adjacent sub-pixel can be minimized or reduced.

[0256] Aspects in accordance with some embodiments of the present disclosure have been disclosed herein, and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation. In some instances, as will become apparent to those of ordinary skill in the art upon reading the present application, features, characteristics, and / or elements described in conjunction with a particular embodiment can be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically stated. Accordingly, one of ordinary skill in the art will realize that various changes in form and details can be made without departing from the spirit and scope of the embodiments of the present disclosure as defined by the following claims and the equivalents thereof.

Claims

1. A display device, characterized by comprising: comprises: a first sub-pixel and a second sub-pixel, wherein each of the first sub-pixel and the second sub-pixel comprises: a first electrode comprising a recessed portion; a protection layer in the recessed portion of the first electrode; an electrode layer on the first electrode and the protection layer; a light emitting structure on the electrode layer; and a second electrode on the light emitting structure, wherein the display device comprises a trench between the first electrode of the first sub-pixel and the first electrode of the second sub-pixel, and wherein a width of the electrode layer in a first direction is greater than a width of the first electrode in the first direction.

2. The display device of claim 1, wherein, The electrode layer partially protrudes over the trench.

3. The display device of claim 1, wherein The light emitting structure of the first sub-pixel and the light emitting structure of the second sub-pixel are at least partially separated by the trench.

4. The display device of claim 1, wherein The first electrode comprises a first conductive layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer.

5. The display device of claim 4, wherein, The protection layer is directly on the third conductive layer.

6. The display device of claim 4, wherein, The first conductive layer and the third conductive layer comprise the same material.

7. The display device according to claim 4, wherein The electrode layer is in contact with the first conductive layer, the second conductive layer, and the third conductive layer.

8. The display device of claim 4, wherein, The electrode layer comprises the same material as the third conductive layer.

9. The display device according to claim 4, wherein The trench at least partially exposes the first conductive layer.

10. The display device of claim 1, wherein The protection layer has insulating properties.

11. An electronic device, comprising: comprises: a processor providing input image data; and a display device displaying an image based on the input image data, the display device comprising a sub-pixel area, wherein the display device comprises: a first sub-pixel and a second sub-pixel, wherein each of the first sub-pixel and the second sub-pixel comprises: a first electrode comprising a recessed portion; a protection layer in the recessed portion of the first electrode; an electrode layer on the first electrode and the protection layer; a light emitting structure on the electrode layer; and a second electrode on the light emitting structure, wherein the display device comprises a trench between the first electrode of the first sub-pixel and the first electrode of the second sub-pixel, and wherein a width of the electrode layer in a first direction is greater than a width of the first electrode in the first direction.

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