Chip stacking packaging structure combined by multiple connection modes
By combining bonding wires and conductive pillars for electrical connection, along with a redistribution layer, and eliminating the need for a substrate, the problem of traditional packaging thickness limitations is solved, resulting in a thinner and lower-cost chip stacking packaging structure and improved packaging yield.
Patent Information
- Application Number
- CN202423307699.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2026-01-30
- Estimated Expiration
- 2034-12-31
AI Technical Summary
Existing technologies make it difficult to manufacture ultra-thin chip packages. Traditional wire bonding packaging has reached its process limit in terms of thickness. The thickness of the substrate and the chip limits the further thinning of the packaging structure, and the production yield is difficult to guarantee.
By employing a combination of bonding wires and conductive pillars for electrical connection, combined with a redistribution layer, a chip stacked packaging structure is formed, eliminating the need for a substrate. The conductive pillars and conductive bumps are used to electrically connect with the redistribution layer, controlling the packaging thickness and reducing production costs.
It achieves a thinner packaging structure, reduces packaging thickness and production costs, and improves packaging yield. It also achieves a thinner and more controllable packaging structure through multiple connection methods.
Smart Images
Figure CN223859652U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the semiconductor field, and more particularly to the stacked packaging of bare dies in the semiconductor field. Background Technology
[0002] The advanced packaging industry is booming, and the requirements for chip packaging thickness are getting thinner and thinner. However, the chip packaging thickness achieved by traditional wire bonding packaging has reached the limit of the process and equipment. There is an urgent need to use new interconnection methods to create thinner packaging structures.
[0003] 1) Traditional packaging involves stacking chips on a substrate and then electrically connecting them to the metal on the substrate via leads. A certain gap needs to be left between the highest point of the lead of the top layer chip and the plastic cover.
[0004] 2) Traditional wire bonding still requires a substrate as a carrier, and the minimum thickness of the substrate has reached the limit of the process.
[0005] 3) The gap between the top chip and the plastic cover, as well as the minimum processing thickness of the substrate, have reached their limits. If ultra-thin chip packaging is required, the thickness of a single chip needs to be even lower. However, the thinner the single chip, the more difficult it is to guarantee the manufacturing yield. This limits the production of ultra-thin chip packaging. Utility Model Content
[0006] The purpose of this invention is to provide a chip stacking package structure with multiple connection methods. The chip stacking package structure is formed by a combination of bonding wires and conductive pillars, which makes the packaged structure thinner and lower in cost.
[0007] To achieve the above objectives, this utility model provides a chip stacking package structure with multiple connection methods, including a bare die, conductive pillars, conductive bumps, a redistribution layer, and a package body; the bare die includes a third bare die spaced above the front side of the redistribution layer, one or more second bare dies stacked sequentially and staggered on the third bare die, and one or more first bare dies stacked sequentially and staggered on the second bare dies, with the electrode surfaces of the second and third bare dies facing the redistribution layer; the conductive pillars correspond to the electrodes of the second bare die and are supported on the electrode surfaces of the second bare die and the redistribution layer. Between the pads on the front side of the redistribution layer, the electrode of the second die and the pads are electrically connected; the conductive bump corresponds to the electrode of the third die and is supported between the electrode surface of the third die and the pads on the front side of the redistribution layer, and is electrically connected to the electrode of the third die and the pads; there are bonding wires between the second die and the first die, electrically connecting the electrodes of the second die and the first die; the package is located on the front side of the redistribution layer and integrally encapsulates the die, conductive pillars and conductive bumps; the back side of the redistribution layer has solder pads electrically connected to the pads on the redistribution layer.
[0008] Preferably, the second die has a first pad on the electrode surface of the second die, the first pad is electrically connected to the electrode of the second die, and the at least one bonding wire is welded between the first pad and the electrode of the first die.
[0009] Specifically, when the first die has a plurality of electrodes, the bonding wire is between the electrodes of adjacent first dies, and the bonding wire is between the electrode of the bottommost first die and the electrode of the second die.
[0010] Specifically, when the first die has a plurality of electrodes, the bonding wire is between the electrode of each first die and the electrode of the second die.
[0011] Specifically, the second die is relatively misaligned and stacked on the third die along a first direction, the first die is relatively misaligned and stacked on the third die along the first direction in turn, the electrode of the first die is located on one side of the first die in the first direction, the conductive column is located on one side of the second die in the first direction, the first pad is located on one side of the second die in the first direction, and the electrode of the first die is not blocked by the adjacent first die or the second die, and the conductive column is not blocked by the third die.
[0012] Specifically, the electrode of the first die faces the redistribution layer.
[0013] Preferably, the number of the first die is 1-6. Of course, the number of the first die is not limited thereto, and can be set according to actual needs.
[0014] Preferably, when the first die has a plurality of electrodes, the bonding wire is between the electrodes of adjacent first dies, and the bonding wire is between the electrode of the bottommost first die and the electrode of the second die.
[0015] Preferably, when the first die has a plurality of electrodes, the bonding wire is between the electrode of each first die and the electrode of the second die.
[0016] Preferably, the conductive column is protruded on the electrode of the second die.
[0017] Preferably, the conductive column is protruded on a second pad on the electrode surface of the second die, and the second pad is electrically connected to the electrode of the second die through a circuit.
[0018] Preferably, the conductive column is a metal block plated on the second die or a conductive wire welded on the second die, the conductive bump is a metal block plated on the third die or a conductive wire welded on the third die, and the material of the metal block is one or a combination of copper, gold, silver, nickel, and tin.
[0019] Preferably, the package further has a black insulating layer on the back of the redistribution layer.
[0020] Preferably, the height of the conductive bump is 20pm±1pm.
[0021] Preferably, when the second die is multiple, the height difference of the conductive pillars corresponding to the multiple second dies matches the thickness of the multiple second dies.
[0022] Preferably, the second die is one or two.
[0023] Compared with the prior art, the second die and the third die adjacent to the redistribution layer are respectively electrically connected to the pads of the redistribution layer through the conductive pillars and the conductive bumps. Since the conductive pillars provide sufficient height for the arc of the bonding wire during bonding, there is no need to leave sufficient bonding wire interval at the top of the die stack, preventing the arc of the bonding wire at the top of the package from increasing the thickness of the package, so that the thickness of the final package can be controlled by the height of the conductive bump, and the thickness is controllable and can be made relatively thin. On the other hand, the redistribution layer replaces the traditional substrate, effectively reducing the thickness of the package structure formed after packaging. Furthermore, the utility model combines the electrical connection mode of the bonding wire and the conductive pillar, saves the number of conductive pillars, and effectively reduces the process cost during production. BRIEF DESCRIPTION OF DRAWINGS
[0024] Figure 1 is a structural diagram of a chip stack package structure in the embodiment 1 of the utility model.
[0025] Figure 2 is a structural diagram of a chip stack package structure in the embodiment 2 of the utility model.
[0026] Figure 3 is a structural diagram of a chip stack package structure in the embodiment 3 of the utility model.
[0027] Figure 4 is a structural diagram of a chip stack package structure in the embodiment 4 of the utility model.
[0028] Figure 5 is a structural diagram of a chip stack package structure in the embodiment 5 of the utility model. DETAILED DESCRIPTION
[0029] To illustrate the technical content, structural features, purposes and effects of the utility model, the following will be described in detail in combination with the embodiments and the drawings.
[0030] Embodiment 1:
[0031] The utility model discloses a kind of multi-connection mode combined chip stack package structures, including bare chip, conductive column 31, conductive bump 32, rewiring layer 40 and package body 50.
[0032] Reference Figure 1 The bare chip includes third bare chip 23 with spacing on the front face of the rewiring layer 40, second bare chip 22 is stacked on the third bare chip 23 with misplacement, and one or more first bare chips 21 are sequentially stacked on the second bare chip 22 with misplacement, and the electrode face of the second bare chip 22 and third bare chip 23 faces the front face of the rewiring layer 40.
[0033] Specifically, the second bare chip 22 is relatively mispositioned and stacked on the third bare chip 23 along a first direction, the first bare chip 21 is sequentially relatively mispositioned and stacked on the third bare chip 23 along the first direction, the electrode of the first bare chip 21 is located on one side of the first bare chip 21 in the first direction of the central axis, the conductive column 31 is located on one side of the second bare chip 22 in the first direction of the central axis, the first solder pad 33 is located on one side of the second bare chip 22 in the first direction of the central axis, and the electrode of the first bare chip 21 is not shielded by the adjacent first bare chip 21 or second bare chip 22, and the conductive column 31 is not shielded by the third bare chip 23. Wherein, the electrode face of the first bare chip 21 faces the rewiring layer 40.
[0034] Reference Figure 1 The conductive column 31 is supported between the electrode face of the second bare chip 22 and the pad 41 of the rewiring layer 40, and electrically communicates the electrode of the second bare chip 22 and the pad 41 on the rewiring layer 40. In the embodiment, the conductive column 31 is protruded on the electrode of the second bare chip 22. Of course, different from this, a second solder pad electrically connected to the electrode of the second bare chip 22 can also be arranged on the electrode face of the second bare chip 22, and then the conductive column 31 is protruded on the second solder pad, and the second solder pad is electrically connected to the electrode of the second bare chip 22 through a circuit.
[0035] Reference Figure 1 The conductive bump 32 is supported between the electrode face of the third bare chip 23 and the pad 41 of the rewiring layer 40, and electrically communicates the electrode of the third bare chip 23 and the pad 4 on the rewiring layer 40. The conductive bump 32 can be directly formed on the electrode of the third bare chip 23, or can be formed on the electrode face of the third bare chip 23 in a non-electrode area and then electrically connected to the electrode of the third bare chip 23 through a circuit.
[0036] The conductive column 31 and the conductive bump 32 are metal blocks, in the embodiment, the conductive column 31 and the conductive bump 32 are metal blocks plated on the second bare die 22 and the third bare die 23, which are plated metal blocks. Of course, different from this, the conductive column 31 can also be a conductive wire, such as a copper wire, a gold wire, etc., welded on the second bare die 22. The material of the metal block is one or a combination of more of copper, gold, silver, nickel, and tin.
[0037] The height of the conductive bump 32 is 20pm±1pm.
[0038] Referring to Figure 1 , the second bare die 22 and the first bare die 21 have a bonding wire electrically connecting the electrode of the second bare die 22 and the electrode of the first bare die 21. In the embodiment, the electrode surface of the second bare die 22 also has a first soldering pad 33 electrically connected to the electrode of the second bare die 22, and at least one bonding wire is welded between the first soldering pad 33 and the electrode of the first bare die 21. Of course, different from this, the bonding wire can also be directly arranged on the electrode of the second bare die 22 and the electrode of the first bare die 21, without the need to arrange the first soldering pad 33.
[0039] Referring to Figure 1 , in the embodiment, when the first bare die 21 has multiple, the electrodes of adjacent first bare dies 21 have the bonding wire, and the electrode of the bottommost first bare die 21 and the first soldering pad 33 have the bonding wire.
[0040] Referring to Figure 1 , the package 50 is located on the front surface of the redistribution layer 40 and integrally wraps the bare dies (including the first bare die 21, the second bare die 22, and the third bare die 23), the conductive column 31, and the conductive bump 32. The package 50 is tightly connected with the redistribution layer 40. Among them, the redistribution layer 40 is directly grown on the package 50.
[0041] Referring to Figure 1 , the back surface of the redistribution layer 40 has a solder leg 60 electrically connected with the pad 41 on the redistribution layer 40. Among them, the solder leg 60 is a solder block or a solder ball, in the embodiment, the solder leg 60 is a tin ball.
[0042] Among them, the package 50 further has a black insulating layer 12 away from the back surface of the redistribution layer 40.
[0043] Among them, the bare dies of the utility model are thinned bare dies.
[0044] Referring to Figure 1 , in the embodiment, the number of the first bare dies 21 is 4, preferably 1-6. Of course, it is not limited to this, the number of the first bare dies can also be other values, which is set according to actual needs.
[0045] Embodiment 2:
[0046] Referring to Figure 2 In Embodiment 2, different from Embodiment 1, there is a bonding wire between each of the first dies 21 and the second die 22 to electrically connect the electrode of the first die 21 and the electrode of the second die 22. Specifically, the electrode surface of the second die 22 is provided with a first soldering pad 33 electrically connected with the electrode, and there is a bonding wire between the electrode of each of the first dies 21 and the first soldering pad 33.
[0047] Referring to Figure 3 In Embodiment 3, different from Embodiment 1, the number of the first dies 21 is 1 and the first dies 21 are stacked in 1 layer, and the chip stacked package structure has a total of 3 layers of dies.
[0048] Referring to Figure 4 In Embodiment 4, different from Embodiment 1, the number of the first dies 21 is 2 and the first dies 21 are stacked in 2 layers, and the chip stacked package structure has a total of 4 layers of dies.
[0049] Referring to Figure 5 In Embodiment 5, different from Embodiment 1, the number of the first dies 21 is 6 and the first dies 21 are stacked in 6 layers, and the chip stacked package structure has a total of 8 layers of dies.
[0050] In the present embodiment, all the dies are stacked together in a staggered manner in one direction, and in the present embodiment, the first dies 21 can also be stacked in a zigzag manner, and are not limited to be stacked in the same direction.
[0051] Different from the above embodiments, the number of the second dies 22 is also not limited to 1, and the number of the second dies 22 can be multiple. When the number of the second dies is multiple, the multiple second dies 22 can be stacked on the third die 23 in a staggered manner in turn, and the stacking direction of the multiple second dies 22 can be staggered in one direction or in opposite directions, as long as the conductive pillars protruding therefrom are staggered relative to each other and exposed outside the projection of the third die 23.
[0052] When the multiple second dies 22 are staggered in opposite directions, the first dies 21 can also be stacked in a staggered manner in opposite directions in turn, and when the bonding wires are connected, the first dies 21 with the electrodes exposed on the same side and the second dies 22 with the electrodes or the first soldering pads exposed on the same side can be electrically connected.
[0053] In the stacked dies, adjacent dies are adhered together by an insulating adhesive layer.
[0054] The above only discloses preferred embodiments of the present application, and of course cannot limit the scope of the present application, and therefore equivalent changes made within the scope of the present application still fall within the scope of the present application.
Claims
1. A chip stacking package structure with multiple connection methods, characterized in that: The package includes a bare die, a conductive column, a conductive bump, a redistribution layer and a package body. The bare die includes a third bare die arranged above the front surface of the redistribution layer, one or more second bare dies stacked on the third bare die in sequence and in relative misalignment, and one or more first bare dies stacked on the second bare dies in sequence and in relative misalignment, the electrode surfaces of the second bare dies and the third bare die facing the redistribution layer. The conductive column corresponds to the electrode of the second bare die, is supported between the electrode surface of the second bare die and a pad on the front surface of the redistribution layer, and electrically connects the electrode of the second bare die and the pad. The conductive bump corresponds to the electrode of the third bare die, is supported between the electrode surface of the third bare die and a pad on the front surface of the redistribution layer, and electrically connects the electrode of the third bare die and the pad. The second bare die and the first bare die are electrically connected by a bonding wire. The package body is arranged on the front surface of the redistribution layer and integrally covers the bare die, the conductive column and the conductive bump. The back surface of the redistribution layer has a soldering leg electrically connected to the pad on the redistribution layer.
2. The chip stack package structure of claim 1, wherein: The electrode surface of the second bare die further has a first soldering pad electrically connected to the electrode of the second bare die, and at least one bonding wire is electrically welded between the first soldering pad and the electrode of the first bare die.
3. The chip stack package structure of claim 2, wherein: When the first bare die is multiple, the bonding wire is arranged between the electrodes of adjacent first bare dies, and the bonding wire is arranged between the electrode of the bottommost first bare die and the electrode of the second bare die, or the bonding wire is arranged between the electrode of each first bare die and the electrode of the second bare die.
4. The chip stack package structure of claim 2, wherein: The second bare die is arranged on the third bare die in relative misalignment along a first direction, and the first bare die is arranged on the third bare die in sequence and in relative misalignment along the first direction, the electrode surface of the first bare die faces the redistribution layer, the electrode of the first bare die is located on one side of the first bare die in the first direction, the conductive column is located on one side of the second bare die in the first direction, the first soldering pad is located on one side of the second bare die in the first direction, and the electrode of the first bare die is not blocked by the adjacent first bare die or the second bare die, and the conductive column is not blocked by the third bare die.
5. The chip stack package structure of claim 1, wherein: The number of the first bare die is 1-6.
6. The chip stack package structure of claim 1, wherein: When the first bare die is multiple, the bonding wire is arranged between the electrodes of adjacent first bare dies, and the bonding wire is arranged between the electrode of the bottommost first bare die and the electrode of the second bare die, or the bonding wire is arranged between the electrode of each first bare die and the electrode of the second bare die.
7. The chip stack package structure of claim 1, wherein: The conductive column is arranged on the electrode of the second bare die, or is arranged on a second soldering pad on the electrode surface of the second bare die, and the second soldering pad is electrically connected to the electrode of the second bare die by a wire.
8. The chip stack package structure of claim 1, wherein: The conductive column is a metal block electroplated on the second bare die or a conductive wire welded on the second bare die, and the conductive bump is a metal block electroplated on the third bare die or a conductive wire welded on the third bare die.
9. The chip stack package structure of claim 1, wherein: The package body further has a black insulating layer away from the back surface of the redistribution layer.
10. The chip stack package structure of claim 1, wherein: The height of the conductive bump is 20μm±1μm.
11. The chip stack package structure of claim 1, wherein: When the second bare die is multiple, the height difference of the conductive pillars corresponding to the multiple second bare dies matches the thickness of the second bare die.
12. The chip stack package structure of claim 1, wherein: The second bare die is one or two.