Semiconductor device with gallium nitride through hole and corresponding semiconductor chip
By designing gallium nitride via structures with different widths and depths in gallium nitride transistor devices, the problem of incomplete polymer removal was solved, improving device reliability and metal filling effect.
Patent Information
- Application Number
- CN202520426287.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-11
- Publication Date
- 2026-01-30
- Estimated Expiration
- 2035-03-11
AI Technical Summary
In existing gallium nitride transistor devices, it is difficult to completely remove the polymer at the bottom of the hole during polymer removal, which affects the metal filling morphology and leads to low device reliability.
Design a semiconductor device with gallium nitride through-holes, including a first gallium nitride through-hole and a second gallium nitride through-hole. The width and depth of the second gallium nitride through-hole are 2-4 times and 3-5 times that of the first gallium nitride through-hole, respectively, forming a stepped structure that facilitates the removal of polymer and is filled into the through-hole by connecting metal.
It improves the reliability of gallium nitride transistor devices, and the good connection metal filling effect enhances the reliability of the devices.
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Figure CN223859664U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of semiconductor devices, especially to a semiconductor device with gallium nitride via and a corresponding semiconductor chip. BACKGROUND
[0002] In modern society, gallium nitride transistor devices have superior device performance and have broad application prospects in high-frequency and high-power fields. Gallium nitride transistor devices are provided with gallium nitride vias, but existing gallium nitride vias have a large depth. When removing the polymer, the polymer at the bottom of the hole is difficult to remove completely. Further, it will have an adverse effect on the subsequent metal filling morphology, reducing the device reliability. Therefore, the existing gallium nitride transistor device has the technical problem of low reliability.
[0003] Therefore, it is necessary to provide a semiconductor device with a gallium nitride via and a corresponding semiconductor chip to solve the above technical problems. SUMMARY
[0004] The utility model provides a semiconductor device with gallium nitride via, effectively solve the technical problem of low reliability of existing gallium nitride transistor device.
[0005] The utility model provides a semiconductor device with gallium nitride via, which comprises,
[0006] Silicon substrate;
[0007] Laminated structure, set up in the upper end of silicon substrate, with silicon substrate is connected;
[0008] Gallium nitride via structure, set up on silicon substrate and laminated structure, gallium nitride via structure along the circumference of silicon substrate and laminated structure is set up, gallium nitride via structure includes first gallium nitride via and second gallium nitride via, first gallium nitride via and second gallium nitride via are communicated, second gallium nitride via sets up in the upper end of first gallium nitride via, the width of second gallium nitride via is greater than the width of first gallium nitride via, so that the top of first gallium nitride via and the bottom of second gallium nitride via form a stepped structure;
[0009] Connecting metal, connect in first gallium nitride via and second gallium nitride via inside, and protrude from second gallium nitride via, connecting metal is used for with external wiring connection.
[0010] Further, the width of the second gallium nitride via is 2-4 times the width of the first gallium nitride via.
[0011] Further, the second gallium nitride via has a depth greater than the first gallium nitride via, and the depth of the second gallium nitride via is 3-5 times the depth of the first gallium nitride via.
[0012] Further, a spacing is provided between the bottom of the first gallium nitride via and the bottom of the silicon substrate, and the length of the spacing is greater than 1 / 2 of the thickness of the silicon substrate.
[0013] Further, the stack structure comprises,
[0014] a gallium nitride layer disposed on the upper end of the silicon substrate and connected to the silicon substrate;
[0015] an aluminum gallium nitride layer disposed on the upper end of the gallium nitride layer and connected to the gallium nitride layer;
[0016] a silicon nitride layer disposed on the upper end of the aluminum gallium nitride layer and connected to the aluminum gallium nitride layer.
[0017] Further, the stack structure further comprises,
[0018] a dielectric layer disposed on the upper end of the silicon nitride layer and connected to the silicon nitride layer;
[0019] a gate layer disposed on the upper end of the dielectric layer and connected to the dielectric layer;
[0020] a first dielectric layer disposed on the upper end of the gate layer and connected to the gate layer;
[0021] a second dielectric layer disposed on the upper end of the first dielectric layer and connected to the first dielectric layer;
[0022] a third dielectric layer disposed on the upper end of the second dielectric layer and connected to the second dielectric layer.
[0023] Further, the first gallium nitride via is formed based on etching on the silicon substrate, the gallium nitride layer, and the aluminum gallium nitride layer.
[0024] Further, the second gallium nitride via is formed based on etching on the silicon nitride layer, the dielectric layer, the gate layer, the first dielectric layer, and the second dielectric layer.
[0025] Further, the stack structure further comprises,
[0026] an ohmic metal layer connected to the interior of the aluminum gallium nitride layer, the silicon nitride layer, and the silicon nitride layer;
[0027] a gate field plate layer connected to the interior of the dielectric layer, the gate layer, and the first dielectric layer;
[0028] A first metal layer is connected to the gate layer, the first dielectric layer and the second dielectric layer, one end of the first metal layer is connected to the ohmic metal layer, and the other end of the first metal layer is connected to a second metal layer.
[0029] The second metal layer is located in the second dielectric layer and the third dielectric layer, and is connected to the first metal layer.
[0030] A semiconductor chip comprising the semiconductor device with a gallium nitride via as described above.
[0031] Compared with the prior art, the semiconductor device with a gallium nitride via has the beneficial effects that: the semiconductor device with a gallium nitride via is internally provided with a gallium nitride via structure. The gallium nitride via structure comprises a first gallium nitride via and a second gallium nitride via, the first gallium nitride via and the second gallium nitride via are communicated, and the second gallium nitride via is arranged at the upper end of the first gallium nitride via. Moreover, the width of the first gallium nitride via is greater than the width of the first gallium nitride via, so that the top of the first gallium nitride via and the bottom of the second gallium nitride via form a stepped structure. Because the width of the first gallium nitride via is greater, and the top of the first gallium nitride via and the bottom of the second gallium nitride via form a stepped structure. Furthermore, the polymer at the bottom of the gallium nitride via structure is more easily cleaned. Thus, in subsequent process steps, the connecting metal can be more easily filled into the interior of the gallium nitride via structure. The filling effect of the connecting metal is better, which is beneficial to improve the reliability of the semiconductor device. Therefore, the semiconductor device with a gallium nitride via effectively solves the technical problem of low reliability of the existing gallium nitride transistor device. BRIEF DESCRIPTION OF DRAWINGS
[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following briefly introduces the drawings needed in the embodiments, and the drawings in the following description are only corresponding drawings of some embodiments of the present application.
[0033] Figure 1 It is a plane schematic view of an embodiment of the semiconductor device with a gallium nitride via of the present application.
[0034] In the figure, 10, semiconductor device; 11, silicon substrate; 12, laminated structure; 121, gallium nitride layer; 122, aluminum gallium nitride layer; 123, silicon nitride layer; 124, dielectric layer; 125, gate layer; 126, first dielectric layer; 127, second dielectric layer; 128, third dielectric layer; 129, ohmic metal layer; 1291, gate field plate layer; 1292, first metal layer; 1293, second metal layer; 13, gallium nitride via structure; 131, first gallium nitride via; 132, second gallium nitride via; 14, connecting metal. DETAILED DESCRIPTION
[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.
[0036] The direction terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", "top" and "bottom", are only the orientation of the drawings, and the direction terms are used to illustrate and understand the present application, but not to limit the present application.
[0037] The terms "first", "second" and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying relative importance, and are not limited as the order of precedence.
[0038] In the figure, similar structures are indicated by the same reference numerals.
[0039] Please refer to Figure 1 The present application provides a semiconductor device 10 with gallium nitride via, which comprises a silicon substrate 11, a laminated structure 12, a gallium nitride via structure 13 and a connecting metal 14. The semiconductor device 10 with gallium nitride via is applied to a semiconductor chip. The laminated structure 12 is arranged at the upper end of the silicon substrate 11, and the laminated structure 12 is connected with the silicon substrate 11. The laminated structure 12 comprises a gallium nitride layer 121, an aluminum gallium nitride layer 122 and a silicon nitride layer 123. The gallium nitride layer 121 is arranged at the upper end of the silicon substrate 11, and the gallium nitride layer 121 is connected with the silicon substrate 11. The aluminum gallium nitride layer 122 is arranged at the upper end of the gallium nitride layer 121, and the aluminum gallium nitride layer 122 is connected with the gallium nitride layer 121. The silicon nitride layer 123 is arranged at the upper end of the aluminum gallium nitride layer 122, and the silicon nitride layer 123 is connected with the aluminum gallium nitride layer 122.
[0040] Please refer toFigure 1 The laminated structure 12 further comprises a dielectric layer 124, a gate layer 125, a first dielectric layer 126, and a second dielectric layer 127. The dielectric layer 124 is arranged on the upper end of the silicon nitride layer 123, and the dielectric layer 124 is connected with the silicon nitride layer 123. The gate layer 125 is arranged on the upper end of the dielectric layer 124, and the gate layer 125 is connected with the dielectric layer 124. The first dielectric layer 126 is arranged on the upper end of the gate layer 125, and the first dielectric layer 126 is connected with the gate layer 125. The second dielectric layer 127 is arranged on the upper end of the first dielectric layer 126, and the second dielectric layer 127 is connected with the first dielectric layer 126. The third dielectric layer 128 is arranged on the upper end of the second dielectric layer 127, and the third dielectric layer 128 is connected with the second dielectric layer 127.
[0041] Please refer to Figure 1 The laminated structure 12 further comprises an ohmic metal layer 129, a first metal layer 1292, and a second metal layer 1293. The ohmic metal layer 129 is connected in the aluminum gallium nitride layer 122, the silicon nitride layer 123, and the silicon nitride layer 123. The gate field plate layer 1291 is connected in the dielectric layer 124, the gate layer 125, and the first dielectric layer 126. The first metal layer 1292 is connected in the gate layer 125, the first dielectric layer 126, and the second dielectric layer 127. One end of the first metal layer 1292 is connected with the ohmic metal layer 129, and the other end of the first metal layer 1292 is connected with the second metal layer 1293. The second metal layer 1293 is located in the second dielectric layer 127 and the third dielectric layer 128, and the second metal layer 1293 is connected with the first metal layer 1292. The second metal layer 1293 is used for connecting with external wiring.
[0042] Please refer to Figure 1The gallium nitride via structure 13 is disposed on the silicon substrate 11 and the laminated structure 12, and is disposed along the circumference of the silicon substrate 11 and the laminated structure 12. The gallium nitride via structure 13 comprises a first gallium nitride via 131 and a second gallium nitride via 132, and the first gallium nitride via 131 and the second gallium nitride via 132 are communicated. The second gallium nitride via 132 is disposed at the upper end of the first gallium nitride via 131, and the width of the second gallium nitride via 132 is greater than the width of the first gallium nitride via 131, so that the top of the first gallium nitride via 131 and the bottom of the second gallium nitride via 132 form a stepped structure. In the preferred embodiment of the present embodiment, the width of the second gallium nitride via 132 can be 2-4 times the width of the first gallium nitride via 131. Because the width of the first gallium nitride via 131 is large, and the top of the first gallium nitride via 131 and the bottom of the second gallium nitride via 132 form a stepped structure. Further, the polymer at the bottom of the gallium nitride via structure 13 is easier to be cleaned. Thus, in the subsequent process step, the connection metal 14 can be more easily filled into the inside of the gallium nitride via structure 13. The filling effect of the connection metal 14 is better, which is beneficial to improve the reliability of the semiconductor device 10.
[0043] Please refer to Figure 1 The first gallium nitride via 131 is formed based on etching on the silicon substrate 11, the gallium nitride layer 121, the aluminum gallium nitride layer 122, and the second gallium nitride via 132 is formed based on etching on the silicon nitride layer 123, the dielectric layer 124, the gate layer 125, the first dielectric layer 126 and the second dielectric layer 127. The connection metal 14 is connected to the inside of the first gallium nitride via 131 and the second gallium nitride via 132, and the connection metal 14 protrudes from the second gallium nitride via 132, and the connection metal 14 is used for connecting with external wiring. The depth of the second gallium nitride via 132 is greater than the depth of the first gallium nitride via 131, and the depth of the second gallium nitride via 132 is 3-5 times the depth of the first gallium nitride via 131. Because the width of the second gallium nitride via 132 is large, and the depth is also large, it is beneficial to remove the polymer after etching is completed, and further beneficial to fill the connection metal 14 into the inside of the gallium nitride via structure 13 subsequently. The first gallium nitride via 131 and the bottom of the silicon substrate 11 are provided with a spacing, and the length of the spacing is greater than 1 / 2 of the thickness of the silicon substrate 11.
[0044] The manufacturing process of the utility model is: firstly, the user provides a silicon substrate 11, and deposits a gallium nitride layer 121 on the upper end of the silicon substrate 11. Then, the user deposits an aluminum gallium nitride layer 122 on the upper end of the gallium nitride layer 121, and deposits a silicon nitride layer 123 on the upper end of the aluminum gallium nitride layer 122. Furthermore, the user deposits a dielectric layer 124 on the upper end of the silicon oxide layer. Next, the user performs etching operation on the aluminum gallium nitride layer 122, the silicon nitride layer 123 and the dielectric layer 124 to form an ohmic via structure. Then, the user fills the ohmic metal layer 129 into the ohmic via structure. Then, the user deposits a gate layer 125 on the upper end of the dielectric layer 124. The user performs etching operation on the dielectric layer 124 and the gate layer 125 to form a gate hole, and fills the gate field plate layer 1291 into the gate hole. Next, the user deposits a first dielectric layer 126 on the upper end of the gate layer 125. Furthermore, the user performs etching operation on the gate layer 125 and the first dielectric layer 126 to form a first metal contact via. The user fills the first metal layer 1292 into the first metal contact via, and the first metal layer 1292 is connected with the ohmic metal layer 129. Then, the user deposits a second dielectric layer 127 on the upper end of the first dielectric layer 126. Furthermore, the user performs light shielding operation on part of the structure of the semiconductor device 10 through a light shield, so that the second dielectric layer 127 can be exposed and developed. Furthermore, the user performs etching operation on the second dielectric layer 127 to form a second metal contact via. Simultaneously, the user performs etching operation on the silicon nitride layer 123, the dielectric layer 124, the gate layer 125, the first dielectric layer 126 and the second dielectric layer 127 to form a second gallium nitride via 132. The user performs light shielding operation on part of the structure of the semiconductor device 10 through a light shield, so that the first gallium nitride via 131 can be exposed and developed. Further, the user performs etching operation on the silicon substrate 11, the gallium nitride layer 121 and the aluminum gallium nitride layer 122 to form the first gallium nitride via 131. Then, the user fills the second metal layer 1293 into the second metal contact via, and the second metal layer 1293 is connected with the first metal layer 1292. Meanwhile, the user fills the connecting metal 14 into the inside of the first gallium nitride via 131 and the second gallium nitride via 132, wherein the connecting metal 14 is formed simultaneously with the second metal layer 1293. After that, the user deposits a third dielectric layer 128 on the upper end of the second dielectric layer 127, so that the user completes the manufacturing of the semiconductor device 10 with the gallium nitride via.
[0045] Since the second metal contact via hole and the second gallium nitride via hole 132 are both etched in a dielectric layer, they can be etched synchronously, so that the second metal contact via hole and the second gallium nitride via hole 132 can be exposed and developed synchronously, and the user does not need to expose and develop the second metal contact via hole and the second gallium nitride via hole 132 twice, thereby effectively saving the process cost and process time. Moreover, in the process of manufacturing the semiconductor device 10 with the gallium nitride via hole, the second metal layer 1293 and the connecting metal 14 are filled with the same material metal at the same time, thereby reducing a metal etching process, saving a photomask, and effectively saving the process time. In the manufacturing process of the semiconductor device 10, the etching of the second contact via hole and the gallium nitride deep hole and the etching after the metal deposition process require a total of three photomasks. Compared with the traditional manufacturing process, the metal via hole interconnection structure and the gallium nitride deep hole metal structure are often realized separately, and five photomasks are used in the process. The manufacturing process of the semiconductor device 10 has the advantages of saving photomasks and saving costs.
[0046] The semiconductor device 10 with the gallium nitride via hole provided by the present application has the gallium nitride via hole structure 13 arranged in the interior of the semiconductor device 10. The gallium nitride via hole structure 13 comprises a first gallium nitride via hole 131 and a second gallium nitride via hole 132. The first gallium nitride via hole 131 and the second gallium nitride via hole 132 are communicated, and the second gallium nitride via hole 132 is arranged at the upper end of the first gallium nitride via hole 131. Moreover, the width of the first gallium nitride via hole 131 is greater than the width of the first gallium nitride via hole 131, so that the top of the first gallium nitride via hole 131 and the bottom of the second gallium nitride via hole 132 form a stepped structure. Because the width of the first gallium nitride via hole 131 is greater, and the top of the first gallium nitride via hole 131 and the bottom of the second gallium nitride via hole 132 form a stepped structure. Furthermore, the polymer at the bottom of the gallium nitride via hole structure 13 is easier to be cleaned. Thus, in the subsequent process step, the connecting metal 14 can be more easily filled into the interior of the gallium nitride via hole structure 13. The filling effect of the connecting metal 14 is better, which is beneficial to improve the reliability of the semiconductor device 10. Therefore, the semiconductor device 10 with the gallium nitride via hole effectively solves the technical problem of low reliability of the existing gallium nitride transistor device.
[0047] To sum up, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application, and those skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is subject to the scope defined by the claims.
Claims
1. A semiconductor device with a gallium nitride via, characterized by, It comprises, a silicon substrate; a laminated structure disposed on the upper end of the silicon substrate and connected with the silicon substrate; a gallium nitride via structure disposed on the silicon substrate and the laminated structure, the gallium nitride via structure is disposed along the circumference of the silicon substrate and the laminated structure, the gallium nitride via structure comprises a first gallium nitride via and a second gallium nitride via, the first gallium nitride via and the second gallium nitride via are communicated, the second gallium nitride via is disposed on the upper end of the first gallium nitride via, the width of the second gallium nitride via is greater than the width of the first gallium nitride via, so that the top of the first gallium nitride via and the bottom of the second gallium nitride via form a stepped structure; a connecting metal connected inside the first gallium nitride via and the second gallium nitride via and protruding from the second gallium nitride via, the connecting metal is used for connecting with external wiring.
2. The semiconductor device with a gallium nitride via of claim 1, wherein, The width of the second gallium nitride via is 2-4 times the width of the first gallium nitride via.
3. The semiconductor device with a gallium nitride via of claim 1, wherein, The depth of the second gallium nitride via is greater than the depth of the first gallium nitride via, and the depth of the second gallium nitride via is 3-5 times the depth of the first gallium nitride via.
4. The semiconductor device with a gallium nitride via of claim 1, wherein, The bottom of the first gallium nitride via and the bottom of the silicon substrate are provided with a spacing, and the length of the spacing is greater than 1 / 2 of the thickness of the silicon substrate.
5. The semiconductor device with a gallium nitride via of claim 1, wherein, The laminated structure comprises, a gallium nitride layer disposed on the upper end of the silicon substrate and connected with the silicon substrate; an aluminum gallium nitride layer disposed on the upper end of the gallium nitride layer and connected with the gallium nitride layer; a silicon nitride layer disposed on the upper end of the aluminum gallium nitride layer and connected with the aluminum gallium nitride layer.
6. The semiconductor device with a gallium nitride via of claim 5, wherein, The laminated structure further comprises, a dielectric layer disposed on the upper end of the silicon nitride layer and connected with the silicon nitride layer; a gate layer disposed on the upper end of the dielectric layer and connected with the dielectric layer; a first dielectric layer disposed on the upper end of the gate layer and connected with the gate layer; a second dielectric layer disposed on the upper end of the first dielectric layer and connected with the first dielectric layer; a third dielectric layer disposed on the upper end of the second dielectric layer and connected with the second dielectric layer.
7. The semiconductor device with a gallium nitride via of claim 5, wherein, The first gallium nitride via is formed based on etching on the silicon substrate, the gallium nitride layer, and the aluminum gallium nitride layer.
8. The semiconductor device with a gallium nitride via of claim 6, wherein, The second gallium nitride via is formed based on etching on the silicon nitride layer, the dielectric layer, the gate layer, the first dielectric layer, and the second dielectric layer.
9. The semiconductor device with a gallium nitride via of claim 6, wherein, The laminated structure further comprises, an ohmic metal layer connected inside the aluminum gallium nitride layer, the silicon nitride layer, and the silicon nitride layer; a gate field plate layer connected inside the dielectric layer, the gate layer, and the first dielectric layer; a first metal layer connected inside the gate layer, the first dielectric layer, and the second dielectric layer, one end of the first metal layer is connected with the ohmic metal layer, and the other end of the first metal layer is connected with a second metal layer; The second metal layer is located inside the second dielectric layer and the third dielectric layer and is connected with the first metal layer, and the second metal layer is used for connecting with external wiring.
10. A semiconductor chip, characterized by It comprises the semiconductor device with gallium nitride via of any one of claims 1-9.