Protection circuit, chip and electronic equipment
By using secondary logic control elements during chip testing, the problem of protection functions being covered during testing is solved, achieving effective protection of the protection circuit without changing the test coverage.
Patent Information
- Application Number
- CN202520147384.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2026-02-03
- Estimated Expiration
- 2035-01-21
AI Technical Summary
During chip testing, components used for functional protection may be overwritten by the test operation, causing the protection function to fail and affecting the security of the chip system.
The system employs a two-level logic control element, including a first logic control element and a second logic control element. By receiving protection information and test signals, it controls the protection circuit to maintain its original locked state during the test, thus preventing the protection function from being overridden.
While ensuring test coverage, the original locking state of the protection circuit remains unchanged, preventing the chip's original protection function from being overridden by the test function, thus achieving effective protection of the chip.
Smart Images
Figure CN223871053U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and more specifically, to a protection circuit, chip, and electronic device. Background Technology
[0002] During chip testing, in order to ensure test coverage, components used for functional protection (such as disabling functions of functional modules) are inserted into the test chain. In this case, when the chip is tested, the original values of the components used for functional protection may be overwritten, causing the corresponding protection functions to fail. Utility Model Content
[0003] In view of this, this application provides a protection circuit, a chip, and an electronic device, which sets up a secondary logic control element in the protection circuit so that the original locking state of the protection circuit is not changed during chip testing while ensuring test coverage, thereby avoiding the original protection function of the chip being covered by the test function, and thus achieving effective chip protection.
[0004] In a first aspect, embodiments of this application provide a protection circuit, the protection circuit comprising:
[0005] The first logic control element, including a first input terminal, a first enable terminal and a first output terminal, is configured to receive protection information and send protection information to the corresponding protection module, so that the protection module performs the corresponding operation according to the protection information;
[0006] The second logic control element is configured to output an enable signal of the first logic control element under the control of the protection information and / or test signal, so as to control the first logic control element to be in a response mode or a hold mode.
[0007] In the response mode, the first logic control element outputs protection information reflecting the input change of the first input terminal, and in the hold mode, it keeps the output protection information unchanged.
[0008] Furthermore, the second logic control element includes a second input terminal, a second enable terminal, and a second output terminal. The second enable terminal is configured to receive a test signal, and the second output terminal is connected to the first enable terminal of the first logic control element.
[0009] Furthermore, the first logic control element and the second logic control element are latches.
[0010] Furthermore, the first logic control element is a latch that is enabled by a low level, and the second logic control element is a latch that is enabled by a low level and has a reset function.
[0011] Furthermore, the protection circuit also includes:
[0012] A multiplexer includes a third input, a fourth input, a third output, and a signal selection terminal. The third input is configured to receive the protection information, the fourth input is configured to receive a predetermined selection signal, the third output is connected to the second input of the second logic control element, and the signal selection terminal is connected to the second output of the second logic control element.
[0013] The multiplexer is configured to select, controlled by the output signal of the second logic control element, the protection information input at the third input terminal or the predetermined selection signal input at the fourth input terminal and output to the second input terminal of the second logic control element.
[0014] Furthermore, the protection circuit also includes:
[0015] An inverter, connected to the second enable terminal of the second logic control element, is configured to invert the test signal and use it as the enable signal for the second logic control element.
[0016] Furthermore, the protection circuit also includes:
[0017] Storage unit for storing the protection information;
[0018] The first input terminal of the first logic control element is connected to the output terminal of the corresponding storage unit, and the first output terminal is connected to the corresponding protection module. The first logic control element is configured to receive protection information output from the storage unit and send protection information to the corresponding protection module.
[0019] Furthermore, the storage unit is a register.
[0020] Furthermore, the protection circuit also includes:
[0021] Programmable elements are configured to store protection modules that need to be protected through programming.
[0022] A decoder, connected between the programmable element and the storage unit, is configured to read the state of the programmable element, obtain protection information, and send the protection information to the storage unit.
[0023] Furthermore, the programmable element is a fuse, and the decoder is a fuse decoder.
[0024] Secondly, embodiments of this application provide a chip, the chip comprising:
[0025] The test logic circuit is configured to generate a test signal and perform test logic on the chip based on the test signal;
[0026] The protection circuit described above.
[0027] Thirdly, embodiments of this application provide an electronic device, which includes the chip described above.
[0028] The protection circuit of this application includes a first logic control element and a second logic control element. The first logic control element includes a first input terminal, a first enable terminal, and a first output terminal, and is configured to receive protection information and send protection information to a corresponding protection module, so that the protection module performs a corresponding operation according to the protection information. The second logic control element is controlled by the protection information and / or test signal to output an enable signal of the first logic control element, so as to control the output of the first logic control element to reflect the protection information of the input change of the first input terminal or to keep the output protection information unchanged. Therefore, this embodiment, by setting a two-level logic control element, ensures that the original locking state of the protection circuit is not changed during chip testing while ensuring test coverage, thus avoiding the original protection function of the chip being covered by the test function, thereby achieving effective chip protection. Attached Figure Description
[0029] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
[0030] Figure 1 and Figure 2 This is a schematic diagram of a proportional protection circuit;
[0031] Figure 3 This is a schematic diagram of the protection circuit according to an embodiment of this application;
[0032] Figure 4 This is a schematic diagram of a chip according to an embodiment of this application. Detailed Implementation
[0033] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0034] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.
[0035] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.
[0036] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".
[0037] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0038] The protection circuit of this application embodiment is mainly described in detail using the design based on the disabled function (func_disable) as an example. It should be understood that other functions that may be affected by the test process can also be protected by the protection circuit of this embodiment according to the actual situation, so as to avoid the original function being overwritten by the test operation value. They will not be described one by one here.
[0039] `func_disable` typically refers to a function in electronic devices, chips, or other circuit modules that disables certain functions or modules to protect the hardware system from further damage when specific conditions or faults are detected. However, if the protection information corresponding to this function (i.e., the information about disabling related modules) is overwritten by the value of the test operation, it may lead to further damage to the hardware system and cause failures in electronic devices or chips. Therefore, it is crucial to avoid the original protection function being overwritten by the test value while ensuring test coverage.
[0040] Figure 1 and Figure 2 This is a schematic diagram of a proportional protection circuit. (For example...) Figure 1 As shown, in this comparative example, the protection circuit includes a fuse 11, a fuse decoder 12, a disable register 13, and a protected logic module 14.
[0041] In this example, fuse 11 is a programmable hardware component whose state can be permanently changed after manufacturing using methods such as electric current or laser. In this comparative example, fuse 11 is used to store critical safety settings or configuration information. For instance, if a corresponding fault is detected, the faulty functional module can be disabled by blowing a specific fuse. That is, fuse 11 is programmed to store the functional modules that need to be disabled by blowing the corresponding fuse.
[0042] The fuse decoder 12 is used to read the status of a group of fuses 11 and convert it into usable control signals or addresses. That is, the fuse decoder 12 can be used to identify which fuses in a group of fuses 11 have been programmed, and generate corresponding control information based on this programming information to trigger the disable logic for security protection.
[0043] The disable register 13 acts as an intermediate layer, used to receive and manage control signals from the fuse decoder 12. The protection module 14, which is the actual functional module or path being protected, receives and identifies its own control signals from the disable register 13, and is controlled to comply with the corresponding control signals (i.e., disable commands) to disable the protection module 14, which may be faulty, thus protecting the safety of the entire system.
[0044] Furthermore, the chip system undergoes DFT (Design for Testability), which involves inserting various hardware logics to improve chip testability during the initial chip design phase. This logic generates test vectors to enable large-scale chip design. SCAN is a commonly used general-purpose test circuit in DFT, typically combined with scan chain technology. In normal operation mode, flip-flops in the chip system operate according to their functional connections; however, in test mode, these flip-flops are reconfigured into one or more long shift registers, i.e., a "scan chain." This allows test patterns to be loaded serially into the chip system, and circuit responses can be read in the same way. ATPG (Automatic Test Pattern Generation) is a test vector generation method that uses chip I / O and a SCAN scan chain to perform structured testing of the chip's internal logic. Scan Dump is a system-level test diagnostic method that can export the chip's register values using a SCAN scan chain.
[0045] Taking the above testing method as an example, such as Figure 2As shown, during chip system testing, in order to ensure test coverage, the disable register 13 is inserted into the test chain. This means that although the disable register 13 can be configured to set the value of the corresponding protection module 14 to 1 in functional mode, there is still a possibility that the value of the corresponding test register 21 may overwrite the value in the disable register 13 during testing. This leads to the failure of the chip system's disable function, which may further damage the chip system.
[0046] Based on this, this application provides a protection circuit, a chip, and an electronic device. The protection circuit includes a first logic control element and a second logic control element. The first logic control element includes a first input terminal, a first enable terminal, and a first output terminal, configured to receive protection information and send the protection information to a corresponding protection module, causing the protection module to perform a corresponding operation based on the protection information. The second logic control element is controlled by the protection information and / or a test signal to output an enable signal for the first logic control element, thereby controlling the output of the first logic control element to reflect the protection information reflecting changes in the input of the first input terminal or to maintain the output protection information unchanged. Thus, this embodiment, by setting a two-level logic control element, ensures that the original locked state of the protection circuit is not changed during chip testing while maintaining test coverage, preventing the original protection function of the chip from being covered by the test function, thereby achieving effective chip protection.
[0047] Figure 3 This is a schematic diagram of the protection circuit according to an embodiment of this application. It should be understood that the protection circuit of this embodiment is used to protect the chip system from being affected during testing, such as disabling operations, thereby achieving effective protection of the chip system. It should be understood that the protection circuit of this embodiment can be applied to the above-mentioned test method using the SCAN scan chain and the disabling operation protection function, and can also be applied to other test functions or test methods, as well as other protected functions. That is, this embodiment does not limit the corresponding test functions, test methods, or specific protected functions. Test methods that include registers and other storage units in the circuit module in the test, and functions that control each circuit or functional module to comply with relevant execution strategies, can all be applied to the protection circuit of this embodiment. Examples will not be provided here.
[0048] like Figure 3 As shown, the protection circuit of this embodiment includes a first logic control element L1 and a second logic control element L2. The first logic control element L1 includes a first input terminal D1, a first enable terminal G1, and a first output terminal Q1. The first logic control element L1 is configured to receive protection information and send protection information to the corresponding protection module 34, so that the protection module 34 performs corresponding operations according to the protection information.
[0049] In one alternative implementation, this embodiment can receive protection information determined by other circuit modules. Taking the protection information as a disable information for controlling a faulty protection module as an example, the first logic control element L1 can be used to receive the disable information determined by a fault detection module that has detected a module fault.
[0050] Furthermore, such as Figure 3 As shown, the protection circuit of this embodiment further includes a storage unit 33, which is used to store protection information determined by other circuit modules and send the protection information to the first logic control element L1. Optionally, the storage unit 33 can be a register. It should be understood that this embodiment does not limit the type of storage unit 33; it only needs to be able to temporarily store the protection information and transmit the temporarily stored protection information to the first logic control element L1.
[0051] Furthermore, the first input terminal D1 of the first logic control element L1 is connected to the output terminal Q0 of the corresponding memory cell 33, and the first output terminal Q1 is connected to the corresponding protection module 34. The first logic control element L1 is configured to receive protection information output from the memory cell 33 and send protection information to the corresponding protection module 34, so that the protection module 34 performs corresponding operations based on the protection information. Further, the first logic control element L1 is used to receive protection information output from the corresponding memory cell 33, the first enable terminal G1 is used to receive an enable signal, and the first output terminal Q1 is used to output the protection information to the corresponding protection module 34. For example, the protection information can be disable information used to control the protection module 34 that has failed to perform a disable operation based on the disable information, thereby preventing further damage to the chip system.
[0052] In one alternative implementation, such as Figure 3 As shown, the protection circuit of this embodiment further includes a programmable element 31 and a decoder 32. The programmable element 31 is configured to store protection modules that need to be protected through programming. For example, the programmable element 31 can store protection modules that need to be disabled through programming. The decoder 32 is connected between the programmable element 31 and the storage unit 33, and is configured to read the state of the programmable element 31, obtain protection information, and send the protection information to the storage unit 33. Further, the programmable element 31 is a fuse, and the decoder 32 is a fuse decoder.
[0053] Using the protection information as the disable information for faulty modules, with programmable element 31 as a fuse and decoder 32 as a fuse decoder, if the fault detection module detects a corresponding fault, programmable element 31 can disable the faulty functional module by burning a specific fuse. That is, programmable element 31 is programmed by burning the corresponding fuse to store the functional modules that need to be disabled. Decoder 32 can be used to identify which fuses in programmable element 31 have been programmed, and generate corresponding disable information based on this programming information to trigger the disable logic for security protection. Storage unit 33 acts as an intermediate layer, receiving and managing the disable signals from decoder 32, and transmitting them to protection module 34 through first logic control element L1. Protection module 34 receives and identifies its own disable information and is controlled to comply with the corresponding disable command to disable the potentially faulty protection module 34, thus protecting the security of the entire system.
[0054] In this embodiment, the first logic control element L1 in the protection circuit can directly receive the corresponding protection information from the circuit module that determines the protection information. Alternatively, it can receive the protection information through a storage unit and transmit it to the first logic control element L1. It can also store the protection information using programmable elements and a decoder, and then transmit it to the first logic control element L1. Furthermore, it can receive and transmit the protection information to the first logic control element L1 using a circuit structure including programmable elements, a decoder, and a storage unit. It should be understood that this embodiment does not limit how the first logic control element L1 receives the corresponding protection information; the circuit can be planned and configured according to specific system requirements, and will not be described in detail here.
[0055] Furthermore, in this embodiment, the second logic control element L2 is configured to be controlled by the protection information and / or test signal dft to output an enable signal of the first logic control element L1, thereby controlling the first logic control element L1 to be in a response mode or a hold mode. In response mode, the first logic control element L1 outputs protection information reflecting changes in the input of its first input terminal D1; in hold mode, it maintains the output protection information unchanged. Optionally, the test signal in this embodiment can be a signal that activates the scan dump function, or it can be other types of circuit test signals. This embodiment does not limit the type of test function that affects the value in the storage cell 33. That is, the protection circuit of this embodiment can avoid the influence of any test function that can affect the value in the storage cell 33 on the protection operation of the protection module 34, thus achieving effective protection of the chip system.
[0056] Furthermore, the second logic control element L2 can control the first logic control element L1 to be in hold mode based on the validity of the test signal dft, so that when the value of the output of the first logic control element L1 in the storage unit 33 may be overwritten by the value of the test register, the value of the first output terminal Q1 does not change accordingly. This avoids the storage unit from mistakenly transmitting the value of the overwritten protection information to the protection module 34, which would lead to the corresponding protection operation error, and achieves effective protection of the chip system.
[0057] Further, the second logic control element L2 in this embodiment includes a second input terminal D2, a second enable terminal G2, and a second output terminal Q2. The second enable terminal G2 is configured to receive a test signal dft, and the second output terminal Q2 is connected to the first enable terminal G1 of the first logic control element L1. Optionally, the input information of the input terminal D2 of the second logic control element L2 is determined according to the protection information.
[0058] In one optional implementation, the first logic control element L1 is a latch. The response mode of the first logic control element L1 is also the transparent mode of the latch. This embodiment uses a D-type latch as an example for detailed description, but it should be understood that this embodiment does not limit the type of latch used for the first logic control element L1; it can also use other types of latches such as SR latches and dynamic latches. In other optional implementations, the first logic control element L1 in this embodiment can also use other types of logic circuits that can realize the functions of reflecting the state of the output terminal and keeping the value of the output terminal unchanged. For example, circuit elements such as flip-flops or registers, and their variant circuit structures that play a similar role, can all be applied to this embodiment. This embodiment does not limit the specific logic circuit structure of the first logic control element L1.
[0059] Furthermore, in this embodiment, the first logic control element L1 is a latch that is enabled by a low level. It should be understood that, based on the actual needs and specific configuration of the circuit, the first logic control element L1 can also be a latch that is enabled by a high level. This embodiment does not limit how the first logic control element L1 is enabled; it can achieve the corresponding function by adding or removing circuit elements, which will not be illustrated here.
[0060] Furthermore, in this embodiment, the second logic control element L2 is a latch. This embodiment uses a D-type latch as an example for detailed description; however, it should be understood that this embodiment does not limit the type of latch used in the second logic control element L2, and it can also use other types of latches such as SR latches and dynamic latches. In other optional implementations, the second logic control element L2 in this embodiment can also use other types of logic circuits, as long as they can achieve the corresponding functions. For example, circuit elements such as flip-flops or registers, and their modified circuit structures that play similar roles, can all be applied in this embodiment. This embodiment does not limit the specific logic circuit structure of the second logic control element L2.
[0061] Furthermore, in this embodiment, the second logic control element L2 is a latch enabled by a low level. It should be understood that, based on actual circuit requirements and specific configuration, the second logic control element L2 can also be a latch enabled by a high level. This embodiment does not limit how the second logic control element L2 is enabled; its functionality can be achieved by adding or removing circuit components, which will not be illustrated here. Further optionally, the second logic control element L2 is a latch enabled by a low level with a reset function, enabling it to control the first logic control element L1 to be in response mode via a reset. In other optional implementations, the second logic control element L2 may not have a reset function, while the first logic control element L1 may have a reset function, which enables mode switching in the corresponding scenario.
[0062] In one alternative implementation, such as Figure 3 As shown, the protection circuit of this embodiment also includes a multiplexer 35. The multiplexer 35 includes a third input terminal In1, a fourth input terminal In2, a third output terminal O1, and a signal selection terminal S. The third input terminal In1 is configured to receive protection information, the fourth input terminal In2 is configured to receive a predetermined selection signal S1, the third output terminal O1 is connected to the second input terminal D2 of the second logic control element L2, and the signal selection terminal S is connected to the second output terminal Q2 of the second logic control element L2. The multiplexer 35 is configured to be controlled by the output signal of the second logic control element L2 to select either the protection information input at the third input terminal In1 or the predetermined selection signal S1 input at the fourth input terminal In2 and output it to the second input terminal D2 of the second logic control element L2.
[0063] Further, in this embodiment, the multiplexer 35 responds to a low-level output signal from the second logic control element L2 by selecting to output the protection information received at the third input terminal In1 to the second input terminal D2 of the second logic control element L2; and responds to a high-level output signal from the second logic control element L2 by selecting to output the predetermined selection signal s1 received at the fourth input terminal In2 to the second input terminal D2 of the second logic control element L2. Optionally, the predetermined selection signal s1 may be a high-level signal. It should be understood that this embodiment does not limit the control method of the multiplexer 35; it may also select to output the predetermined selection signal s1 received at the fourth input terminal In2 to the second input terminal D2 of the second logic control element L2 when the signal received at the signal selection terminal S is low, and select to output the protection information received at the third input terminal In1 to the second input terminal D2 of the second logic control element L2 when the signal received at the signal selection terminal S is high.
[0064] In one alternative implementation, such as Figure 3 As shown, the protection circuit also includes an inverter 36. The inverter 36 is connected to the second enable terminal G2 of the second logic control element L2 and is configured to invert the test signal dft and use it as the enable signal for the second logic control element L2. It should be understood that the protection circuit of this embodiment may also omit the inverter 36, achieving the same control logic by changing the type of the second logic control element L2. This embodiment does not limit this, as long as it enables the second logic control element L2 to control the output of the first logic control element L1 during the test process.
[0065] Furthermore, the following are... Figure 3 The protection circuit shown is used to specifically describe the operation of the protection circuit in this embodiment. The first logic control element L1 is a latch enabled by a low-level signal, and the second logic control element L2 is a latch enabled by a low-level signal and has a reset function. Figure 3 As shown, after the protection circuit initialization or the testing process of the storage unit 33 or other elements storing protection information is completed, the second logic control element L2 is reset by a valid reset signal sys_por_rstn. At this time, the output signal so2 of the output terminal Q2 of the second logic control element L2 is a low-level signal. At this time, the first enable terminal G1 of the first logic control element L1 receives a valid enable signal so2 and is controlled to be in response mode, that is, the first logic control element L1 is directly powered on, and transmits the protection information of the storage unit 33 to the corresponding protection module 34, so that the protection module 34 performs the corresponding operation based on the protection information, such as a disable operation, to ensure the security of the chip system.
[0066] Simultaneously, after the second logic control element L2 is reset, since the test signal dft is invalid (i.e., remains low), the test signal dft is inverted by inverter 36 to obtain the enable signal si2 of the second logic control element L2. At this time, since the test signal dft remains low and the enable signal si2 remains an invalid high-level signal, the second logic control element L2 is in hold mode, that is, it holds the output low-level output signal so2. Furthermore, since the signal selection terminal S of the multiplexer 35 is controlled by the output signal so2 of the second logic control element L2, and the output signal so2 is low at this time, the multiplexer 35 selects the protection information output by the storage unit 33 and outputs it to the input terminal D2 of the second logic control element L2. However, since the second logic control element L2 is in hold mode, its output terminal Q2 does not change with the input value of the input terminal D2. Therefore, the first logic control element L1 can always maintain the response mode during this period, that is, it can always transmit the protection information of the storage unit 33 to the corresponding protection module 34 so that the protection module 34 can perform the corresponding operation based on the protection information, such as the disable operation, to ensure the security of the chip system.
[0067] Furthermore, after the testing process of storage unit 33 or other elements storing protection information begins, that is, when the test signal dft switches to a high level (i.e., valid), the test signal dft is inverted by inverter 36 to obtain the enable signal si2 of the second logic control element L2. At this time, the enable signal si2 is a valid low-level signal, and the second logic control element L2 is controlled by the valid enable signal si2 to be in response mode, and its output terminal Q2 outputs the value from the input terminal D2. Furthermore, if the output signal so1 of storage unit 33 is high at this time, the first logic control element L1 outputs a high-level signal. The input terminal D2 of the second logic control element L2 receives this high-level signal and outputs a high-level output signal so2 through the output terminal Q2. At this time, the first enable terminal G1 of the first logic control element L1 receives the invalid enable signal so2 and is controlled to be in holding mode, that is, the first logic control element L1 is locked to maintain the output high-level signal. Meanwhile, the signal selection terminal S of the multiplexer 35 is controlled by the output signal so2 of the second logic control element L2. At this time, the output signal so2 is high, so the multiplexer 35 selects the predetermined selection signal s1 and outputs it to the input terminal D2 of the second logic control element L2. Since the second logic control element L2 is in response mode at this stage, the output signal so2 output by the output terminal Q2 of the second logic control element L2 is the predetermined selection signal s1. Since the predetermined selection signal s1 is a high-level signal, the first logic control element L1 is controlled by the high-level output signal so2 and is always in hold mode during this period. That is, it is locked and maintains the output high-level signal, which does not change with the change of the value of the storage unit 33. This avoids the situation where the protection information of the storage unit 33 is overwritten by the value of the test register during the test, and thus the error information is transmitted to the protection module 34, thereby ensuring the effective protection of the chip system.
[0068] Furthermore, after the testing process of storage unit 33 or other elements storing protection information begins, and the output signal so1 of storage unit 33 is low, the first logic control element L1 outputs a low-level signal. The input terminal D2 of the second logic control element L2 receives this low-level signal and outputs a low-level output signal so2 through the output terminal Q2. At this time, the first enable terminal G1 of the first logic control element L1 receives a valid enable signal so2 and is controlled to be in response mode, that is, the output terminal of the first logic control element L1 outputs a low-level signal from the input terminal. At the same time, the signal selection terminal S of the multiplexer 35 is controlled by the output signal so2 of the second logic control element L2. At this time, the output signal so2 is low, so the multiplexer 35 selects the output signal so1 of storage unit 33 to be output to the input terminal D2 of the second logic control element L2. Since the second logic control element L2 is in response mode at this stage, the output signal so2 output by the output terminal Q2 of the second logic control element L2 is a low-level signal. Therefore, the first logic control element L1 is controlled to be in response mode by the low-level output signal so2. Therefore, if the output signal so1 of the storage unit 33 remains at a low level, the first logic control element L1 will always be in hold mode, maintaining a low output level and not locking.
[0069] In summary, in this embodiment, when the corresponding test function is not activated, i.e., when the test signal dft is invalid, the circuit remains open, meaning the first logic control element L1 is in response mode, transmitting the value from the storage unit 33 to the protection module 34 without affecting the corresponding protection function and test coverage. After the corresponding test function is activated, the first logic control element L1 is controlled to be in hold mode, i.e., the output of the first logic control element L1 is locked. This prevents the protection information of the storage unit 33 from being overwritten by the value of the test register during testing, thus avoiding the transmission of error information to the protection module 34 and ensuring effective protection of the chip system.
[0070] It should be understood that the protection circuit of any of the above implementation methods can achieve the corresponding function. This embodiment does not provide examples of the working process of the protection circuit under each implementation method.
[0071] The protection circuit of this embodiment includes a first logic control element and a second logic control element. The first logic control element includes a first input terminal, a first enable terminal, and a first output terminal, and is configured to receive protection information and send protection information to the corresponding protection module, so that the protection module performs a corresponding operation according to the protection information. The second logic control element is controlled by the protection information and / or test signal to output an enable signal of the first logic control element, so as to control the output of the first logic control element to reflect the protection information of the input change of the first input terminal or keep the output protection information unchanged. Therefore, this embodiment, by setting a two-level logic control element, ensures that the original locking state of the protection circuit is not changed during chip testing while ensuring test coverage, thus avoiding the original protection function of the chip being covered by the test function, thereby achieving effective chip protection.
[0072] Figure 4 This is a schematic diagram of a chip according to an embodiment of this application. Another embodiment of this application also provides a chip, such as... Figure 4 As shown, the chip 4 in this embodiment includes a test logic circuit 41 and a protection circuit 42. The test logic circuit 41 is configured to generate a corresponding test vector and execute test logic on the chip 4 based on the test signal. The protection circuit 42 can be any of the protection circuit implementations described above; its specific structure and operation can be found in the above embodiments and will not be repeated here. Further, the storage unit in the protection circuit 42 is inserted into the test chain. After the corresponding test function is started, the test logic circuit 41 generates a corresponding test signal dft and sends it to the protection circuit 42. This allows the protection circuit 42 to adjust the states of the first and second logic control elements based on the test signal dft. This ensures that when the test function is not started, the protection circuit 42 remains open, transmitting the value in the storage unit to the functional module without affecting the corresponding protection function and test coverage. After the test function is started, the control protection circuit 42 is locked, preventing the protection information in the storage unit from being overwritten by the value of the test register during the test, thus preventing the transmission of error information to the protection module and ensuring effective protection of the chip system. Optionally, the test signal in this embodiment can be a signal that activates the scandump function, or it can be a circuit test signal for other test functions. This embodiment does not limit the type of test function that affects the value in the storage unit 33. That is, the protection circuit in this embodiment can avoid the influence of any test function that can affect the value in the storage unit 33 on the protection operation of the protection module 34, thereby achieving effective protection of the chip system.
[0073] Furthermore, another embodiment of this application provides an electronic device that uses the chip described in the above embodiments. The chip in this electronic device is effectively protected by the protection circuit described above while ensuring test coverage.
[0074] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A protection circuit, characterized in that, The protection circuit includes: The first logic control element, including a first input terminal, a first enable terminal and a first output terminal, is configured to receive protection information and send protection information to the corresponding protection module, so that the protection module performs the corresponding operation according to the protection information; The second logic control element is configured to output an enable signal of the first logic control element under the control of the protection information and / or test signal, so as to control the first logic control element to be in a response mode or a hold mode. In the response mode, the first logic control element outputs protection information reflecting the input change of the first input terminal, and in the hold mode, it keeps the output protection information unchanged.
2. The protection circuit according to claim 1, characterized in that, The second logic control element includes a second input terminal, a second enable terminal, and a second output terminal. The second enable terminal is configured to receive a test signal, and the second output terminal is connected to the first enable terminal of the first logic control element.
3. The protection circuit according to claim 1, characterized in that, The first logic control element and the second logic control element are latches.
4. The protection circuit according to claim 1, characterized in that, The first logic control element is a latch that is enabled by a low level, and the second logic control element is a latch that is enabled by a low level and has a reset function.
5. The protection circuit according to claim 1, characterized in that, The protection circuit also includes: A multiplexer includes a third input, a fourth input, a third output, and a signal selection terminal. The third input is configured to receive the protection information, the fourth input is configured to receive a predetermined selection signal, the third output is connected to the second input of the second logic control element, and the signal selection terminal is connected to the second output of the second logic control element. The multiplexer is configured to select, controlled by the output signal of the second logic control element, the protection information input at the third input terminal or the predetermined selection signal input at the fourth input terminal and output to the second input terminal of the second logic control element.
6. The protection circuit according to claim 2, characterized in that, The protection circuit also includes: An inverter, connected to the second enable terminal of the second logic control element, is configured to invert the test signal and use it as the enable signal for the second logic control element.
7. The protection circuit according to claim 1, characterized in that, The protection circuit also includes: Storage unit, used to store the protection information; The first input terminal of the first logic control element is connected to the output terminal of the corresponding storage unit, and the first output terminal is connected to the corresponding protection module. The first logic control element is configured to receive protection information output from the storage unit and send protection information to the corresponding protection module.
8. The protection circuit according to claim 7, characterized in that, The storage unit is a register.
9. The protection circuit according to claim 7, characterized in that, The protection circuit also includes: Programmable elements are configured to store protection modules that need to be protected through programming. A decoder, connected between the programmable element and the storage unit, is configured to read the state of the programmable element, obtain protection information, and send the protection information to the storage unit.
10. The protection circuit according to claim 9, characterized in that, The programmable element is a fuse, and the decoder is a fuse decoder.
11. A chip, characterized in that, The chip includes: The test logic circuit is configured to generate a test signal and perform test logic on the chip based on the test signal; The protection circuit as described in any one of claims 1-10.
12. An electronic device, characterized in that, The electronic device includes the chip as described in claim 11.