Vertical cavity surface emitting laser chip, laser radar system and light source thereof

Abstract

The utility model discloses a vertical cavity surface emitting laser chip, a laser radar system and a light source thereof, and the chip comprises a substrate which is provided with a light-emitting region; the light-emitting array is formed on the substrate; the covering layer is formed on the light-emitting array; the light-emitting array comprises a plurality of light-emitting units, each light-emitting unit comprises a first reflector layer, an active layer, a photoelectric limiting layer and a second reflector layer which are sequentially stacked from the substrate, and the photoelectric limiting layer is provided with a photoelectric limiting hole used for limiting the light-emitting range of the light-emitting units; the light-emitting area comprises a central area and a surrounding peripheral area, and the aperture of the photoelectric limiting hole located in the peripheral area is smaller than that of the photoelectric limiting hole located in the central area. In each light-emitting unit, the aperture of the photoelectric limiting hole in the central area is larger, so that the equivalent resistance of the light-emitting unit in the central area is smaller, the injection current of the light-emitting unit in the peripheral area is further reduced, the peripheral light-emitting unit is prevented from generating a high-order mode, and the purpose of reducing the far-field emission angle is achieved.

Description

Technical Field

[0001] This utility model relates to the field of laser technology, specifically to a vertical cavity surface-emitting laser chip, a lidar system and its light source. Background Technology

[0002] In the design of Vertical-Cavity Surface-Emitting Laser (VCSEL) chips, in pursuit of a small divergence angle, both the epitaxial layer and the chip design often sacrifice power to reduce the far-field divergence angle. Conversely, to compensate for the power loss, the number of apertures on the chip must be increased. However, increasing the number of apertures leads to increased chip size, increased heat generation, and uneven injection current, which objectively increases the power loss per aperture. Furthermore, the uneven current injection, particularly the apertures on the outer edge of the chip which receive a larger injection current, causes higher-order modes to be generated earlier than those with lower injection currents. These higher-order modes increase the overall far-field divergence angle of the chip. Therefore, how to reduce the far-field divergence angle without affecting optical power is a pressing problem that needs to be solved. Utility Model Content

[0003] The main technical problem solved by this invention is the large far-field divergence angle of vertical cavity surface-emitting laser chips in related technologies.

[0004] To address the aforementioned technical problems, this application provides a vertical-cavity surface-emitting laser chip, comprising:

[0005] Substrate, having a light-emitting region;

[0006] A light-emitting array is formed on the substrate; and

[0007] A cover layer is formed on the light-emitting array;

[0008] The light-emitting array includes multiple light-emitting units arranged in an array within the light-emitting region. Each light-emitting unit includes a first reflective mirror layer, an active layer, a photoelectric confinement layer, and a second reflective mirror layer, which are sequentially stacked from the substrate. The photoelectric confinement layer is provided with a photoelectric confinement hole, which is used to limit the light-emitting range of the light-emitting unit.

[0009] The light-emitting area includes a central area and a surrounding peripheral area, and at least one of the photoelectric limiting holes located in the peripheral area has a smaller aperture than the photoelectric limiting hole located in the central area.

[0010] In one embodiment, the aperture of the photoelectric limiting hole gradually decreases in the direction from the central region to the peripheral region.

[0011] In one embodiment, the spacing between two adjacent photoelectric limiting holes in the central region is smaller than the spacing between two adjacent photoelectric limiting holes in the peripheral region.

[0012] In one embodiment, the spacing between adjacent photoelectric limiting holes gradually increases in the direction from the central region to the peripheral region.

[0013] In one embodiment, the first reflective mirror layer of the plurality of light-emitting units is an integral structure.

[0014] In one embodiment, the cover layer includes a contact layer, an insulating layer, and a conductive layer stacked sequentially. The contact layer is formed on the second reflector layer, the insulating layer has a through-hole, and the conductive layer is electrically connected to the contact layer through the through-hole.

[0015] In one embodiment, the light-emitting units in the light-emitting array are arranged in a ring array, a rectangular array, or a radial array.

[0016] In one embodiment, the cover layer has an electrode region and a photoelectric aperture region arranged side by side. The electrode region is provided with an electrical connector for electrical connection with an external power supply. The aperture of the photoelectric limiting aperture near the electrode region is smaller than the aperture of the photoelectric limiting aperture away from the electrode region.

[0017] Based on the same inventive concept, this application also provides a laser source, including a power supply unit and at least one of the above-described vertical cavity surface-emitting laser chips, wherein the power supply unit is electrically connected to the vertical cavity surface-emitting laser chip.

[0018] Based on the same inventive concept, this application also provides a lidar system, including a transmitting component and a receiving component, wherein the transmitting component uses the laser light source described above.

[0019] According to the vertical cavity surface emission laser chip, lidar system and light source of the above embodiments, since the aperture of the photoelectric confinement hole in the central region of each light-emitting unit in the array is larger, the equivalent resistance of the light-emitting unit in the central region is smaller. Therefore, it reduces the injection current of the light-emitting unit in the peripheral region, thereby suppressing the generation of higher-order modes by the peripheral light-emitting unit, thereby achieving the purpose of reducing the far-field emission angle. Attached Figure Description

[0020] Figure 1 This is a top view of the vertical cavity surface-emitting laser chip in an embodiment of this application.

[0021] Figure 2 This is a schematic diagram of the stacked structure of a vertical cavity surface-emitting laser chip in an embodiment of this application.

[0022] Figure 3 This is a schematic diagram of a photoelectric limiting hole setting method in an embodiment of this application.

[0023] Figure 4 This is a schematic diagram of another photoelectric limiting hole setting method in the embodiments of this application.

[0024] Figure 5 This is a schematic diagram of another photoelectric limiting hole setting method in the embodiments of this application.

[0025] Figure 6 This is a schematic diagram of another photoelectric limiting hole setting method in the embodiments of this application.

[0026] Explanation of reference numerals in the attached figures:

[0027] 1-Substrate; 11-Central region; 12-Peripheral region;

[0028] 2-Light-emitting array; 20-Light-emitting unit; 21-First reflector layer; 22-Active layer; 23-Photoelectric confinement layer; 24-Second reflector layer; 25-Photoelectric confinement hole;

[0029] 3-Covering layer; 31-Contact layer; 32-Insulating layer; 33-Conductive layer; 35-Porcelain aperture area; 36-Electrode area. Detailed Implementation

[0030] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Similar elements in different embodiments are referred to by related similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0031] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0032] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0033] In related technologies, vertical-cavity surface-emitting laser (VCSEL) chips, with their advantages such as beam emission perpendicular to the substrate, good beam symmetry, low power consumption, ease of single-mode operation, and two-dimensional array integration, have been widely used in optical communication, optical storage, optical interconnects, solid-state lighting, laser printing, and biosensing, attracting considerable interest and close attention. To balance divergence angle and emission power, VCSEL chips typically employ an array of multi-aperture light-emitting units to achieve light emission. During chip operation, the current injected into the chip is relatively stable, and the structure of each light-emitting unit can be considered as a resistor, with each unit connected in parallel to the chip. Theoretically, if the fabrication process of each aperture is completely identical, the current injected into the chip should be evenly distributed among the light-emitting units. However, in practice, due to the arrangement of the apertures and the distance between each aperture and the power supply, the current is not uniform. The closer to the periphery of the chip, the greater the injected current, while the central region, farther from the periphery, has a relatively lower injected current. As a result, light-emitting units with larger injection currents will generate higher-order modes earlier than other light-emitting units with smaller injection currents, thus increasing the divergence angle of the entire device due to the higher-order modes in the peripheral region.

[0034] To reduce the higher-order modes of a vertical-cavity surface-emitting laser (VCSEL) chip, and thus reduce the far-field divergence angle of the entire VCSEL chip, this application provides a VCSEL chip. Please refer to [link / reference]. Figure 1 and Figure 2 The vertical-cavity surface-emitting laser chip includes:

[0035] A substrate 1 has a light-emitting region; a light-emitting array 2 is formed on the substrate 1; and a cover layer 3 is formed on the light-emitting array 2; wherein, the light-emitting array 2 includes a plurality of light-emitting units 20 arranged in an array within the light-emitting region, and the light-emitting unit 20 includes a first reflective mirror layer 21, an active layer 22, a photoelectric confinement layer 23 and a second reflective mirror layer 24 stacked sequentially from the substrate 1, and the photoelectric confinement layer 23 is provided with a photoelectric confinement hole 25, which is used to limit the light-emitting range of the light-emitting unit;

[0036] The light-emitting area includes a central area 11 and a surrounding peripheral area 12, and the aperture of the photoelectric confinement hole 25 located in the peripheral area 12 is smaller than the aperture of the photoelectric confinement hole 25 located in the central area 11.

[0037] The vertical cavity surface-emitting laser chip in this embodiment has a stacked structure, including a substrate 1, a light-emitting array 2, and a capping layer 3 arranged sequentially. The substrate 1 includes, but is not limited to, a ceramic substrate such as silicon nitride, with other components formed sequentially on the substrate 1. Additionally, the substrate 1 may be provided with conductive electrodes to serve as one of the electrodes of the light-emitting unit 20 in the light-emitting array 2, providing power to the light-emitting unit 20.

[0038] The substrate 1 itself has a certain area; a light-emitting region is formed on the surface of the substrate 1, which represents the area where the light-emitting array 2 is disposed on the substrate 1. Other areas of the substrate 1 besides the light-emitting region can also be used to house other devices besides the light-emitting unit 20, and are not limited in this embodiment. Therefore, the location of the light-emitting region on the substrate 1 is not limited to the center of the substrate 1. In fact, the light-emitting region can occupy any position and any range on the surface of the substrate 1.

[0039] The light-emitting array 2 is formed on the substrate 1 and disposed in the light-emitting region. The light-emitting array 2 is a structure formed by an array arrangement of multiple light-emitting units 20. Each light-emitting unit 20 is disposed in the light-emitting region with a central region 11 and a peripheral region 12 surrounding the central region 11. Some of the light-emitting units 20 are disposed in the central region 11, and some are disposed in the peripheral region 12 surrounding the central region 11. Therefore, in order to achieve the effect of the peripheral region 12 surrounding the central region 11, the peripheral region 12 has at least three light-emitting units 20, and the central region 11 has at least one light-emitting unit 20, thereby forming a surrounding effect. It is worth mentioning that, in this embodiment, the central region 11 and the peripheral region 12 encompassed by the light-emitting area are actually determined according to the arrangement of each light-emitting unit 20 in the light-emitting array 2. That is, the light-emitting units 20 arranged in the array are located at the center and the periphery, respectively. The periphery refers to the outermost part of the entire light-emitting array 2. According to the number and arrangement of the light-emitting units 20, the central region 11 and the peripheral region 12 can be configured to corresponding sizes. The central region 11 and the peripheral region 12 can be derived from the division of the entire light-emitting area, that is, the entire light-emitting area only includes the central region 11 and the peripheral region 12; or, a transition area can also be included between the central region 11 and the peripheral region 12. In short, the central region 11 and the peripheral region 12 in this embodiment are only applicable to distinguishing the setting position of the light-emitting units 20 in the light-emitting area.

[0040] The light-emitting unit 20 comprises at least an encapsulation structure consisting of a first reflective mirror layer 21, an active layer 22, a photoelectric confinement layer 23, and a second reflective mirror layer 24 stacked sequentially. In this encapsulation structure, the first reflective mirror layer 21 is typically an N-type doped lower DBR (distributed Bragg reflector) layer, the active layer 22 is a multi-quantum-well active layer, and the second reflective mirror layer 24 is a P-type doped upper DBR layer. The active layer 22 of the light-emitting unit 20 is sandwiched between the two DBR layers, forming a resonant cavity. Optical feedback is provided by the two DBR layers. Typically, the reflectivity of the lower DBR layer is close to 100%, while the reflectivity of the upper DBR layer is relatively low. During operation, current is injected through the photoelectric confinement layer 23 above the active layer 22, resulting in stimulated emission in the active layer 22 to achieve laser output. The laser output direction is perpendicular to the surface of the active layer 22, passes through the photoelectric confinement hole 25 and the photoelectric confinement layer 23, and exits from the low-reflectivity upper DBR layer.

[0041] A Discrete Reflector (DBR) is typically a film system composed of two materials with different refractive indices, each with an optical thickness of 1 / 4 wavelength, stacked alternately. When the optical path difference between two DBR layers is an integer multiple of the wavelength, the light undergoes in-phase interference enhancement in the resonant cavity, oscillating continuously within the cavity. Eventually, the gain exceeds the loss, resulting in laser output. The reflectivity of a DBR is determined by the refractive index of the film layers and the number of layers. The greater the refractive index difference between the two materials and the more layers, the higher the reflectivity of the system. The reflection bandwidth is primarily determined by the refractive index difference.

[0042] For semiconductor devices, to inject electrons into the active layer 22, it is typically placed within a PN junction. Electrons are injected into the active layer 22 through the N-layer, while holes are injected through the P-layer. To achieve high lasing efficiency, the active layer 22 is generally undoped. However, background impurities exist during the growth of semiconductor chips, meaning the active layer 22 is not an ideal intrinsic semiconductor. Injected carriers combine with impurities, reducing carrier lifetime and thus lowering the lasing efficiency of the laser. However, this also increases the modulation rate. Therefore, sometimes the active layer 22 is intentionally doped to improve the modulation rate while maintaining performance.

[0043] Furthermore, the effective cavity length of a vertical-cavity surface-emitting laser (VCSEL) chip is the thickness of the active layer 22 plus the penetration depth of the dual-mode receivers (DBRs) on both sides. The active layer 22 is relatively thin, typically resulting in a total cavity length of a few micrometers, while EELs, which use edge emission, generally have cavity lengths of several hundred micrometers. Therefore, VCSELs have shorter cavity lengths, larger spacing between longitudinal modes, and better single-mode characteristics. Additionally, the volume of the active layer 22 in a VCSEL chip is smaller (typically 0.07 cubic micrometers), leading to a lower threshold current. However, reducing the volume of the active layer 22 shrinks the resonant cavity, increasing losses and requiring a higher electron density for oscillation. This necessitates increasing the reflectivity of the resonant cavity, thus requiring VCSELs to fabricate DBRs with very high reflectivity.

[0044] The photoelectric confinement layer 23 is used to confine the lateral light field of the light-emitting unit, thereby reducing the divergence angle of the emitted beam. Depending on the implementation method, the photoelectric confinement layer can specifically include air column type, ion implantation type, buried heterojunction type, oxide confinement type, etc.; among which:

[0045] An air-column type optoelectronic confinement layer is formed by dry etching to create an air column of a specific diameter, utilizing the difference in refractive index between the material and the air interface to form optical confinement. This fabrication process is relatively simple, but the optical loss of the agent under this structure is relatively large, and the active layer is exposed to the air, which may affect the performance and lifespan of the vertical cavity surface-emitting laser chip.

[0046] Ion-implanted optoelectronic confinement layers create a high-resistivity region by injecting ions (mostly protons) above the active layer, thereby forming electrical confinement. These vertical-cavity surface-emitting laser (VCSEL) chips are generally very small in size because they do not confine light, making their fabrication process quite challenging. Furthermore, the energy of the implanted ions must be carefully controlled; low energy will not provide effective electrical confinement, while excessively high energy will allow ions to enter the active layer, severely impacting device performance.

[0047] The buried heterojunction type photoelectric confinement layer can be seen as a variant of the air column type photoelectric confinement layer. It is formed by etching the reflector layer to form an air column, and then forming a buried heterojunction structure through secondary epitaxy. Photoelectric confinement is formed by selecting a suitable secondary epitaxial material.

[0048] The oxidation-confined photoelectric confinement layer is a compound layer immediately above the active layer 22. This compound layer undergoes oxidation to form a ring of non-conductive oxides. For example, the high-Al composition layer in a vertical-cavity surface-emitting laser (VCSEL) chip is oxidized to Al2O3 in a high-temperature wet oxidation process. This processing technology (side-oxidation process) is a challenging process in VCSEL chip fabrication. By controlling the oxidation depth from the outside in, the aperture size of the unoxidized portion can be controlled. When a voltage is applied to the two electrodes, the aperture size of this photoelectric confinement aperture 25 affects the longitudinal current passing through the active layer 22, thereby controlling the power characteristics of the VCSEL chip. The larger the aperture of the photoelectric confinement aperture 25, the larger the current passing through the active layer 22, and the greater the output power. Correspondingly, an increase in the aperture of the photoelectric confinement aperture 25 is also accompanied by an increase in the divergence angle of the emitted beam. According to the arrangement of the light-emitting units 20 in the embodiments of this application, the aperture of the photoelectric limiting hole 25 of the light-emitting unit 20 located in the central region 11 is larger than that of the photoelectric limiting hole 25 of the light-emitting unit 20 located in the peripheral region 12. Therefore, the light-emitting unit 20 located in the central region 11 can inject a larger current than the light-emitting unit 20 located in the peripheral region 12, which can suppress the generation of higher-order modes in the light-emitting unit 20 located in the peripheral region 12, thereby reducing the far-field divergence angle of the vertical cavity surface-emitting laser chip.

[0049] A cover layer 3 is disposed over the light-emitting array 2, and its purpose is to provide the electrodes required for powering the light-emitting unit 20. Specifically, the cover layer 3 comprises a contact layer 31, an insulating layer 32, and a conductive layer 33. The contact layer 31 is formed on the second reflective mirror layer 24, the insulating layer 32 has a through-hole, and the conductive layer 33 is electrically connected to the contact layer 31 through the through-hole. The contact layer 31 is configured to form an ohmic contact with the second reflective mirror layer 24, and the conductive layer 33 serves as another electrode of the light-emitting unit 20, providing power to the light-emitting unit 20 together with the electrodes disposed on the substrate 1.

[0050] In some optional embodiments, to make the light emission of the vertical-cavity surface-emitting laser chip more uniform, that is, to ensure high consistency of the light emission from each light-emitting unit 20 disposed on the central region 11 and the peripheral region 12 after merging, the aperture of the photoelectric confinement hole 25 can be configured such that the aperture of the photoelectric confinement hole 25 gradually decreases in the direction from the central region 11 to the peripheral region 12. In other words, depending on the placement position of the light-emitting chip on the light-emitting region, the farther away from the central region 11, the smaller the aperture of the corresponding photoelectric confinement hole 25 becomes, and the aperture of the photoelectric confinement hole 25 is gradually decreasing in the direction away from the central region 11. With this structure, the light emission effect of adjacent light-emitting units 20 of the vertical-cavity surface-emitting laser chip is similar, and the final effect of the superimposed light emission from each light-emitting unit 20 is highly uniform and consistent.

[0051] In some optional embodiments, to facilitate light emission, a light-emitting region can be formed on the cover layer 3 corresponding to the photoelectric confinement hole 25. The light-emitting region can be formed by means of light-transmitting material, etching, or other methods, which allows the light emitted through the photoelectric confinement hole to be emitted outward without obstruction. In addition, to further reduce the far-field divergence angle, the actual light-emitting range of the light-emitting region can be set to be smaller than the aperture of the photoelectric confinement hole 25. This setting can further reduce the divergence angle of the light projected outward through the photoelectric confinement hole 25.

[0052] In this embodiment, besides setting the photoelectric limiting aperture 25 of the light-emitting unit 20 in the central region 11 to be larger to prevent the light-emitting unit 20 in the peripheral region 12 from generating higher-order modes, in some optional embodiments, the equivalent resistance of each light-emitting unit 20 within a certain range can be adjusted by adjusting the spacing between the photoelectric limiting apertures 25. The spacing between two adjacent photoelectric limiting apertures 25 in the central region 11 is configured to be smaller than the spacing between two adjacent photoelectric limiting apertures 25 in the peripheral region 12. Therefore, the photoelectric limiting apertures 25 in the central region are closer to the photoelectric limiting apertures 25 in the peripheral region 12. Under this structure, the equivalent resistance of the light-emitting unit 20 in the central region 11 is lower, resulting in a larger injected current. This suppresses the generation of higher-order modes in the light-emitting unit 20 in the peripheral region 12, thereby reducing the far-field divergence angle of the vertical cavity surface-emitting laser chip.

[0053] In some optional embodiments, to improve the light emission uniformity of the entire vertical cavity surface-emitting laser chip, the spacing between adjacent photoelectric confinement holes 25 gradually increases in the direction from the central region 11 to the peripheral region 12. In other words, the spacing between adjacent photoelectric confinement holes 25 in this embodiment gradually increases in the direction away from the central region 11, so the light emission effect of adjacent light-emitting units 20 is similar, and the light emission uniformity after the light emission of each light-emitting unit 20 is superimposed is also better.

[0054] In some optional embodiments, to simplify the manufacturing process and ensure that each light-emitting unit 20 has the same or similar electrical performance, the first reflective mirror layer 21 of multiple light-emitting units 20 can be an integral structure. In other words, each light-emitting unit 20 in the embodiments of this application can be integrally formed on the same substrate 1, with each light-emitting unit 20 having the same first reflective mirror layer 21. Other layer structures, including the active layer 22, photoelectric confinement layer 23, and second reflective mirror layer 24, can also be the same. Then, in subsequent further manufacturing processes, adjacent light-emitting units 20 are separated according to the light-emitting unit. Other layer structures, except for the first reflective mirror layer 21, are removed by etching processes, etc., to obtain relatively independent light-emitting units 20.

[0055] In some alternative embodiments, please refer to Figures 3 to 5 As shown, the light-emitting units 20 in the light-emitting array 2 are arranged in an array. The specific arrangement of the light-emitting array 2 includes, but is not limited to, a circular arrangement, a rectangular array arrangement, or a radial array arrangement. The specific arrangement can be set according to the actual light output requirements. The arrangement mainly affects the shape of the light spot, and is not specifically limited in this embodiment.

[0056] In some optional embodiments, in addition to adjusting the aperture of the photoelectric confinement hole 25 in the light-emitting array 2 according to the division of the central region 11 and the peripheral region 12 to reduce the far-field divergence angle of the vertical cavity surface-emitting laser chip, the aperture of the corresponding photoelectric confinement hole 25 can also be adjusted according to the position of the electrode set on the cover layer 3. Specifically, for the light-emitting unit 20 on the chip, the closer it is to the electrode, the larger the injected current. Therefore, the current injected by the light-emitting unit 20 near the electrode can be reduced by relatively increasing the resistance of the light-emitting unit 20 near the electrode. In this embodiment, the cover layer 3 may have an electrode region 36 and a light aperture region 35 arranged in parallel. The electrode region 36 is provided with an electrical connector for electrical connection with an external power supply. The photoelectric confinement hole 25 is located in the light aperture region 35. The aperture of the photoelectric confinement hole 25 near the electrode region 36 is smaller than the aperture of the photoelectric confinement hole 25 far from the electrode region 36. In this structure, electrode region 36 and aperture region 35 are arranged side-by-side on the cover layer 3, thus separating them relatively. The aperture region 35 corresponds to the light-emitting region on the substrate 1, meaning the aperture region 35 is directly opposite the light-emitting region. In this structure, the aperture region 35 has a photoelectric confinement hole 25, which is also located within the aperture region 35. The relationship between the photoelectric confinement hole 25 and the electrode region 36 is such that the aperture diameter of the photoelectric confinement hole 25 closer to the electrode region 36 is smaller than that of the photoelectric confinement hole 25 farther from the electrode region 36. This structure allows for a relatively increased resistance to the light-emitting unit 20 closer to the electrode region 36, thereby reducing the injection current of the light-emitting unit 20, suppressing the generation of higher-order modes by the light-emitting unit 20, and thus reducing the far-end divergence angle of the chip. Figure 6 As shown.

[0057] This application provides a vertical cavity surface emission laser chip. Since the aperture of the photoelectric confinement hole 25 located in the central region 11 is larger among the light-emitting units 20 in the array, the equivalent resistance of the light-emitting unit 20 in the central region 11 is smaller. Therefore, it reduces the injection current of the light-emitting unit 20 in the peripheral region 12, thereby suppressing the generation of higher-order modes in the peripheral light-emitting units, and thus achieving the purpose of reducing the far-field emission angle.

[0058] This application also provides a laser source for a lidar system, which includes a power supply unit and at least one vertical cavity surface-emitting laser chip as described in this application, with the power supply unit electrically connected to the vertical cavity surface-emitting laser chip.

[0059] In addition, this application also provides a lidar system, which includes a transmitting component and a receiving component, wherein the transmitting component uses the laser light source described in this application.

[0060] The above-described specific examples are for illustrative purposes only and are not intended to limit the scope of this invention. Those skilled in the art to which this invention pertains can make various simple deductions, modifications, or substitutions based on the concept of this invention.

Claims

1. A vertical-cavity surface-emitting laser chip, characterized in that, include: Substrate, having a light-emitting region; A light-emitting array is formed on the substrate; as well as A cover layer is formed on the light-emitting array; The light-emitting array includes multiple light-emitting units arranged in an array within the light-emitting region. Each light-emitting unit includes a first reflective mirror layer, an active layer, a photoelectric confinement layer, and a second reflective mirror layer, which are sequentially stacked from the substrate. The photoelectric confinement layer is provided with a photoelectric confinement hole, which is used to limit the light-emitting range of the light-emitting unit. The light-emitting area includes a central area and a surrounding peripheral area, and at least one of the photoelectric limiting holes located in the peripheral area has a smaller aperture than the photoelectric limiting hole located in the central area.

2. The vertical-cavity surface-emitting laser chip as described in claim 1, characterized in that, The aperture of the photoelectric confinement hole gradually decreases in the direction from the central region to the peripheral region.

3. The vertical-cavity surface-emitting laser chip as described in claim 1 or 2, characterized in that, The distance between two adjacent photoelectric limiting holes in the central region is smaller than the distance between two adjacent photoelectric limiting holes in the outer region.

4. The vertical-cavity surface-emitting laser chip as described in claim 3, characterized in that, In the direction from the central region to the peripheral region, the spacing between adjacent photoelectric limiting holes gradually increases.

5. The vertical-cavity surface-emitting laser chip as described in claim 1 or 2, characterized in that, The first reflective mirror layer of the plurality of light-emitting units is an integral structure.

6. The vertical-cavity surface-emitting laser chip as described in claim 1 or 2, characterized in that, The cover layer includes a contact layer, an insulating layer, and a conductive layer stacked sequentially. The contact layer is formed on the second reflector layer. The insulating layer has a through-hole. The conductive layer is electrically connected to the contact layer through the through-hole.

7. The vertical-cavity surface-emitting laser chip as described in claim 1 or 2, characterized in that, The light-emitting units in the light-emitting array are arranged in a ring array, a rectangular array, or a radial array.

8. The vertical-cavity surface-emitting laser chip as described in claim 1 or 2, characterized in that, The cover layer has an electrode area and a photoelectric aperture area arranged side by side. The electrode area is provided with an electrical connector for electrical connection with an external power supply. The aperture of the photoelectric limiting aperture near the electrode area is smaller than the aperture of the photoelectric limiting aperture away from the electrode area.

9. A laser light source, characterized in that, It includes a power supply unit and at least one vertical cavity surface-emitting laser chip as described in any one of claims 1-8, wherein the power supply unit is electrically connected to the vertical cavity surface-emitting laser chip.

10. A lidar system, characterized in that, It includes a transmitting component and a receiving component, wherein the transmitting component employs the laser light source as described in claim 9.

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