Transverse MOS device
By adding a moderately doped N-type vertical stripe and P-type left and right well regions to the lateral MOS device, the problem of large reverse recovery current in lateral power LDMOS devices is solved, and losses are reduced.
Patent Information
- Application Number
- CN202520259701.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-19
- Publication Date
- 2026-02-03
- Estimated Expiration
- 2035-02-19
AI Technical Summary
Existing lateral power LDMOS devices have a large reverse recovery current, resulting in high losses.
In lateral MOS devices, a lightly doped N-type drift region is added between the moderately doped N-type vertical stripe and the P-type left and right well regions to ensure that the moderately doped N-type vertical stripe and the lower end face of the P-type left and right well regions are on the same plane, and its width is adjusted to 4-8 times that between the P-type left and right well regions. An aluminum or copper metal layer is used, and the width of the gate oxide layer is greater than the width of the gate electrode.
This effectively reduces the reverse recovery current and avoids a drop in breakdown voltage, thereby reducing the overall device loss.
Smart Images
Figure CN223872667U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of MOS device technology, and in particular to a lateral MOS device. Background Technology
[0002] Lateral power LDMOS devices, or lateral double-diffused metal-oxide-semiconductor devices, are widely used in power integration. Lateral high-voltage MOS devices offer high voltage withstand capability and are easy to integrate, making them commonly used in high-voltage and power integrated circuits. However, lateral MOS devices currently exhibit relatively large reverse recovery currents, which hinders further loss reduction. Summary of the Invention
[0003] The purpose of this invention is to provide a lateral MOS device that avoids reducing the breakdown voltage while reducing the reverse recovery current, thereby reducing the overall loss of the device.
[0004] To achieve the above objectives, the technical solution adopted by this utility model is: a lateral MOS device, comprising: an N-type drain region and a lightly doped N-type drift region stacked within a silicon wafer, a P-type left well region and a P-type right well region respectively located on the left and right sides of the upper part of the lightly doped N-type drift region, and a first source region and a second source region respectively located on the upper part of each of the P-type left well region and the P-type right well region;
[0005] A gate electrode is disposed directly above the region between the lightly doped N-type drift region and the P-type left well region. The left end of the gate electrode extends above the region between the first source region and the lightly doped N-type drift region, and the right end of the gate electrode extends above the region between the second source region and the lightly doped N-type drift region. A gate oxide layer is present between the gate electrode and the lightly doped N-type drift region.
[0006] The lightly doped N-type drift region has a medium-doped N-type vertical stripe vertically disposed at the center between the P-type left well region and the P-type right well region. The medium-doped N-type vertical stripe is equidistant from the P-type left well region and the P-type right well region in the horizontal direction. A first upper metal layer is located on the upper surface of the first source region and the second source region, a second upper metal layer is located on the upper surface of the gate electrode, and a lower metal layer is located on the lower surface of the N-type drain region.
[0007] The following are further improvements to the above technical solution:
[0008] 1. In the above scheme, the lower end face of the doped N-type vertical stripe is located on the same plane as the lower end faces of the P-type left well region and the P-type right well region.
[0009] 2. In the above scheme, the width between the P-type left well region and the P-type right well region is 4 to 8 times the width of the medium-doped N-type vertical stripe.
[0010] 3. In the above scheme, the gate oxide layer is a silicon dioxide layer.
[0011] 4. In the above scheme, the upper metal layer and the lower metal layer are aluminum metal layers or copper metal layers.
[0012] 5. In the above scheme, the width of the gate oxide layer is greater than the width of the gate electrode.
[0013] Due to the application of the above technical solution, this utility model has the following advantages compared with the prior art:
[0014] This utility model relates to a lateral MOS device, which has a P-type left well region and a P-type right well region on the left and right sides of the upper part of the lightly doped N-type drift region. The lightly doped N-type drift region has a medium-doped N-type vertical stripe in the region between the P-type left well region and the P-type right well region. The width of the medium-doped N-type vertical stripe is equal to that of the lightly doped N-type drift region between the P-type left well region and the P-type right well region. The addition of the medium-doped N-type vertical stripe at the center of the current path avoids reducing the breakdown voltage and reduces the reverse recovery current, thereby reducing the overall loss of the device. Attached Figure Description
[0015] Appendix Figure 1 This is a schematic diagram of the structure of the lateral MOS device of this utility model.
[0016] In the above figures: 1. Silicon wafer; 2. N-type drain region; 3. Lightly doped N-type drift region; 41. P-type left well region; 42. P-type right well region; 51. First source region; 52. Second source region; 6. Gate electrode; 7. Gate oxide layer; 8. Medium-doped N-type vertical stripe; 91. First upper metal layer; 92. Second upper metal layer; 10. Lower metal layer; 11. Insulating dielectric layer. Detailed Implementation
[0017] The present patent can be further understood through the specific embodiments given below, but they are not intended to limit the present patent.
[0018] Example 1: A lateral MOS device, as shown in the figure, includes: an N-type drain region 2 and a lightly doped N-type drift region 3 stacked within a silicon wafer 1, with a P-type left well region 41 and a P-type right well region 42 on the left and right sides of the upper part of the lightly doped N-type drift region 3, respectively; and a first source region 51 and a second source region 52 on the upper part of each of the P-type left well region 41 and the P-type right well region 42, respectively.
[0019] A gate electrode 6 is disposed directly above the region between the P-type left well region 41 and the P-type right well region 42 in the lightly doped N-type drift region 3. The left end of the gate electrode 6 extends above the region between the first source region 51 and the lightly doped N-type drift region 3, and the right end of the gate electrode 6 extends above the region between the second source region 52 and the lightly doped N-type drift region 3. A gate oxide layer 7 is provided between the gate electrode 6 and the lightly doped N-type drift region 3.
[0020] The lightly doped N-type drift region 3 has a medium-doped N-type vertical stripe 8 vertically disposed at the center between the P-type left well region 41 and the P-type right well region 42. The medium-doped N-type vertical stripe 8 is equidistant from the P-type left well region 41 and the P-type right well region 42 in the horizontal direction. A first upper metal layer 91 is located on the upper surface of the first source region 51 and the second source region 52, a second upper metal layer 92 is located on the upper surface of the gate electrode 6, and a lower metal layer 10 is located on the lower surface of the N-type drain region 2.
[0021] The lower end face of the N-type vertical stripe 8 and the lower end faces of the P-type left well region 41 and the P-type right well region 42 are located on the same plane.
[0022] The width between the aforementioned P-type left well region 41 and P-type right well region 42 is 6 times the width of the medium-doped N-type vertical stripe 8.
[0023] The upper metal layer 9 and the lower metal layer 10 mentioned above are copper metal layers.
[0024] The width of the gate oxide layer 7 is greater than the width of the gate electrode 6.
[0025] Example 2: A lateral MOS device, as shown in the figure, includes: an N-type drain region 2 and a lightly doped N-type drift region 3 stacked within a silicon wafer 1; a P-type left well region 41 and a P-type right well region 42 respectively located on the left and right sides of the upper part of the lightly doped N-type drift region 3; and a first source region 51 and a second source region 52 respectively located on the upper part of each of the P-type left well region 41 and the P-type right well region 42.
[0026] A gate electrode 6 is disposed directly above the region between the P-type left well region 41 and the P-type right well region 42 in the lightly doped N-type drift region 3. The left end of the gate electrode 6 extends above the region between the first source region 51 and the lightly doped N-type drift region 3, and the right end of the gate electrode 6 extends above the region between the second source region 52 and the lightly doped N-type drift region 3. A gate oxide layer 7 is provided between the gate electrode 6 and the lightly doped N-type drift region 3.
[0027] The lightly doped N-type drift region 3 has a medium-doped N-type vertical stripe 8 vertically disposed at the center between the P-type left well region 41 and the P-type right well region 42. The medium-doped N-type vertical stripe 8 is equidistant from the P-type left well region 41 and the P-type right well region 42 in the horizontal direction. A first upper metal layer 91 is located on the upper surface of the first source region 51 and the second source region 52, a second upper metal layer 92 is located on the upper surface of the gate electrode 6, and a lower metal layer 10 is located on the lower surface of the N-type drain region 2.
[0028] The lower end face of the N-type vertical stripe 8 and the lower end faces of the P-type left well region 41 and the P-type right well region 42 are located on the same plane.
[0029] The width between the aforementioned P-type left well region 41 and P-type right well region 42 is four times the width of the medium-doped N-type vertical stripe 8.
[0030] The aforementioned gate oxide layer 7 is a silicon dioxide layer.
[0031] The upper metal layer 9 and the lower metal layer 10 mentioned above are aluminum metal layers.
[0032] The width of the gate oxide layer 7 is greater than the width of the gate electrode 6.
[0033] When using the above-mentioned lateral MOS device, the left and right portions of the upper part of the lightly doped N-type drift region 3 have a P-type left well region 41 and a P-type right well region 42, respectively. The lightly doped N-type drift region 3 has a medium-doped N-type vertical stripe 8 in the region between the P-type left well region 41 and the P-type right well region 42. The width of the medium-doped N-type vertical stripe 8 is equal to that of the lightly doped N-type drift region 3 between the P-type left well region 41 and the P-type right well region 42. Adding a medium-doped N-type vertical stripe at the center of the current path avoids reducing the breakdown voltage and reduces the reverse recovery current, thereby reducing the overall loss of the device.
[0034] The above embodiments are only for illustrating the technical concept and features of this utility model, and are intended to enable those skilled in the art to understand the content of this utility model and implement it accordingly. They should not be construed as limiting the scope of protection of this utility model. All equivalent changes or modifications made in accordance with the spirit and essence of this utility model should be included within the scope of protection of this utility model.
Claims
1. A lateral MOS device, characterized in that: include: The N-type drain region (2) and the lightly doped N-type drift region (3) are stacked inside the silicon wafer (1). The left and right parts of the upper part of the lightly doped N-type drift region (3) have a P-type left well region (41) and a P-type right well region (42), respectively. The upper part of each of the P-type left well region (41) and the P-type right well region (42) has a first source region (51) and a second source region (52), respectively. A gate electrode (6) is disposed directly above the region between the P-type left well region (41) and the P-type right well region (42) of the lightly doped N-type drift region (3). The left end of the gate electrode (6) extends above the region between the first source region (51) and the lightly doped N-type drift region (3), and the right end of the gate electrode (6) extends above the region between the second source region (52) and the lightly doped N-type drift region (3). A gate oxide layer (7) is present between the gate electrode (6) and the lightly doped N-type drift region (3). The lightly doped N-type drift region (3) has a medium-doped N-type vertical strip (8) vertically disposed at the center between the P-type left well region (41) and the P-type right well region (42). The medium-doped N-type vertical strip (8) is equidistant from the P-type left well region (41) and the P-type right well region (42) in the horizontal direction. A first upper metal layer (91) is located on the upper surface of the first source region (51) and the second source region (52), a second upper metal layer (92) is located on the upper surface of the gate electrode (6), and a lower metal layer (10) is located on the lower surface of the N-type drain region (2).
2. The lateral MOS device according to claim 1, characterized in that: The lower end face of the medium-doped N-type vertical strip (8) is on the same plane as the lower end faces of the P-type left well region (41) and the P-type right well region (42).
3. The lateral MOS device according to claim 1, characterized in that: The width between the P-type left well region (41) and the P-type right well region (42) is 4 to 8 times the width of the medium-doped N-type vertical stripe (8).
4. The lateral MOS device according to claim 1, characterized in that: The gate oxide layer (7) is a silicon dioxide layer.
5. The lateral MOS device according to claim 1, characterized in that: The upper metal layer (9) and the lower metal layer (10) are aluminum metal layers or copper metal layers.
6. The lateral MOS device according to claim 1, characterized in that: The width of the gate oxide layer (7) is greater than the width of the gate electrode (6).