Trench power device, method of manufacturing the same, and electronic device

Abstract

The application relates to a trench power device and a preparation method thereof and electronic equipment, and comprises the following steps: providing a substrate; the substrate comprises a well region extending into the substrate via a first surface of the substrate; based on the same mask, strip-shaped source grooves and strip-shaped gate grooves with different opening sizes are simultaneously formed in the substrate along a first direction and a second direction; the strip-shaped source grooves and the strip-shaped gate grooves penetrate the well region along a third direction; an ion implantation process is performed on the substrate, so as to form a first shielding region at the bottom of the strip-shaped gate grooves and simultaneously form a second shielding region arranged at the bottom of the strip-shaped source grooves along the second direction; after a gate structure is formed in the strip-shaped gate grooves, a source metal that at least fills the strip-shaped source grooves is formed; wherein the substrate between adjacent second shielding regions along the second direction and the source metal form a Schottky structure; not only is the Ron, Vf and Erec low, but also the surge resistance is strong, and the manufacturing cost is relatively low.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a trench power device, a preparation method thereof and an electronic device. BACKGROUND

[0002] Metal-Oxide-Semicondμctor Field Effect Transistor (MOSFET) is a widely used and superior performance power device, among which, SiC material has strong attraction in high power due to its excellent characteristics, and becomes one of the ideal materials for high-performance power MOSFET. SiC MOSFET devices mainly include lateral double diffusion DMOSFET and vertical gate trench structure. The trench gate type silicon carbide (SiC) MOSFET device structure is favored due to its high trench gate crystal plane mobility, small cell size, high channel density, and no JFET area resistance.

[0003] With the development of semiconductor technology, small size, high power and high performance have become the main development trend. The continuous miniaturization of device physical size promotes the continuous reduction of cell design pitch. However, due to the limitation of process level and structure design, the miniaturization of trench gate type MOSFET device has limited performance optimization space. SUMMARY

[0004] Therefore, it is necessary to provide a trench power device, a preparation method thereof and an electronic device to at least achieve device miniaturization, performance upgrade and effective cost reduction.

[0005] In a first aspect, the present application provides a preparation method of a trench power device, comprising:

[0006] providing a substrate; the substrate comprises a well region extending into the substrate via a first surface of the substrate;

[0007] simultaneously forming strip-shaped source trenches and strip-shaped gate trenches with different opening sizes in the substrate along a first direction and a second direction based on the same mask; the strip-shaped source trenches and the strip-shaped gate trenches penetrate the well region along a third direction;

[0008] performing an ion implantation process on the substrate to form a first shielding region at the bottom of the strip-shaped gate trenches, and simultaneously form a second shielding region arranged at the bottom of the strip-shaped source trenches along the second direction;

[0009] after forming a gate structure in the strip-shaped gate trenches, forming a strip-shaped dielectric layer covering the top surface of the gate structure, and a source metal filling at least the strip-shaped source trenches; wherein the substrate between adjacent second shielding regions along the second direction and the source metal form a Schottky structure;

[0010] The first direction, the second direction and the third direction are perpendicular to each other.

[0011] In some embodiments, the opening size of the strip-shaped source trench is smaller than the opening size of the strip-shaped gate trench.

[0012] The depth of the strip-shaped source trench is smaller than the depth of the strip-shaped gate trench.

[0013] The depth is used to represent the dimension along the third direction.

[0014] In some embodiments, the substrate comprises, in sequence along the third direction, an epitaxial layer, a buffer layer and a substrate;

[0015] The second shielding region and the epitaxial layer, the buffer layer and the substrate directly below form a PiN structure; the PiN structure and the Schottky structure form an MPS structure extending along the second direction.

[0016] In some embodiments, forming the source metal comprises:

[0017] Removing part of the strip-shaped dielectric layer to form contact holes arranged at intervals along the first direction; the opening size of the contact holes is larger than the opening size of the strip-shaped source trench;

[0018] Removing the sacrificial layer in the strip-shaped source trench; the sacrificial layer and the gate structure are prepared synchronously in the same process step;

[0019] Forming a source metal filling at least the contact holes and the strip-shaped source trench.

[0020] In some embodiments, comprising: a substrate, a strip-shaped dielectric layer, a source metal; the substrate comprises a well region extending into the substrate via a first surface of the substrate;

[0021] The substrate comprises strip-shaped source trenches and strip-shaped gate trenches having different opening sizes arranged alternately at intervals along the first direction and extending along the second direction; the strip-shaped source trenches and the strip-shaped gate trenches are formed in the substrate simultaneously based on the same mask and penetrate the well region along the third direction;

[0022] The first shielding region at the bottom of the strip-shaped gate trench and the second shielding region at the bottom of the strip-shaped source trench arranged at intervals along the second direction are prepared synchronously in the same process step;

[0023] The strip-shaped gate trench comprises a gate structure, and the strip-shaped dielectric layer is located on the top surface of the gate structure.

[0024] The strip-shaped source trench comprises a source metal; wherein the substrate between adjacent second shielding regions along the second direction and the source metal form a Schottky structure.

[0025] In some embodiments, the opening size of the strip-shaped source trench is smaller than the opening size of the strip-shaped gate trench.

[0026] The depth of the strip-shaped source trench is less than the depth of the strip-shaped gate trench.

[0027] The depth is used to represent the dimension along the third direction.

[0028] In some embodiments, the substrate comprises, in sequence along the third direction, an epitaxial layer, a buffer layer and a substrate;

[0029] The second shielding region, together with the epitaxial layer, the buffer layer and the substrate directly below, forms a PiN structure; the PiN structure and the Schottky structure form an MPS structure extending along the second direction.

[0030] In some embodiments, the source metal comprises, in sequence along the third direction, a first part and a second part;

[0031] The first part is located in the strip-shaped source trench and has a bottom surface in contact with a top surface of the second shielding region;

[0032] The second part is arranged on the first surface along the first direction and spaced apart from the strip-shaped dielectric layer, and has a width greater than the opening size of the strip-shaped source trench;

[0033] The width is used to represent the dimension along the first direction.

[0034] In some embodiments, the first shielding region has a width not greater than the width of the strip-shaped source trench;

[0035] The second shielding region has a width not greater than the width of the strip-shaped gate trench.

[0036] In a third aspect, the present application provides an electronic device, comprising: a trench-type power device prepared by the preparation method of any one of the above embodiments, or a trench-type power device as described in any one of the above embodiments.

[0037] In the above embodiments, the strip-shaped source trench with a smaller opening size is prepared at the same time as the strip-shaped gate trench, replacing the deep and wide source trench in the related art, so that the trench preparation can be completed in one etching process. While reducing the cell pitch, the first shielding region and the second shielding region are prepared by single ion implantation as the electric field shielding layer during reverse bias.

[0038] In addition, the Schottky structure and the PiN structure are integrated in the strip-shaped source trench, and are arranged alternately with the strip-shaped gate trench along the second direction and spaced apart from the side wall of the gate trench, so as to avoid occupying the effective channel length on both sides of the gate from the structure, and finally realize the increase of channel density and the reduction of specific on-resistance, while taking into account the process simplification and performance optimization. BRIEF DESCRIPTION OF DRAWINGS

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 Power devices with trench gate structures provided in related technologies;

[0041] Figure 2 This is a schematic diagram of the trench-type power device provided in the embodiments of this application;

[0042] Figure 3 This is a flowchart of a method for fabricating a trench-type power device provided in one embodiment;

[0043] Figure 4 This is a schematic cross-sectional view of the substrate in step S20 of the preparation method provided in one embodiment;

[0044] Figure 5 for Figure 4 A schematic diagram of the cross-section of the structure after the formation of the trap region;

[0045] Figure 6 This is a cross-sectional schematic diagram of the structure obtained after forming strip-shaped source trenches and strip-shaped gate trenches in step S40 of the preparation method provided in one embodiment;

[0046] Figure 7 This is a cross-sectional schematic diagram of the structure obtained after forming the first shielding region and the second shielding region in step S60 of the preparation method provided in one embodiment;

[0047] Figure 8 for Figure 7 The photomask used;

[0048] Figure 9 This is the photomask used in step S60 in another embodiment;

[0049] Figure 10 This is a schematic cross-sectional view of the structure obtained after forming the gate structure and sacrificial layer in step S802 of the preparation method provided in one embodiment;

[0050] Figure 11 This is a cross-sectional schematic diagram of the structure obtained after forming a strip-shaped dielectric layer and contact holes in step S804 of the preparation method provided in one embodiment;

[0051] Figure 12 This is a schematic cross-sectional view of the structure obtained after forming the source metal in step S806 of the preparation method provided in one embodiment;

[0052] Figure 13 For Figure 12 Cross-sectional view of the resulting structure after performing a backside metallization process in the middle.

[0053] Reference Signs List:

[0054] 1, substrate; 2, buffer layer; 3, epitaxial layer; 10, substrate; 20, well region; 22, source region; 21, base region; 23, first shielding region; 24, second shielding region; 301, strip-shaped source trench; 30, MPS structure; 31, Schottky structure; 32, PiN structure; 40, gate structure; 401, strip-shaped gate trench; 41, gate oxide layer; 42, gate conductive layer; 11, strip-shaped dielectric layer; 501, contact hole; 51, source metal; 511, first part; 512, second part. DETAILED DESCRIPTION

[0055] For the purposes of this application, reference will be made to the accompanying drawings in which the preferred embodiments of the application are illustrated. It should be understood that the application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. It will be apparent that those skilled in the art will be able to make modifications to the embodiments disclosed herein without departing from the scope of the application.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0057] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be p-type and a second doped type can be n-type, or the first doped type can be n-type and the second doped type can be p-type.

[0058] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0059] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. In addition, use of the term "and / or" includes any and all combinations of associated items.

[0060] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0061] Traditional power MOSFETs all contain parasitic PiN body diodes. When these diodes switch from on to reverse breakdown state, they generate large reverse recovery currents and voltage spikes. Furthermore, the charge extraction from the drift region during reverse recovery significantly increases losses. In addition, the theoretical on-state voltage of silicon carbide body diodes is greater than 3.0V, resulting in high power dissipation. These issues lead to high switching losses and severe electromagnetic interference (EMI) in SiC MOSFETs, and can even cause circuit oscillations and device damage. Trench-type SiC power MOSFETs are not immune to these problems either.

[0062] In related technologies, an optimized SiC trench MOSFET structure integrating a Schottky junction has been proposed based on this typical structure. The specific structure is as follows: Figure 1 . Figure 1 (a) in the figure is a three-dimensional diagram of the structure. Figure 1 (b) in the figure is a top view of the structure, as shown below. Figure 1 As shown, the improved structure mainly adopts the design idea of ​​alternating Schottky and source ohmic contacts, integrating the Schottky structure into the sidewall of the gate trench. The design intercept is reduced, which occupies part of the channel length, resulting in an increase in the forward specific on-resistance of the MOS device, which is not conducive to the overall performance improvement.

[0063] Furthermore, in this structure, both the gate trench and the source trench are deep trench structures, requiring a larger width to meet the requirements of the etching process, which indirectly increases the device's design pitch. If only the size of the source trench is adjusted, the individual change in its depth or width will disrupt the original electric field distribution, easily causing local electric field concentration. During avalanche breakdown, current accumulation and heat accumulation will occur, leading to a decrease in the device's avalanche resistance.

[0064] For the convenience of understanding, in the embodiments mentioned in the application, the epitaxial layer can include a first surface located at the front surface, and a back surface opposite to the front surface, i.e. a second surface. In the case of ignoring the flatness of the first surface and the second surface, a first direction parallel to the first surface, a second direction, and a third direction towards the substrate are defined. Among them, the first direction, the second direction and the third direction are perpendicular to each other. The first direction is defined as the Y-axis direction, the second direction is defined as the X-axis direction, and the third direction is defined as the Z-axis direction.

[0065] Based on this, please refer to Figure 2 , Figure 2 (a) in the application provided in the silicon carbide power device shows a local plane top view, Figure 2 (b) and Figure 2 (c) in the application provides a kind of silicon carbide power device, including: substrate 10, MPS structure 30, gate structure 40 and source metal 51.In the embodiments mentioned in the application, N+ or P+ indicates heavy doping, N- or P- indicates light doping.

[0066] Specifically, the substrate 10 is composed of N+ type base 1, N+ type buffer layer 2 and N- type epitaxial layer 3 arranged in ZO direction in sequence. The well region 20 extending into the epitaxial layer 3 through the first surface is provided in the epitaxial layer 3, and the well region 20 includes N-type source region 22 and P-type base region 21 arranged in OZ direction.

[0067] Further, the first shielding region 23 and the second shielding region 24 of P+ type are also provided in the epitaxial layer 3, wherein the first shielding region 23 is arranged at the bottom of the gate structure 40, and the second shielding region 24 is arranged at the bottom of the strip-shaped source trench, and forms the PiN structure 32 in the MPS structure 30 with the N- type epitaxial layer 3, the N+ type buffer layer 2 and the N+ type base 1.

[0068] The top surface of the epitaxial layer 3 is provided with the source metal 51 in the form of "T" section, including the first part 511 and the second part 512 arranged in ZO direction. The second part 512 and the strip-shaped dielectric layer 11 are alternately arranged in OY direction, and the first part 511 is located in the strip-shaped source trench and forms ohmic contact with the second shielding region 24, and forms the Schottky structure 31 in the MPS structure 30 with the epitaxial layer 3 between the second shielding region 24 adjacent to it in OX direction.

[0069] The MPS structure 30 and the gate structure 40 are alternately and spacedly arranged in OY direction, and the specific structure is shown in Figure 2 (a), and the Schottky structure 31 and the PiN structure 32 are alternately arranged in OX direction, and the specific structure is shown in Figure 2 (b) and Figure 2 (c).

[0070] In the above embodiment, the PiN structure and the Schottky structure are arranged alternately and parallel to the strip-shaped gate trench, which does not increase the cell pitch and does not squeeze the length of the MOS channel. Figure 1 Compared with the power device shown in the related art, the cell provided by the present application has a greater channel density and a lower on-resistance Rsp.

[0071] In some embodiments, the first shielding region 23 and the second shielding region 24 are prepared simultaneously in the same process step; the source metal 51 and the Schottky structure 31 are prepared simultaneously in the same process step; and the strip-shaped source trench and the strip-shaped gate trench are prepared simultaneously in the same process step, which significantly reduces the manufacturing cost compared with the original scheme.

[0072] Next, the embodiment of forming the above silicon carbide power device is described. Referring to Figure 3 , the preparation method provided by the present application includes steps S20-S80.

[0073] Step S20: providing a substrate; the substrate includes a well region extending into the substrate via a first surface of the substrate.

[0074] Step S40: simultaneously forming strip-shaped source trenches and strip-shaped gate trenches with different opening sizes in the substrate along a first direction based on the same mask, the strip-shaped source trenches and the strip-shaped gate trenches extending along a second direction; the strip-shaped source trenches and the strip-shaped gate trenches penetrating the well region along a third direction.

[0075] Step S60: performing an ion implantation process on the substrate to form a first shielding region at the bottom of the strip-shaped gate trench while forming a second shielding region at the bottom of the strip-shaped source trench along the second direction.

[0076] Step S80: after forming a gate structure in the strip-shaped gate trench, forming a strip-shaped dielectric layer covering the top surface of the gate structure, and a source metal filling at least the strip-shaped source trench; wherein the substrate between adjacent second shielding regions along the second direction and the source metal form a Schottky structure.

[0077] It should be understood that, although Figure 3 the steps in the flowchart of the present application are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figure 3At least one of the steps in the method can comprise a plurality of steps or stages which are not necessarily performed at the same time but can be performed at different times and in which case the order of the steps or stages is not necessarily sequential but can be performed in rotation or alternation with other steps or steps or stages in other steps.

[0078] In the following, the exemplary method of manufacturing a power device according to the present application will be described with reference to the drawings. Figures 4 to 13 An exemplary method of manufacturing a power device according to the present application will be described below. Figures 4 to 13 An exemplary method of manufacturing a power device according to the present application will be described below.

[0079] Reference will now be made to Figures 4-5 , Figure 4 The wafer of SiC substrate plus epitaxial layer provided for the present application is in the original state. In the ZO direction, there are in order an N+ type base 1, an N+ type buffer layer 2, and an N- type epitaxial layer 3, all of which are doped with nitrogen. In the present example, the concentration of the base 1 is typically 1e20 cm -3 , and the concentration of the buffer layer 2 is typically 1e18 cm -3 . The epitaxial layer 3 is lightly doped, and is indicated by N-, the concentration of which in the present example is typically 1e16 cm -3 .

[0080] In the extension step of step S20, a general implantation is performed on the epitaxial layer 3 to form a base region 21 and a source region 22 arranged in order in the OZ direction, the resulting structure being as shown in Figure 5 In the present embodiment, the base region 21 and the source region 22 are collectively referred to as a well region 20.

[0081] Specifically, the implanted element of the base region 21 is aluminum, the doping concentration of which is in the range of 5e16 cm -3 - 5e18 cm -3 , for example 5e16 cm -3 , 5e17 cm -3 , or 5e18 cm -3 , and the implantation depth thereof is approximately 0.3 μm - 1.0 μm, for example 0.3 μm, 0.5 μm, 0.7 μm, or 1 μm. The implanted element of the source region 22 is nitrogen, the doping concentration of which is in the range of 1e19 cm -3 - 5e20 cm -3 , for example 1e19 cm -3 , 1e20 cm -3 , or 5e20 cm -3 , and the implantation depth thereof is approximately 0.02 μm - 0.3 μm, for example 0.02 μm, 0.04 μm, 0.06 μm, 0.08 μm, or 0.1 μm.

[0082] In the embodiment, the doping concentration of the base region 21 is 8e17cm -3 , the implantation depth is 0.5μm, the doping concentration of the source region 22 is 1e20cm -3 , and the implantation depth is 0.1μm.

[0083] Referring to Figure 6 , in the extending step of step S40, a photoetching and etching process is performed on the epitaxial layer 3 to form strip-shaped source grooves 301 and strip-shaped gate grooves 401 in the well region 20, which are alternately arranged along OY and extend along OX. The structure obtained is as shown in Figure 6 .

[0084] As Figure 6 shown, the structure after the epitaxial layer 3 is etched with grooves after implanting the well region 20. The wide and deep one is the strip-shaped gate groove 401, and the narrow and slightly shallow one is the strip-shaped source groove 301. By optimizing the depth-width ratio, the double-groove one-step etching process is completed synchronously, reducing the steps of separate adjustment and processing in batches, simplifying the process flow, and reducing the processing cost.

[0085] For example, the depth of the strip-shaped gate groove 401 is 0.9μm-1μm, such as 0.9μm, 0.95μm or 1μm, etc., and the width is 0.9μm-1.5μm, such as 0.9μm, 1μm or 1.5μm, etc.; the depth of the strip-shaped source groove 301 is 0.7μm-0.8μm, such as 0.7μm, 0.75μm or 0.8μm, etc. In the embodiment, the width of the strip-shaped gate groove 401 is 1μm, and the width of the strip-shaped source groove 301 is determined by the capacity of the etching machine and the process parameter adjustment.

[0086] Referring to Figures 7-9 , in the extending step of step S60, a patterned ion implantation is performed on the epitaxial layer 3 to form P+ type second shielding regions 24 which are alternately arranged with the P+ type first shielding regions 23 along OY and are spaced along OX. The structure obtained is as shown in Figure 7 .

[0087] Specifically, the ion implantation can be performed at an angle of 0°-7°. The implantation element of the first shielding region 23 and the second shielding region 24 is aluminum, and the doping concentration is 1e19cm -3 -5e20cm -3 , such as 1e19cm -3 , 1e20cm -3 or 5e20cm -3 , etc., and the implantation depth is 0.8μm-1.5μm, such as 0.8μm, 1μm, 1.2μm or 1.5μm, etc. In the embodiment, the doping concentration of the first shielding region 23 and the second shielding region 24 is 2e20cm-3 The implantation depth is 1.2 μm.

[0088] Further, Figure 8 The photomask used in step S602 is shown in the design. The photomask has different implantation features in the longitudinal direction of the device, and the black position represents the implantation region. The narrow implantation region is the diode region, and the width is not greater than the width of the aforementioned strip source trench 301, and the typical value is 0.6 μm; the wide implantation region is the passivation layer at the bottom of the trench, and the typical value is 0.9 μm. The position of the A-A' tangent corresponds to the cross section shown in (b) of Figure 7 , which represents P+ implantation into part of the strip source trench 301, where the second shielding region 24 (i.e., the anode of the PiN diode) will be formed; the position of the B-B' tangent corresponds to the cross section shown in (c) of Figure 7 , which represents P+ not implanted into the strip source trench 301, where the Schottky structure described later will be formed.

[0089] In the above embodiment, the embedded Schottky structure and the PiN structure together constitute the MPS structure. The low barrier characteristic of the Schottky structure can reduce the reverse conduction voltage drop Vf, and the Schottky junction has no conductivity modulation effect, which can significantly reduce the reverse recovery loss Erec. The PiN structure mainly undertakes the function of surge current tolerance, and comprehensively improves the performance of the diode region of the device.

[0090] Of course, in some embodiments, the ratio of x:y on the photomask can be freely adjusted to obtain a more reasonable PiN:Schottky ratio. The typical value of the present technical solution is 1.5 μm:1.5 μm. A misaligned photomask as shown in Figure 9 can also be used to realize the synchronous preparation of the first shielding region 23 and the second shielding region 24. After the above two-step implantation and one-step trench etching, the entire ion implantation of the device can be completed. Compared with the conventional scheme, the number of etched trench channels and the number of ion implantation layers are greatly reduced, effectively reducing the manufacturing complexity and manufacturing cost of the device.

[0091] Please refer to Figures 10-13 , the extension step of step S80 includes:

[0092] Step S802: After the above two-step patterned implantation, high-temperature annealing is performed on the device to activate the implanted ions, and the typical annealing temperature range is 1600°C~1750°C. After the gate oxide layer 41 is formed in the strip gate trench and the strip source trench, the polycrystalline silicon is filled and etched back to form the gate conductive layer 42, the gate structure 40 is formed in the strip gate trench, and the gate oxide layer 41 and the polycrystalline silicon in the strip source trench are used to form a sacrificial layer. The specific structure is shown in Figure 10 .

[0093] In the above embodiment, the first shielding region 23 at the bottom serves as an electric field shielding layer in the reverse bias state, protecting the bottom of the trench, shielding the high electric field, and ensuring that the channel density is not substantially damaged, thereby significantly enhancing the gate oxide reliability of the device and reducing the requirements for the gate oxide process.

[0094] Step S804: Form a strip-shaped dielectric layer 11 on the first surface using a deposition process, and use a reflow process or a chemical mechanical planarization process to make the top surface flat. After etching the strip-shaped dielectric layer 11 to form a contact hole 501 extending in the OZ direction and the OX direction, the sacrificial layer in the strip-shaped source trench 301 is removed using a combination of dry etching and wet etching, and the resulting structure is as shown in Figure 11 .

[0095] For example, the material of the strip-shaped dielectric layer 11 includes, but is not limited to, a high-k dielectric constant material. For example, aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3), etc. In this embodiment, the thickness of the strip-shaped dielectric layer 11 is 1 μm.

[0096] Step S806: Form a metal layer that fills the contact hole and the strip-shaped source trench, and covers the top surface of the strip-shaped dielectric layer 11. The metal layer in the contact hole and the strip-shaped source trench constitutes the source metal 51, and the resulting structure is as shown in Figure 12 (a).

[0097] In the OX direction, as shown in Figure 12 (b), the first part 511 of the source metal 51 is in contact with the top surface of the second shielding region 24 to form an ohmic contact, and the second shielding region 24 forms a PiN structure 32 with the epitaxial layer 3, the buffer layer 2, and the substrate 1. Figure 12 As shown in (c), the first part 511 is in contact with the epitaxial layer 3 between the second shielding region 24 adjacent in the OX direction to form a Schottky junction.

[0098] It should be understood that, as shown in Figure 12 (b), the lower surface of the source metal 51 that is not surrounded by the second shielding region 24 will also form a Schottky junction with the peripheral epitaxial layer 3. Since the PiN structure 32 is mainly used to resist the impact of inrush current, the Schottky junction will not have a negative impact on the PiN structure 32.

[0099] In addition, as shown in Figure 12 (c), the first shielding region 23 not only protects the gate oxide layer, but also forms a thick depletion region between the first shielding region 23, the second shielding region 24, the base region 21, and the N-type epitaxial layer 3 in the reverse bias state, shielding the Schottky junction, reducing the reverse leakage current of the Schottky junction, and improving the stability of the device.

[0100] In some embodiments, step S804 further comprises front side metallization process steps including nickel silicide (NiSilicide) formation, Ti / TiN deposition and W deposition, Al / Cu deposition, etc. After step S804, back side substrate 1 needs to be thinned, back side metallization process, which is not the focus of the technical solution, is not described in detail here, and the final structure is as shown in Figure 13 .

[0101] In the above embodiments, the unexpected technical effects of the present application are:

[0102] The trench power device provided by the present application, the preparation method thereof and the electronic equipment, innovatively optimize the double-trench aspect ratio, realize the completion of strip-shaped source trench and strip-shaped gate trench etching at the same time, and the first shielding area and the second shielding area are prepared at the same time in the same process step, thereby greatly reducing the trench etching times and ion implantation layers, and significantly reducing the manufacturing complexity and manufacturing cost.

[0103] From the perspective of device electrical performance, by alternately arranging the PiN structure and the Schottky structure and parallel to the trench, the cell design pitch is not only avoided from being increased, but also the MOS channel length is not occupied, greater channel density and lower specific on-resistance Rsp are achieved compared with the related art; at the same time, the first shielding area at the bottom of the strip-shaped gate trench can shield a high electric field and enhance the gate oxide reliability, the second shielding area at the bottom of the strip-shaped source trench and the epitaxial layer, the buffer layer and the substrate form a PiN structure, cooperating with the Schottky structure formed by the source metal and the epitaxial layer, the formed MPS structure not only reduces the reverse conduction voltage drop Vf and the reverse recovery loss Erec, but also improves the surge resistance, and the width ratio of the PiN and the Schottky can be flexibly matched by adjusting the photoetching plate parameters.

[0104] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features of the above embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the description.

[0105] The above-described embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as a limitation on the patent application scope. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method for fabricating a trench-type power device, characterized in that, include: Provide substrate; The substrate includes a well region extending into the substrate via a first surface of the substrate; Based on the same photomask, strip-shaped source trenches and strip-shaped gate trenches with different opening sizes are simultaneously formed in the substrate, which are alternately arranged along the first direction and extend along the second direction. The strip-shaped source trench and the strip-shaped gate trench penetrate the well region along a third direction; The opening size of the strip source trench is smaller than the opening size of the strip grid trench, and the depth of the strip source trench is smaller than the depth of the strip grid trench. An ion implantation process is performed on the substrate to form a first shielding region at the bottom of the strip-shaped gate trench, while simultaneously forming a plurality of second shielding regions spaced apart at the bottom of the strip-shaped source trench along the second direction; After forming the gate structure in the strip-shaped gate trench, a strip-shaped dielectric layer covering the top surface of the gate structure and a source metal that at least fills the strip-shaped source trench are formed; wherein, a Schottky structure is formed on the side and bottom of the substrate adjacent to the second shielding region along the second direction and the source metal embedded in the substrate; the area ratio of the Schottky structure on the chip is freely adjustable by the photomask forming the second shielding region; The depth is used to characterize the dimension along the third direction; the first direction, the second direction, and the third direction are all perpendicular to each other.

2. The preparation method according to claim 1, characterized in that, The source metal includes a first part and a second part arranged in a direction opposite to the third part; The first part is located within the strip-shaped source trench, with its bottom surface in contact with the top surface of the second shielding area; The second part is arranged on the first surface at intervals from the strip-shaped dielectric layer along the first direction, and its width is greater than the opening size of the strip-shaped source trench; The width is used to characterize the dimension along the first direction.

3. The preparation method according to claim 2, characterized in that, The substrate includes an epitaxial layer, a buffer layer, and a substrate arranged sequentially along a third direction; The second shielding region, together with the epitaxial layer, buffer layer, and substrate directly below it, constitutes a PiN structure; the PiN structure and the Schottky structure form an MPS structure extending along the second direction.

4. The preparation method according to claim 3, characterized in that, The source metal is formed by: A portion of the strip-shaped dielectric layer is removed to form contact holes spaced apart along the first direction; the opening size of the contact holes is larger than the opening size of the strip-shaped source trench. Remove the sacrificial layer within the strip-shaped source trench; the sacrificial layer and the gate structure are fabricated simultaneously in the same process steps. A source metal is formed that at least fills the contact hole and the strip-shaped source trench.

5. A trench-type power device, characterized in that, include: A substrate, a strip-shaped dielectric layer, and a source metal; the substrate includes a well region extending into the substrate via a first surface of the substrate; The substrate includes strip-shaped source trenches and strip-shaped gate trenches with different opening sizes, which are alternately arranged along a first direction and extend along a second direction; the strip-shaped source trenches and the strip-shaped gate trenches are formed simultaneously in the substrate based on the same photomask and penetrate the well region along a third direction; The opening size of the strip-shaped source trench is smaller than the opening size of the strip-shaped grid trench; the depth of the strip-shaped source trench is smaller than the depth of the strip-shaped grid trench. In the same process steps, a first shielding area located at the bottom of the strip-shaped grid trench and a plurality of second shielding areas arranged at intervals along the second direction at the bottom of the strip-shaped source trench are prepared simultaneously. The strip-shaped gate trench includes a gate structure, and the strip-shaped dielectric layer is located on the top surface of the gate structure; The strip-shaped source trench includes source metal; wherein, a Schottky structure is formed between the substrate adjacent to the second shielding area along the second direction and the side and bottom of the source metal embedded in the substrate; the area ratio of the Schottky structure on the chip is freely adjustable by the photomask forming the second shielding area; The depth is used to characterize the dimension along the third direction.

6. The trench-type power device according to claim 5, characterized in that, The substrate includes an epitaxial layer, a buffer layer, and a substrate arranged sequentially along a third direction; The second shielding region, together with the epitaxial layer, buffer layer, and substrate directly below it, constitutes a PiN structure; the PiN structure and the Schottky structure form an MPS structure extending along the second direction.

7. The trench-type power device according to claim 5, characterized in that, The source metal includes a first part and a second part arranged in a direction opposite to the third part; The first part is located within the strip-shaped source trench, with its bottom surface in contact with the top surface of the second shielding area; The second part is arranged on the first surface at intervals from the strip-shaped dielectric layer along the first direction, and its width is greater than the opening size of the strip-shaped source trench; The width is used to characterize the dimension along the first direction.

8. The trench-type power device according to claim 7, characterized in that, The width of the first shielding area is not greater than the width of the strip-shaped source trench; The width of the second shielding area is not greater than the width of the strip-shaped grid groove.

9. An electronic device, characterized in that, include: A trench-type power device prepared by the preparation method according to any one of claims 1-4; or The trench power device as described in any one of claims 5-8.

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