Integrated die

Abstract

The embodiment of the utility model provides an integrated crystal grain. An integrated die includes a substrate, a semiconductor waveguide layer, a conductive heater wire, a first heater contact, and a second heater contact. The semiconductor waveguide layer is over the substrate. A base portion of the semiconductor waveguide layer extends across over the substrate. The ridge portion of the semiconductor waveguide layer protrudes upward beyond the base portion. Conductive heater lines are spaced over the ridge portion of the semiconductor waveguide layer. First and second heater contacts extend from the conductive heater wire to a base portion of the semiconductor waveguide layer on opposite sides of the ridge portion of the semiconductor waveguide layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to an integrated die. BACKGROUND

[0002] Optical waveguides are often used as components in integrated optical circuits. Optical waveguides are used to confine and guide light from a first point on an integrated chip (IC) to a second point on the IC while minimizing attenuation. Many modern optical waveguides are formed using semiconductors. The semiconductor waveguides can include optical transducers or optical couplers for optically coupling optical fibers to the semiconductor waveguides. SUMMARY

[0003] In some embodiments, the present summary relates to an integrated die comprising a substrate, a semiconductor waveguide layer, a conductive heater line, a first heater contact, and a second heater contact. The semiconductor waveguide layer is positioned above the substrate. A base portion of the semiconductor waveguide layer extends laterally above the substrate. A ridge portion of the semiconductor waveguide layer protrudes upwardly from the base portion. The conductive heater line is spaced above the ridge portion of the semiconductor waveguide layer. The first heater contact and the second heater contact extend from the conductive heater line to the base portion of the semiconductor waveguide layer on opposite sides of the ridge portion of the semiconductor waveguide layer.

[0004] In other embodiments, the present summary relates to an integrated die comprising a substrate, a semiconductor waveguide layer, a dielectric structure, a first heater contact, a second heater contact, and a conductive heater line. The semiconductor waveguide layer is positioned above the substrate. The dielectric structure is positioned above the semiconductor waveguide layer. The first heater contact and the second heater contact are positioned above the semiconductor waveguide layer. A ridge portion of the semiconductor waveguide layer protrudes upwardly from a base portion of the semiconductor waveguide layer directly between the first heater contact and the second heater contact. The conductive heater line extends onto the dielectric structure directly above the ridge portion of the semiconductor waveguide layer and between the first heater contact and the second heater contact. The first heater contact and the second heater contact extend through the dielectric structure and contact the base portion of the semiconductor waveguide layer. BRIEF DESCRIPTION OF DRAWINGS

[0005] The various aspects of the present summary can be best understood with respect to the following detailed description in conjunction with the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale in accordance with standard practice of the art. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0006] Figure 1Cross-sectional views showing some embodiments of a photonic integrated die including a heater located above and in contact with a waveguide.

[0007] Figure 2 Top views showing some embodiments of a photonic integrated die. Figure 1

[0008] Figures 3 to 6 Cross-sectional views showing some other embodiments of a photonic integrated die. Figure 1

[0009] Figure 7 Cross-sectional views showing some embodiments of a photonic integrated die in which the waveguide forms a micro-ring modulator. Figure 1

[0010] Figure 8 Top views showing some embodiments of a photonic integrated die. Figure 7

[0011] Figure 9 Cross-sectional views showing some embodiments of a photonic integrated die in which the waveguide forms a Mach-Zehnder modulator. Figure 1

[0012] Figure 10 Top views showing some embodiments of a photonic integrated die. Figure 9

[0013] Figures 11 to 26 Cross-sectional views showing some embodiments of a method of forming a photonic integrated die including a heater located above and in contact with a waveguide.

[0014] Figure 27 Flowcharts showing some embodiments of a method of forming a photonic integrated die including a heater located above and in contact with a waveguide.

[0015] BRIEF DESCRIPTION OF DRAWINGS

[0016] 100, 300, 400, 600, 700, 900, 1100, 1100, 1200, 1300, 1400, 1500, 1500-2100, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2200, 2300, 2400, 2500, 2600: cross-sectional view

[0017] 101x, 101y, 101z: direction

[0018] ​​​​​​102: base semiconductor layer

[0019] 104: base dielectric layer

[0020] 108: semiconductor waveguide layer

[0021] 108a, 122a: bottom surface

[0022] 108b, 108c, 108f, 108g, 118a, 120a: sidewall

[0023] 108d, 108e: top surface

[0024] 108h: top surface

[0025] 110: base portion

[0026] 112, 906: ridge portion

[0027] 114: dielectric structure

[0028] 118, 120, 702, 910, 912: heater contact

[0029] 122, 914: heater line

[0030] 124, 126, 128, 318: distance

[0031] 200, 800, 1000: top view

[0032] 302, 304, 306, 502, 504: doped region

[0033] 308, 310, 312: thickness

[0034] 314, 316: width

[0035] 320: first etch stop layer

[0036] 322: first dielectric layer

[0037] 324: second etch stop layer

[0038] 326: second dielectric layer

[0039] 402: upper via

[0040] 404: lower via

[0041] 506, 1402, 1404: intrinsic region

[0042] 508, 510: contact region

[0043] 512, 514: wire

[0044] 602: barrier layer

[0045] 604, 606: via

[0046] 608, 610: line

[0047] 802, 804: waveguide

[0048] 806: microring modulator

[0049] 902, 904: splitter

[0050] 1302, 1304, 1606, 1904, 2304, 2406: mask layer

[0051] 1602, 1604, 1902, 2302, 2402, 2404: opening

[0052] 2700: method

[0053] 2702, 2704, 2706, 2708: block DETAILED DESCRIPTION

[0054] The following detailed description is presented to enable any person skilled in the art to make and use the application. Various modifications to the embodiments described herein will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit or scope of the application. Accordingly, the present application is not intended to be limited to the embodiments described herein but is to be accorded the widest scope consistent with the principles and features disclosed herein. The following detailed description is presented to enable any person skilled in the art to make and use the application. Various modifications to the embodiments described herein will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit or scope of the application. Accordingly, the present application is not intended to be limited to the embodiments described herein but is to be accorded the widest scope consistent with the principles and features disclosed herein. For the purposes of the present application, the terms "coupled" and "connected," along with their derivatives, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" can be used to indicate that two or more elements are in direct physical contact with each other. "Coupled" can mean that two or more elements are in direct physical contact. However, "coupled" can also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other in some manner. Additionally, the term "coupled" can mean that two or more elements are able to co-operate or interact with each other in some manner.

[0055] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0056] A photonic integrated die includes a waveguide on a substrate. The waveguide is formed from a semiconductor waveguide layer. A base portion of the semiconductor waveguide layer extends across the substrate, and a ridge portion of the semiconductor waveguide layer protrudes upward from the base portion. Optical radiation (e.g., an optical signal) travels through the semiconductor waveguide layer. In some cases, a majority of the optical radiation traveling through the semiconductor waveguide layer is confined within the ridge portion of the semiconductor waveguide layer.

[0057] The performance of the semiconductor waveguide layer can be affected by the temperature of the semiconductor waveguide layer. For example, the phase of an optical signal traveling through the semiconductor waveguide layer can be affected by the temperature of the semiconductor waveguide layer. Accordingly, a heater is disposed above the semiconductor waveguide layer to control the temperature of the semiconductor waveguide layer. The heater is formed from an electrically conductive heater line. The electrically conductive heater line is positioned above the ridge portion of the semiconductor waveguide layer. In some cases, the heater can cause optical radiation loss in the semiconductor waveguide layer if the heater is too close to the ridge portion. Accordingly, the electrically conductive heater line is spaced apart from the ridge portion. An electrical current is passed through the electrically conductive heater line to increase the temperature of the electrically conductive heater line. The temperature of the electrically conductive heater line can be controlled by controlling the electrical current. Heat emitted from the electrically conductive heater line heats the semiconductor waveguide layer. By using the heater to control the temperature of the semiconductor waveguide layer, control of the waveguide performance can be improved.

[0058] One challenge with the heater is that the sides of the ridge portion of the semiconductor waveguide layer are less exposed to heat from the heater than the top of the ridge portion of the semiconductor waveguide layer. Accordingly, temperature control of the sides of the ridge portion of the semiconductor waveguide layer can be reduced. Another challenge with the heater is that the spacing between the heater and the semiconductor waveguide layer can inhibit heat transfer from the electrically conductive heater line to the semiconductor waveguide layer. Accordingly, temperature control of the semiconductor waveguide layer can be further reduced.

[0059] According to various embodiments in accordance with the present disclosure, the heater is further formed from a first heater contact and a second heater contact that extend from the electrically conductive heater line to the base portion of the semiconductor waveguide layer on opposite sides of the ridge portion of the semiconductor waveguide layer. The first heater contact and the second heater contact contact the base portion of the semiconductor waveguide layer and are laterally spaced apart from the ridge portion of the semiconductor waveguide layer by a substantial distance.

[0060] Because the heater contacts extend along the sides of the ridge portion of the semiconductor waveguide layer, the area of the ridge portion exposed to the heater is increased. As a result, control of the temperature of the ridge portion can be improved, and thus control of the waveguide performance can be improved. Furthermore, because the heater contacts directly contact the base portion of the semiconductor waveguide layer, heat transfer from the heater to the semiconductor waveguide layer can be improved. As a result, control of the temperature of the semiconductor waveguide layer can be further improved. Moreover, because a substantial distance is maintained between the heater contacts and the ridge portion, the likelihood of the heater causing optical radiation loss along the semiconductor waveguide layer can be reduced.

[0061] Figure 1 A cross-sectional view 100 of some embodiments of a photonic integrated die including a heater positioned above and in contact with a waveguide is shown.

[0062] The integrated die includes a base semiconductor layer 102 and a base dielectric layer 104 positioned above the base semiconductor layer 102. In some embodiments, the base semiconductor layer 102 and the base dielectric layer 104 are referred to as a substrate.

[0063] A semiconductor waveguide layer 108 is positioned above the base dielectric layer 104. The semiconductor waveguide layer 108 forms a waveguide. A base portion 110 of the semiconductor waveguide layer 108 extends laterally along a top surface of the base dielectric layer 104. The base portion 110 is defined by a bottom surface 108a, a first sidewall 108b, a second sidewall 108c, a first upper surface 108d, and a second upper surface 108e of the semiconductor waveguide layer 108. A ridge portion 112 of the semiconductor waveguide layer 108 protrudes upward from the base portion 110. The ridge portion 112 is defined by a third sidewall 108f, a fourth sidewall 108g, and a top surface 108h of the semiconductor waveguide layer 108.

[0064] A heater is positioned above the semiconductor waveguide layer 108. The heater is formed by an electrically conductive heater line 122, a first electrically conductive heater contact 118, and a second electrically conductive heater contact 120. The heater line 122 is spaced apart from the semiconductor waveguide layer 108. The heater line 122 extends laterally above the base portion 110 and the ridge portion 112 of the semiconductor waveguide layer 108. The first heater contact 118 and the second heater contact 120 extend from the heater line 122 to the base portion 110 of the semiconductor waveguide layer 108 on opposite sides of the ridge portion 112 of the semiconductor waveguide layer 108. The first heater contact 118 contacts the first upper surface 108d of the semiconductor waveguide layer 108 and is laterally spaced apart from the ridge portion 112 in a first direction. The second heater contact 120 contacts the second upper surface 108e of the semiconductor waveguide layer 108 and is laterally spaced apart from the ridge portion 112 in a second direction opposite the first direction.

[0065] The dielectric structure 114 includes one or more dielectric layers positioned above the semiconductor waveguide layer 108 and surrounding the heater contacts 118, 120, the heater line 122, and the semiconductor waveguide layer 108. The dielectric structure 114 is positioned directly between the semiconductor waveguide layer 108 and the heater line 122, and between the semiconductor waveguide layer 108 and the heater contacts 118, 120. The dielectric structure 114 is or includes a cladding layer that further forms a waveguide.

[0066] Because the heater contacts 118, 120 extend along the sides of the ridge portion 112 of the semiconductor waveguide layer 108 (e.g., where most of the optical radiation is typically confined), the area of the ridge portion 112 exposed to the heater is increased. As a result, control of the temperature of the ridge portion 112 can be improved. Moreover, because the heater contacts 118, 120 are in contact with the base portion 110 of the semiconductor waveguide layer 108, heat transfer from the heater to the semiconductor waveguide layer 108 can be improved. As a result, control of the temperature of the semiconductor waveguide layer 108 can be further improved. Moreover, a substantial distance is maintained between the heater and the ridge portion 112 to reduce the likelihood of the heater causing optical radiation loss along the semiconductor waveguide layer 108.

[0067] The spacing between the ridge portion 112 and the heater (e.g., the heater line 122 and the heater contacts 118, 120) is large enough to reduce or prevent significant optical loss along the semiconductor waveguide layer 108. For example, the distance 124 between the bottom surface 122a of the heater line 122 and the top surface 108h of the semiconductor waveguide layer 108, the distance 126 between the sidewall 108f of the semiconductor waveguide layer 108 and the sidewall 118a of the first heater contact 118, and the distance 128 between the sidewall 108g of the semiconductor waveguide layer 108 and the sidewall 120a of the second heater contact 120 is at least 100 nanometers, at least 500 nanometers, at least 1 micrometer, at least 5 micrometers, or other suitable distance. In some embodiments, the distance 124, the distance 126, and the distance 128 range from 100 nanometers to 10 micrometers, 500 nanometers to 5 micrometers, 1 micrometer to 2 micrometers, or other suitable range.

[0068] In some embodiments, the base semiconductor layer 102 includes silicon or some other suitable semiconductor. In some embodiments, the base dielectric layer 104 includes silicon dioxide or some other suitable dielectric material. In some embodiments, the semiconductor waveguide layer 108 includes intrinsic (e.g., undoped) silicon or some other suitable semiconductor. In some embodiments, the heater line 122 and the heater contacts 118, 120 include one or more metals, such as copper, aluminum, titanium nitride, tungsten, or some other suitable material.

[0069] In some embodiments, the dielectric layers of the dielectric structure 114 include silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, or some other suitable material. In some embodiments, the thermal capacity of the region between the heater and the waveguide can be tuned by adjusting the dielectric material between the waveguide and the heater. For example, in some embodiments, a first dielectric has a first thermal capacity that is between the heater and the waveguide. In some other embodiments, a second dielectric has a second thermal capacity that is different from the first thermal capacity that is between the heater and the waveguide. By tuning the thermal capacity within the space between the heater and the waveguide, the control of the temperature of the semiconductor waveguide layer 108 can be further improved.

[0070] Figure 2 A top view 200 of some embodiments of the photonic integrated die is shown. Figure 1 In some embodiments, the cross-sectional view 100 is taken along the line A-A’ of the photonic integrated die 100. Figure 1 In some embodiments, the cross-sectional view 100 is taken along the line A-A’ of the photonic integrated die 100. Figure 2 In some embodiments, the dielectric structure 114 is not shown in the cross-sectional view 100, and the heater lines 122 are shown in “phantom” (e.g., dashed lines) in order to clearly show the underlying layers. Figure 2 In some embodiments, the dielectric structure 114 is not shown in the cross-sectional view 100, and the heater lines 122 are shown in “phantom” (e.g., dashed lines) in order to clearly show the underlying layers. Figure 2 In some embodiments, the dielectric structure 114 is not shown in the cross-sectional view 100, and the heater lines 122 are shown in “phantom” (e.g., dashed lines) in order to clearly show the underlying layers.

[0071] The base portion 110 and the ridge portion 112 of the semiconductor waveguide layer 108 extend in the direction 101y. In some embodiments, the heater contacts 118, 120 and the heater line 122 also extend in the direction 101y, along a portion of the length of the ridge portion 112. In some embodiments, the length of the heater line 122 (in the direction 101y) is approximately equal to the length of the heater contacts 118, 120 (in the direction 101y). In some embodiments, the width of the heater line 122 (in the direction 101x) is greater than the width of the semiconductor waveguide layer 108 (in the direction 101x).

[0072] Figure 3 A cross-sectional view 300 of some embodiments of the photonic integrated die is shown, in which regions of the semiconductor waveguide layer 108 are doped. Figure 1 In some embodiments, the cross-sectional view 300 is taken along the line A-A’ of the photonic integrated die 300.

[0073] The first doped region 302 of the semiconductor waveguide layer 108 has a first doping type. The first doped region 302 is located in the ridge portion 112, as well as in a portion of the base portion 110 directly below the ridge portion 112. In addition, the first doped region 302 is located in the base portion 110 on opposite sides of the ridge portion 112. The second doped region 304 and the third doped region 306 of the semiconductor waveguide layer 108 have the first doping type. The second doped region 304 is located in the base portion 110 directly below the first heater contact 118. The third doped region 306 is located in the base portion 110 directly below the second heater contact 120.

[0074] The second and third doped regions 304, 306 have a higher doping concentration than the first doped region 302. For example, the second and third doped regions 304, 306 have a doping concentration ranging from 1016cm-3to 1019cm-3, 1017cm-3to 1018cm-3, or other suitable range, and the first doped region 302 has a doping concentration ranging from 1013cm-3to 1015cm-3, 1014cm-3to 1015cm-3, or other suitable range.

[0075] By including the second doped region 304, the third doped region 306, where the heater contacts 118, 120 are in contact with a higher doping concentration at the semiconductor waveguide layer 108, the contact resistance between the heater contacts 118, 120 and the semiconductor waveguide layer 108 can be reduced. By reducing the contact resistance, heat transfer and heating efficiency can be improved. Further, by including the first doped region 302, which has a lower doping concentration along the ridge portion 112, the electrical resistance at the ridge portion 112 can be adjusted to reduce optical loss along the ridge portion 112.

[0076] In some embodiments, the first doping type is p-type doping. In some other embodiments, the first doping type is n-type doping.

[0077] In some embodiments, the thickness 308 (along direction 101z) of the heater line 122 ranges from 10 nanometers to 5 micrometers, 500 nanometers to 2.5 micrometers, or other suitable range. In some embodiments, the thickness 310, 312 (along direction 101z) of the heater contacts 118, 120 ranges from 10 nanometers to 5 micrometers, 500 nanometers to 2.5 micrometers, or other suitable range. In some embodiments, the width 314, 316 (along direction 101x) of the heater contacts 118, 120 ranges from 100 nanometers to 20 micrometers, 500 nanometers to 10 micrometers, or other suitable range. In some embodiments, the distance 318 (along direction 101x) between the heater contacts (e.g., the distance between the sidewall 118a and the sidewall 120a) ranges from 100 nanometers to 10 micrometers, 500 nanometers to 5 micrometers, or other suitable range.

[0078] In some embodiments, the dielectric structure 114 includes a first etch stop layer 320 on the semiconductor waveguide layer 108, a first dielectric layer 322 on the first etch stop layer 320, a second etch stop layer 324 on the first dielectric layer 322, and a second dielectric layer 326 on the second etch stop layer 324. The heater line 122 extends to a top surface of the second etch stop layer 324. The second etch stop layer 324 is directly between the heater line 122 and the ridge portion 112. The heater contacts 118, 120 extend through the second etch stop layer 324 and the first dielectric layer 322 to the semiconductor waveguide layer 108.

[0079] In some embodiments, the heater is formed by a dual damascene process, in which the heater line 122 and the heater contacts 118, 120 are formed together in a common deposition process.

[0080] In some embodiments, the first etch stop layer 320 and the second etch stop layer 324 include silicon nitride, silicon carbide, silicon carbon nitride, silicon oxycarbide, or some other suitable material. In some embodiments, the first dielectric layer 322 and the second dielectric layer 326 include silicon dioxide, silicon nitride, or some other suitable material.

[0081] Figure 4 A cross-sectional view 400 of some embodiments of the photonic integrated die, in which an upper cavity 402 and a lower cavity 404 surround the waveguide. Figure 1

[0082] The upper cavity 402 is between the ridge portion 112 and the heater. The upper cavity 402 is defined by a bottom surface 122a of the heater line 122, a sidewall 118a of the first heater contact 118, and a sidewall 120a of the second heater contact 120. In some embodiments, sidewalls (e.g., sidewalls 108f, 108g) and upper surfaces (e.g., top surface 108h and upper surfaces 108d, 108e) of the semiconductor waveguide layer 108 further define the upper cavity 402. In some other embodiments, the first etch stop layer 320 remains on the ridge portion 112, so sidewalls and upper surfaces of the first etch stop layer 320 further define the upper cavity 402. The upper cavity 402 is filled with air or similar substance. Air has a higher heat capacity than the dielectric of the dielectric structure 114 (e.g., silicon dioxide or similar substance). Thus, the upper cavity 402 can be formed between the heater and the waveguide to adjust the heat capacity of the spacing between the heater and the waveguide. Thus, the temperature control of the waveguide can be further tuned.

[0083] ​In some embodiments, the lower hole 404 is directly below the semiconductor waveguide layer 108. The lower hole 404 is defined by the bottom surface 108a of the semiconductor waveguide layer 108 and one or more surfaces of the base dielectric layer 104. The lower hole 404 is directly below the ridge portion 112 and is filled with air or a similar substance. The lower hole 404 can be formed below the waveguide to adjust the heat capacity of the area below the ridge portion 112. Thus, the temperature control of the waveguide can be further tuned.

[0084] In some embodiments, the heater is formed by a single damascene process, in which the heater contacts 118, 120 are formed separately from the heater line 122. In some such embodiments, the heater contacts 118, 120 can comprise a different conductive material than the heater line 122.

[0085] Figure 5 A cross-sectional view 500 of some embodiments of a photonic integrated die is shown, in which an active device is disposed on a waveguide. Figure 1

[0086] The active device is formed by a first doped region 502 having a first doping type (e.g., p-type), and a second doped region 504 having a second doping type (e.g., n-type) different from the first doping type. In some embodiments, the active device is further formed by an intrinsic region 506 between the first doped region 502 and the second doped region 504. The first doped region 502, the second doped region 504, and the intrinsic region 506 form a p-i-n junction in the semiconductor waveguide layer 108. The p-i-n junction can convert an optical signal traveling through the waveguide into an electrical signal.

[0087] The intrinsic region 506 is located in the ridge portion 112 and in the base portion 110 directly below the ridge portion 112. The first doped region 502 and the second doped region 504 are located in the base portion 110 on opposite sides of the intrinsic region 506. In some embodiments, a first contact region 508 having the first doping type is located in the first doped region 502, and a second contact region 510 having the second doping type is located in the second doped region 504. The contact regions 508, 510 have a higher doping concentration than their corresponding doped regions 502, 504 to reduce the contact resistance between the heater contacts 118, 120 and the semiconductor waveguide layer 108.

[0088] ​To prevent an electrical short circuit between the first doped region 502 and the second doped region 504 of the active device, the heater line 122 includes two separate conductive lines 512 and 514. The first conductive line 512 and the second conductive line 514 are laterally spaced and electrically isolated. A dielectric structure 114 is located directly between the conductive lines 512 and 514. In some embodiments, the spacing between the conductive lines 512 and 514 is laterally offset from the ridge portion 112 (e.g., not directly above the ridge portion 112), such that the heater line 122 extends directly to the entire area of ​​the top of the ridge portion 112 to maintain temperature control of the ridge portion 112.

[0089] Figure 6 Show Figure 1 A cross-sectional view 600 of some embodiments of the photonic integrated die, wherein the barrier layer 602 is located directly between the heater and the ridge portion 112.

[0090] The barrier layer 602 lined the inner sidewalls (e.g., sidewalls 118a, 120a) of the heater contacts 118, 120 and the bottom surface 122a of the heater line 122. The barrier layer 602 was included in the integrated die to reduce the likelihood of electromigration of the heater contacts 118, 120 and / or the heater line 122 toward the ridge portion 112 (e.g., preventing the distance between the heater and the ridge portion 112 from being shortened). Therefore, the possibility of heater-induced optical loss due to the shortening of the distance between the heater and the waveguide over time due to electromigration can be reduced.

[0091] In some embodiments, multiple conductive interconnect structures are located on and coupled to the heater. For example, conductive vias 604 and 606 are located on heater line 122, and conductive lines 608 and 610 are located on conductive vias 604 and 606, respectively. Current can flow from one line / via (e.g., line 608 and via 604) through the heater to another via / line (e.g., via 606 and line 610).

[0092] Figure 7 Show Figure 1 Cross-sectional view 700 of some embodiments of photonic integrated chips, wherein a semiconductor waveguide layer 108 forms a micro-ring modulator 806, and Figure 8 A top view 800 is shown. In some embodiments, Figure 7 The cross-sectional view 700 is along Figure 8 The B-B' line is cut off. To clearly illustrate the lower layer, heater line 122 is shown below. Figure 8 The middle part is represented by a "dashed line". Figure 8 The dielectric structure 114, the basic dielectric layer 104, and the basic semiconductor layer 102 are not shown.

[0093] The ridge portion 112 extends into a closed ring. The base portion 110 encircles the ring. The first heater contacts 118 and the second heater contacts 120 contact the base portion 110 outside the ring. The third heater contacts 702 contact the base portion 110 inside the ring encircling the center of the ring. The heater line 122 extends across the ring and is coupled to the heater contacts 118, 120, 702. The micro-ring modulator modulates an optical signal passing through the adjacent waveguides 802, 804.

[0094] Figure 9 A cross-sectional view 900 of some embodiments of a photonic integrated die is shown, and Figure 1 a top view 1000 thereof is shown, in which the semiconductor waveguide layer 108 forms a Mach-Zehnder modulator. In some embodiments, Figure 10 the cross-sectional view 900 is taken along line C-C’ of Figure 9 the photonic integrated die 100. To clearly show the underlying layers, the heater line 122 and the heater line 914 are represented in “dashed lines” in Figure 10 . Figure 9 The dielectric structure 114, the base dielectric layer 104, and the base semiconductor layer 102 are not shown in Figure 9 .

[0095] The waveguides have a second ridge portion 906, separate from the ridge portion 112. The ridge portions 112, 906 extend to be between the first splitter 902 and the second splitter 904. The ridge portions are separated from each other at the splitters 902, 904. A second heater is located above the second ridge portion 906. The heater is located above a heater section of the modulator for tuning the operation of the modulator. Adjacent to the heater section of the modulator is a phase shifter section of the modulator, in which high speed modulation can occur. The second heater is formed by a third heater contact 910, a fourth heater contact 912, and a second heater line 914. The second heater is spaced apart from the first heater. For example, the second heater line 914 is spaced apart from the heater line 122, and the heater contacts 910, 912 are spaced apart from the heater contacts 118, 120. The second heater is electrically isolated from the first heater, so that each heater can be independently controlled. Thus, the temperature of each ridge portion in the modulator can be tuned separately. In this way, control over the performance of the modulator can be improved.

[0096] Figures 11 to 26 A cross-sectional view 1100-2600 of some embodiments of a method of forming a photonic integrated die including a heater located above and in contact with a waveguide is shown. While Figures 11 to 26This pertains to a particular method, but it should be understood that... Figures 11 to 26 The disclosed structure is not limited to the method described, but can be considered as a separate structure independent of the method.

[0097] like Figure 11 As shown in cross-sectional view 1100, a base semiconductor layer 102, a base dielectric layer, and a semiconductor waveguide layer 108 are provided. In some embodiments, the base semiconductor layer 102, the base dielectric layer 104, and the semiconductor waveguide layer 108 are semiconductor-on-insulator (SOI) substrates.

[0098] like Figure 12 As shown in cross-sectional Figure 1200, in some embodiments, a lower via 404 is formed in a base dielectric layer 104 beneath the semiconductor waveguide layer 108. In some embodiments, the lower via 404 is formed by etching the base dielectric layer 104 before the semiconductor waveguide layer 108 is formed on the base dielectric layer 104. In some other embodiments, forming the lower via 404 includes forming a sacrificial layer (not shown) in the base dielectric layer 104 and removing the sacrificial layer after the semiconductor waveguide layer 108 is formed on the base dielectric layer 104. Figures 13-26 The lower hole 404 is not shown.

[0099] like Figure 13 As shown in cross-sectional view 1300, the semiconductor waveguide layer 108 is etched to form a waveguide from the semiconductor waveguide layer 108. In some embodiments, a first shielding layer 1302 is formed on the semiconductor waveguide layer 108, and the semiconductor waveguide layer 108 is etched using a first etching process according to the first shielding layer 1302 to define a ridge portion 112 and a base portion 110. Furthermore, after the first etching process, a second shielding layer 1304 is formed on the semiconductor waveguide layer 108, and the semiconductor waveguide layer 108 is etched using a second etching process according to the second shielding layer 1304 to further define the base portion 110.

[0100] In some embodiments, the first shielding layer 1302 and the second shielding layer 1304 comprise photoresist or other suitable materials. In some embodiments, the first etching process and the second etching process comprise dry etching processes, such as plasma etching, reactive ion etching, ion beam etching, or other suitable processes.

[0101] like Figure 14As shown in cross-sectional Figure 1400, in some embodiments, the semiconductor waveguide layer 108 is doped to form a first doped region 302, a second doped region 304, and a third doped region 306 within the semiconductor waveguide layer 108. In some embodiments, one or more intrinsic regions (e.g., intrinsic regions 1402, 1404) remain in the semiconductor waveguide layer 108 after doping. In other embodiments, the second doped region 304 and the third doped region 306 extend in opposite directions from the first doped region 302 to the outermost wall of the semiconductor waveguide layer 108.

[0102] In some embodiments, the first doped region 302 is formed by forming a shielding layer (not shown) on the base portion 110 and performing a doping process, such as ion implantation or some other suitable process, while the shielding layer is in place. In some embodiments, the second doped region 304 and the third doped region 306 are formed by forming a shielding layer (not shown) on the ridge portion 112 and a portion of the base portion 110 and performing a doping process while the shielding layer is in place.

[0103] In some embodiments, the first doped region 302, the second doped region 304, and the third doped region 306 have the same doping type. Furthermore, the second doped region 304 and the third doped region 306 have a higher doping concentration than the first doped region 302.

[0104] In some other embodiments, the semiconductor waveguide layer 108 is doped to form active devices along the semiconductor waveguide layer 108. For example, pin devices are formed in the semiconductor waveguide layer 108, wherein the active devices are located in the intrinsic region (e.g., Figure 5 A first doped region (e.g., p-type) having a first doping type (e.g., p-type) is formed on the opposite side of the intrinsic region 506. Figure 5 The doped region 502), and the second doped region having a second doped type (e.g., n-type) different from the first doped type. Figure 5 (504) doped region.

[0105] Figures 15 to 21 Cross-sectional views 1500 to 2100 show some embodiments of a method for forming a heater on a waveguide. Figures 15 to 21 The method shown can be called a single mosaicking method.

[0106] like Figure 15 As shown in the cross-sectional view 1500, a first etch stop layer 320 is deposited over the semiconductor waveguide layer 108, a first dielectric layer 322 is deposited on the first etch stop layer 320, and a second etch stop layer 324 is deposited on the first dielectric layer 322.

[0107] In some embodiments, the first etch stop layer 320 and the second etch stop layer 324 comprise silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, or other suitable materials, and are deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. In some embodiments, the first dielectric layer 322 comprises silicon dioxide, silicon nitride, or other suitable materials, and is deposited using CVD, PVD, ALD, or other suitable processes. In some embodiments, the first etch stop layer 320 is omitted, and the first dielectric layer 322 is deposited directly on the semiconductor waveguide layer 108.

[0108] like Figure 16 As shown in cross-sectional view 1600, the second etch stop layer 324, the first dielectric layer 322, and the first etch stop layer 320 are etched to form a first opening 1602 and a second opening 1604 in the second etch stop layer 324, the first dielectric layer 322, and the first etch stop layer 320. The first opening 1602 and the second opening 1604 expose portions of the base portion 110 located on opposite sides of the ridge portion 112 (e.g., where the second and third doped regions 304 and 306 are located).

[0109] In some embodiments, a shielding layer 1606 is formed on the second etch stop layer 324, and etching is performed based on the shielding layer 1606. In some embodiments, the shielding layer 1606 comprises photoresist or some other suitable material. In some embodiments, the etching comprises dry etching or some other suitable process.

[0110] like Figure 17 As shown in cross-sectional view 1700, a first heater contact 118 is formed in a first opening 1602, and a second heater contact 120 is formed in a second opening 1604. The first heater contact 118 and the second heater contact 120 respectively contact the base portion 110 of the semiconductor waveguide layer 108 located on opposite sides of the ridge portion 112 (e.g., located at the second doped region 304 and the third doped region 306, respectively).

[0111] In some embodiments, the first heater contact 118 and the second heater contact 120 are formed by depositing a conductive material (e.g., copper, aluminum, titanium nitride, tungsten, or some other suitable material) on the second etch stop layer 324 and in the first opening 1602 and the second opening 1604, and performing a planarization process (e.g., chemical mechanical planarization (CMP), full etch-back process, or some suitable process) to remove the conductive material from the second etch stop layer 324, thus forming the heater contacts 118, 120 from the conductive material.

[0112] likeFigure 18 A second dielectric layer 326 is deposited on the second etch stop layer 324, as shown in cross-sectional view 1800. In some embodiments, the second dielectric layer 326 includes silicon dioxide, silicon nitride, or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0113] As shown in cross-sectional view 1900, the second dielectric layer 326 is etched to form an opening 1902. The opening 1902 exposes a top surface of the heater contacts 118, 120. In some embodiments, a masking layer 1904 is formed on the second dielectric layer 326, and the etching is performed according to the masking layer 1904. In some embodiments, the masking layer 1904 includes photoresist or some other suitable material. In some embodiments, the etching includes a dry etching or some other suitable process. Figure 19 As shown in cross-sectional view 2000, a heater line 122 is formed in the opening 1902. The heater line 122 is coupled to the heater contacts 118, 120. In some embodiments, the heater line 122 is formed by depositing a conductive material (e.g., copper, aluminum, titanium nitride, tungsten, or some other suitable material) on the second dielectric layer 326 and in the opening 1902, and performing a planarization process to remove the conductive material on the second dielectric layer 326, thus forming the heater line 122 from the conductive material.

[0114] Figure 20 In some embodiments, in which the active device is formed along the waveguide, the heater line 122 includes two separate conductive lines (e.g., the conductive lines 512, 514 of FIG. 5) to prevent electrical shorting between the opposite doped regions in the active device. In these embodiments, the etching forms two separate openings to form the two separate conductive lines, the conductive material is deposited in the separate openings, and a planarization is performed to form the separate conductive lines from the conductive material, as shown in cross-sectional view 2000.

[0115] In some embodiments, in which the active device is formed along the waveguide, the heater line 122 includes two separate conductive lines (e.g., the conductive lines 512, 514 of FIG. 5) to prevent electrical shorting between the opposite doped regions in the active device. In these embodiments, the etching forms two separate openings to form the two separate conductive lines, the conductive material is deposited in the separate openings, and a planarization is performed to form the separate conductive lines from the conductive material, as shown in cross-sectional view 2000. Figure 5 Figure 19 In some embodiments, in which the active device is formed along the waveguide, the heater line 122 includes two separate conductive lines (e.g., the conductive lines 512, 514 of FIG. 5) to prevent electrical shorting between the opposite doped regions in the active device. In these embodiments, the etching forms two separate openings to form the two separate conductive lines, the conductive material is deposited in the separate openings, and a planarization is performed to form the separate conductive lines from the conductive material, as shown in cross-sectional view 2000.

[0116] As shown in cross-sectional view 2100, in some embodiments, the upper hole 402 is formed between the ridge portion 112 and the heater line 122, and between the ridge portion 112 and the heater contacts 118, 120. In some embodiments, forming the upper hole 402 includes forming a sacrificial layer (not shown) on the semiconductor waveguide layer 108 (e.g., on the first etch stop layer 320 at the ridge portion 112), and removing the sacrificial layer after the heater line 122 is formed on the heater contacts 118, 120. In some embodiments, the first etch stop layer 320 and the second etch stop layer 324 further define the upper hole 402. Figure 21

[0117] Figures 22 to 26 ​​​Cross-sectional views 2200 to 2600 show another embodiment of a method for forming a heater on a waveguide. Figures 22 to 26 The method shown can be called the double mosaicking method.

[0118] like Figure 22 As shown in cross-sectional view 2200, a first etch stop layer 320 covers the semiconductor waveguide layer 108, a first dielectric layer 322 is deposited on the first etch stop layer 320, a second etch stop layer 324 is deposited on the first dielectric layer, and a second dielectric layer 326 is deposited on the second etch stop layer 324.

[0119] like Figure 23 As shown in cross-sectional view 2300, the second dielectric layer 326 is etched to form an opening 2302 in the second dielectric layer 326. In some embodiments, a shielding layer 2304 is formed on the second dielectric layer 326, and etching is performed on the shielding layer 2304. In some embodiments, the shielding layer 2304 comprises photoresist or some other suitable material. In some embodiments, the etching comprises dry etching or some other suitable process.

[0120] like Figure 24 As shown in cross-sectional view 2400, the second etch stop layer 324, the first dielectric layer 322, and the first etch stop layer 320 are etched to form a first opening 2402 and a second opening 2404 in the second etch stop layer 324, the first dielectric layer 322, and the first etch stop layer 320. The second opening 2402 and the third opening 2302 extend from the opening 2302 to the base portion 110 of the semiconductor waveguide layer 108 and expose a portion of the base portion 110.

[0121] In some embodiments, a shielding layer 2406 is formed on the second etch stop layer 324, and etching is performed based on the shielding layer 2406. In some embodiments, the shielding layer 2406 comprises photoresist or other suitable material. In some embodiments, the etching comprises dry etching or other suitable processes.

[0122] like Figure 25 As shown in cross-sectional view 2500, heater contacts 118 and 120 are formed in openings 2402 and 2404, and heater line 122 is formed in opening 2302. In some embodiments, heater contacts 118 and 120 and heater line 122 are formed by depositing a conductive material (e.g., copper, aluminum, titanium nitride, tungsten, or some other suitable material) on the second dielectric layer 326 and in openings 2402, 2404, and 2302, and performing a planarization process to remove the conductive material from the second dielectric layer 326, thus forming heater contacts 118 and 120 and heater line 122 from the conductive material.

[0123] In some embodiments, where the active device is configured along the waveguide, the heater line 122 includes two separate conductive lines (e.g., Figure 5 Conductive lines 512, 514 are used to prevent electrical short circuits between relatively doped regions of the active device. In these embodiments, Figure 23 The etching shown creates two separate openings for two separate conductive lines.

[0124] like Figure 26 As shown in cross-sectional view 2600, in some embodiments, an upper aperture 402 is formed between the ridge portion 112 and the heater line 122, and between the ridge portion 112 and the heater contacts 118, 120. In some embodiments, forming the upper aperture 402 includes forming a sacrificial layer (not shown) on the semiconductor waveguide layer 108, and removing the sacrificial layer after forming the heater contacts 118, 120 and the heater line 122.

[0125] Figure 27 Flowcharts illustrating some embodiments of a method 2700 for forming a photonic integrated die, including a heater located above and in contact with the waveguide. While method 2700 is shown and described below as a series of actions or events, it should be understood that the order of these actions or events shown should not be construed as limiting. For example, some actions may occur in a different order than those shown and / or described herein and / or simultaneously with other actions or events. Furthermore, not all actions shown are necessary to realize one or more aspects or embodiments described herein. Additionally, one or more actions depicted herein may be implemented in one or more separate actions and / or stages.

[0126] In block 2702, the semiconductor waveguide layer is etched to form a waveguide. After etching, the ridge portion of the semiconductor waveguide layer protrudes upward from the base portion of the semiconductor waveguide layer. Figure 13 Cross-sectional view 1300 is shown for some embodiments corresponding to block 2702.

[0127] In block 2704, a dielectric structure is formed above the semiconductor waveguide layer. Figure 15 , Figure 18 and Figure 22 Cross-sectional views 1500, 1800 and 2200 are shown for some embodiments corresponding to block 2704.

[0128] In block 2706, a heater contact is formed in the dielectric structure, and the heater contact is located directly above the base portion of the semiconductor waveguide layer. The heater contact contacts the base portion of the semiconductor waveguide layer and is located on the opposite side of the ridge portion of the semiconductor waveguide layer. Figure 17 and Figure 25Cross-sectional views 1700 and 2500 are shown, respectively, corresponding to some embodiments of block 2706.

[0129] In block 2708, a heater line is formed in the dielectric structure, the heater line being positioned directly above the ridge portion of the semiconductor waveguide layer. The heater line extends from a first heater contact to a second heater contact. Figure 20 and Figure 25 Cross-sectional views 2000 and 2500 are shown, respectively, corresponding to some embodiments of block 2708.

[0130] Accordingly, the present subject matter relates to a heater positioned above a semiconductor waveguide and in contact with the semiconductor waveguide on opposite sides of a ridge portion of the semiconductor waveguide to improve control over the temperature of the waveguide.

[0131] Accordingly, in some embodiments, the present subject matter relates to an integrated die including a substrate, a semiconductor waveguide layer, an electrically conductive heater line, a first heater contact, and a second heater contact. The semiconductor waveguide layer is positioned above the substrate. A base portion of the semiconductor waveguide layer extends laterally above the substrate. A ridge portion of the semiconductor waveguide layer protrudes upwardly from the base portion. The electrically conductive heater line is spaced above the ridge portion of the semiconductor waveguide layer. The first heater contact and the second heater contact extend from the electrically conductive heater line to the base portion of the semiconductor waveguide layer on opposite sides of the ridge portion of the semiconductor waveguide layer.

[0132] In some embodiments, the semiconductor waveguide layer includes a first doped region having a first doping type in the base portion of the semiconductor waveguide layer, wherein the semiconductor waveguide layer includes a second doped region having the first doping type in the base portion of the semiconductor waveguide layer, wherein the first heater contact contacts the first doped region, and wherein the second heater contact contacts the second doped region. In some embodiments, the semiconductor waveguide layer includes a third doped region having the first doping type in a ridge portion of the semiconductor waveguide layer, the third doped region being directly between the first doped region and the second doped region, wherein a doping concentration of the first doped region and a doping concentration of the second doped region are greater than a doping concentration of the third doped region. In some embodiments, the base portion is defined by a first upper surface, a second upper surface, a first sidewall, and a second sidewall of the semiconductor waveguide layer, wherein the ridge portion is defined by a top surface, a third sidewall, and a fourth sidewall of the semiconductor waveguide layer, wherein the third sidewall is laterally spaced apart from the first heater contact, wherein the fourth sidewall is laterally spaced apart from the second heater contact, and wherein the top surface is vertically spaced apart from the electrically conductive heater line. In some embodiments, further comprising: a dielectric layer directly between the top surface of the semiconductor waveguide layer and the electrically conductive heater line, directly between the third sidewall of the semiconductor waveguide layer and the first heater contact, and directly between the fourth sidewall of the semiconductor waveguide layer and the second heater contact. In some embodiments, an air-filled void is directly between the top surface of the semiconductor waveguide layer and the electrically conductive heater line, directly between the third sidewall of the semiconductor waveguide layer and the first heater contact, and directly between the fourth sidewall of the semiconductor waveguide layer and the second heater contact. In some embodiments, the top surface, the third sidewall, the fourth sidewall, the first upper surface, and the second upper surface of the semiconductor waveguide layer define the void, wherein a sidewall of the first heater contact, a sidewall of the second heater contact, and a lower surface of the electrically conductive heater line further define the void. In some embodiments, a bottom surface of the semiconductor waveguide layer and one or more surfaces of the substrate define a void directly below the ridge portion of the semiconductor waveguide layer.In some embodiments, the ridge portion of the semiconductor waveguide layer extends into a closed loop, with the first heater contact and the second heater contact contacting the base portion outside of the closed loop, the integrated die further comprising: a third heater contact extending from the electrically conductive heater line to the base portion of the semiconductor waveguide layer, with the third heater contact contacting the base portion inside of the closed loop, with the third heater contact directly between the first heater contact and the second heater contact. In some embodiments, the ridge portion is a first ridge portion, with the electrically conductive heater line being a first electrically conductive heater line, and with a second ridge portion of the semiconductor waveguide layer protruding upward from the base portion and laterally spaced apart from the first ridge portion, the integrated die further comprising: a second electrically conductive heater line spaced apart above the second ridge portion of the semiconductor waveguide layer; and third and fourth heater contacts extending from the second electrically conductive heater line to the base portion of the semiconductor waveguide layer on opposite sides of the second ridge portion of the semiconductor waveguide layer.

[0133] In other embodiments, the present inventive subject matter is directed to an integrated die comprising a substrate, a semiconductor waveguide layer, a dielectric structure, a first heater contact, a second heater contact, and an electrically conductive heater line. The semiconductor waveguide layer is above the substrate. The dielectric structure is above the semiconductor waveguide layer. The first heater contact and the second heater contact are above the semiconductor waveguide layer. A ridge portion of the semiconductor waveguide layer protrudes upward from a base portion of the semiconductor waveguide layer directly between the first heater contact and the second heater contact. The electrically conductive heater line extends onto the dielectric structure directly above the ridge portion of the semiconductor waveguide layer and between the first heater contact and the second heater contact. The first heater contact and the second heater contact extend through the dielectric structure and contact the base portion of the semiconductor waveguide layer.

[0134] In some embodiments, the ridge portion of the semiconductor waveguide layer is laterally spaced apart from the first heater contact in a first direction, laterally spaced apart from the second heater contact in a second direction, and vertically spaced apart from the electrically conductive heater line. In some embodiments, the semiconductor waveguide layer includes a first doped region having a first doping type in the base portion of the semiconductor waveguide layer and coupled to the first heater contact, wherein the semiconductor waveguide layer includes a second doped region having a second doping type different from the first doping type in the base portion of the semiconductor waveguide layer and coupled to the second heater contact, wherein the electrically conductive heater line includes a first electrically conductive line and a second electrically conductive line spaced apart from and electrically isolated from the first electrically conductive line, the first electrically conductive line connected to the first heater contact, and the second electrically conductive line connected to the second heater contact. In some embodiments, the electrically conductive heater line extends continuously from the first heater contact to the second heater contact. In some embodiments, further comprising a barrier layer extending along sidewalls of the first heater contact, extending under a surface of the electrically conductive heater line, and extending along sidewalls of the second heater contact, the barrier layer directly between the first heater contact and the ridge portion, directly between the second heater contact and the ridge portion, and directly between the electrically conductive heater line and the ridge portion. In some embodiments, the ridge portion, the first heater contact, the second heater contact, and the electrically conductive heater line extend in a common direction.

[0135] In other embodiments, the present disclosure relates to a method of forming an integrated die. The method includes etching a semiconductor waveguide layer to define a base portion of the semiconductor waveguide layer that extends laterally over a substrate and to define a ridge portion of the semiconductor waveguide layer that protrudes upwardly from the base portion. Depositing one or more dielectric layers over the semiconductor waveguide layer. Etching the one or more dielectric layers to form a first opening and a second opening in the one or more dielectric layers on opposite sides of the ridge portion of the semiconductor waveguide layer. The first opening and the second opening respectively expose a first portion and a second portion of the base portion of the semiconductor waveguide layer. Etching the one or more dielectric layers to form a third opening in the one or more dielectric layers. The third opening is located above the first and second openings and directly above the ridge portion of the semiconductor waveguide layer. Depositing an electrically conductive material in the first and second openings to form a first heater contact in the first opening and a second heater contact in the second opening. Depositing the electrically conductive material in the third opening to form an electrically conductive heater line in the third opening and over the first and second heater contacts.

[0136] In some embodiments, further comprising: doping a first doped region in the base portion of the semiconductor waveguide layer, the first doped region having a first doping type; forming a second doped region in the base portion of the semiconductor waveguide layer, the second doped region having the first doping type; and forming a third doped region in the ridge portion of the semiconductor waveguide layer, the third doped region being directly between the first doped region and the second doped region, wherein a doping concentration of the first doped region and a doping concentration of the second doped region are greater than a doping concentration of the third doped region, wherein the first opening and the second opening are formed directly over the first doped region and the second doped region, respectively. In some embodiments, further comprising: forming a void directly below the ridge portion of the semiconductor waveguide layer, the void being defined by a bottom surface of the semiconductor waveguide layer and one or more surfaces of the substrate. In some embodiments, further comprising: forming a void between the ridge portion and the electrically conductive heater wire and between the ridge portion and the first and second heater contacts.

[0137] The foregoing outlines features of a number of embodiments so that a technical person in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same results as the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated die, comprising: comprises: a substrate; a semiconductor waveguide layer over the substrate, a base portion of the semiconductor waveguide layer extending laterally over the substrate, and a ridge portion of the semiconductor waveguide layer protruding upwardly from the base portion; a conductive heater line spaced above the ridge portion of the semiconductor waveguide layer; and a first heater contact and a second heater contact extending from the conductive heater line to the base portion of the semiconductor waveguide layer on opposite sides of the ridge portion of the semiconductor waveguide layer. the semiconductor waveguide layer includes a first doped region in the base portion of the semiconductor waveguide layer having a first doping type, wherein the semiconductor waveguide layer includes a second doped region in the base portion of the semiconductor waveguide layer having the first doping type, wherein the first heater contact contacts the first doped region, and wherein the second heater contact contacts the second doped region.

2. The integrated die of claim 1, wherein, the base portion is defined by a first upper surface, a second upper surface, a first sidewall, and a second sidewall of the semiconductor waveguide layer, wherein the ridge portion is defined by a top surface, a third sidewall, and a fourth sidewall of the semiconductor waveguide layer, wherein the third sidewall is laterally spaced from the first heater contact, wherein the fourth sidewall is laterally spaced from the second heater contact, and wherein the top surface is vertically spaced from the conductive heater line.

3. The integrated die of claim 1, wherein, a bottom surface of the semiconductor waveguide layer and one or more surfaces of the substrate define a hole directly below the ridge portion of the semiconductor waveguide layer.

4. The integrated die of claim 1, wherein, the ridge portion of the semiconductor waveguide layer extends into a closed loop, wherein the first heater contact and the second heater contact contact the base portion outside of the closed loop, the integrated die further comprising:

5. The integrated die of claim 1, wherein, a third heater contact extending from the conductive heater line to the base portion of the semiconductor waveguide layer, wherein the third heater contact contacts the base portion inside of the closed loop, and wherein the third heater contact is directly between the first heater contact and the second heater contact. the ridge portion is a first ridge portion, wherein the conductive heater line is a first conductive heater line, and wherein a second ridge portion of the semiconductor waveguide layer protrudes upwardly from the base portion and is laterally spaced from the first ridge portion, the integrated die further comprising:

6. The integrated die of claim 1, wherein, a second conductive heater line spaced above the second ridge portion of the semiconductor waveguide layer; and a third heater contact and a fourth heater contact extending from the second conductive heater line to the base portion of the semiconductor waveguide layer on opposite sides of the second ridge portion of the semiconductor waveguide layer. comprises:

7. An integrated die, characterized by, a substrate; a semiconductor waveguide layer over the substrate; a dielectric structure over the semiconductor waveguide layer; ​ a first heater contact and a second heater contact over the semiconductor waveguide layer, wherein a ridge portion of the semiconductor waveguide layer protrudes upward from a base portion of the semiconductor waveguide layer between the first heater contact and the second heater contact; and a conductive heater line extending along the dielectric structure, over the ridge portion of the semiconductor waveguide layer, and between the first heater contact and the second heater contact, wherein the first heater contact and the second heater contact extend through the dielectric structure and contact the base portion of the semiconductor waveguide layer.

8. The integrated die of claim 7, wherein, The ridge portion of the semiconductor waveguide layer is laterally spaced apart from the first heater contact in a first direction, laterally spaced apart from the second heater contact in a second direction, and vertically spaced apart from the conductive heater line.

9. The integrated die of claim 7, wherein, The semiconductor waveguide layer includes a first doped region having a first doping type in the base portion of the semiconductor waveguide layer and coupled to the first heater contact, wherein the semiconductor waveguide layer includes a second doped region having a second doping type different from the first doping type in the base portion of the semiconductor waveguide layer and coupled to the second heater contact, wherein the conductive heater line includes a first conductive line and a second conductive line spaced apart and electrically insulated from the first conductive line, the first conductive line connected to the first heater contact, and the second conductive line connected to the second heater contact.

10. The integrated die of claim 7, wherein, Also included are: a barrier layer extending along sidewalls of the first heater contact, under a lower surface of the conductive heater line, and along sidewalls of the second heater contact, the barrier layer directly between the first heater contact and the ridge portion, directly between the second heater contact and the ridge portion, and directly between the conductive heater line and the ridge portion.

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