Packaging structure of gallium nitride cascade device

Abstract

The utility model relates to a packaging structure of a gallium nitride cascade device, the packaging structure comprises a packaging frame, a gallium nitride chip, a low voltage enhancement chip and a plastic packaging body, the packaging frame comprises a base island used for mounting the chip, a device gate region, a device drain region and a device source region; the gallium nitride chip and the low-voltage enhanced chip are mounted on a base island of the packaging frame; the gallium nitride chip is an original gallium nitride chip or a chip obtained after electrode position transfer is carried out on the original gallium nitride chip, and the low-voltage enhancement chip is an original low-voltage enhancement chip or a chip obtained after electrode position transfer is carried out on the original low-voltage enhancement chip. According to the gallium nitride cascade device, the production cost is reduced, the packaging process flow of the gallium nitride cascade device is simplified, and the performance and the reliability of the device are improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of semiconductor technical field, and particularly to a kind of packaging structure of gallium nitride cascade device. BACKGROUND

[0002] Gallium nitride cascade device (GaN Cascode) is a kind of device structure combining gallium nitride (GaN) high electron mobility transistor (High Electron Mobility Transistors, abbreviated as HEMT) and low-voltage transistor. Low-voltage transistor, for example, field effect transistor and triode, wherein field effect transistor can be metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, abbreviated as MOS) or junction field effect transistor (Junction Field-Effect Transistor, abbreviated as JEFT). In the following description, MOS structure is taken as an example to explain. Referring to Figure 1 , Figure 1 It is a kind of electrical schematic diagram of gallium nitride cascade device in prior art. MOS drain D2 of MOS Q2 is connected with HEMT source S1 of HEMT Q1, MOS source S2 is connected with HEMT gate G1 and serves as the source S of gallium nitride cascade device, HEMT drain D1 serves as the drain D of gallium nitride cascade device, and MOS gate G2 serves as the gate G of gallium nitride cascade device. By cascading high-voltage HEMT and low-voltage MOS, the low-voltage MOS is used to provide driving interface, which avoids the high requirement of GaN device on gate drive circuit.

[0003] Among them, the chip structure of conventional low-voltage silicon-based MOS is usually that gate and source are located on the front surface of chip, and drain is located on the back surface of chip, i.e. the back surface of substrate. The chip structure of conventional HEMT is usually that gate, source and drain are located on the front surface of chip. Thus, the packaging structure of GaN Cascode in prior art is as shown in Figure 2 , Figure 2It is a device packaging structure diagram of GaN Cascode in the prior art. The device packaging of GaN Cascode in the prior art comprises a packaging frame 1, an HEMT chip U1, a MOS chip U2 and a substrate U3, the back surface of the HEMT chip U1 and the substrate U3 are fixed on the conductive area of the base island 11 of the packaging frame 1 through an insulating layer, the conductive area of the base island 11 can be used as the source S of the GaN cascode. The MOS drain D2 on the back surface of the MOS chip U2 is attached to the conductive metal area 21 on the front surface of the substrate U3 through conductive glue or the like, the conductive metal area 21 is connected to the HEMT source S1 of the HEMT chip U1 through a bonding wire, the MOS source S2 on the front surface of the MOS chip U2 is connected to the conductive area 11 of the base island of the packaging frame 1 through a bonding wire, the MOS gate G2 on the front surface of the MOS chip U2 is connected to the gate area 12 of the packaging frame 1 through a bonding wire, and the HEMT drain D1 of the HEMT chip U1 is connected to the drain area 13 of the packaging frame 1 through a bonding wire, so as to realize the electrical connection with the MOS source S2.

[0004] By Figure 2 As can be seen from the packaging structure shown in the figure, since the electrode layout structure of the MOS chip U2 does not match the electrode layout structure of the HEMT chip U1, the substrate U3 needs to be added in the packaging structure, so that the device needs to be mounted three times in the packaging process of the GaN Cascode, the cycle is long; in addition, since the substrate U3 needs to be insulated from the source area of the device, the insulating layer structure of the substrate U3 is relatively complex; moreover, there are too many solder wires in the packaging structure, the parasitic inductance / resistance is large, and thus the reliability and other performances of the GaN Cascode are reduced; in addition, the area of the substrate U3 is large, which leads to the fact that the GaN Cascode cannot adopt the traditional small packaging structure form, so that the packaging cost of the GaN Cascode is high, and the miniaturization development of the GaN Cascode is limited. Content of the utility model

[0005] In view of the technical problems existing in the prior art, the utility model provides a packaging structure of a gallium nitride cascade device, which is suitable for various packaging modes and can improve the performance of the gallium nitride cascade device.

[0006] In order to solve the above technical problems, according to one aspect of the utility model, the utility model provides a packaging structure of a gallium nitride cascade device, which comprises:

[0007] A packaging frame, the packaging frame comprises a base island for attaching a chip, a device gate area, a device drain area and a device source area;

[0008] A gallium nitride chip;

[0009] low-voltage enhancement chip; and

[0010] plastic package body;

[0011] wherein the gallium nitride chip and the low-voltage enhancement chip are mounted on a base island of the package frame; the gallium nitride chip is a raw gallium nitride chip or a chip obtained by electrode position transfer on a raw gallium nitride chip, and the low-voltage enhancement chip is a raw low-voltage enhancement chip or a chip obtained by electrode position transfer on a raw low-voltage enhancement chip.

[0012] the drain of the gallium nitride chip and a device drain region of the package frame are electrically connected; the gate of the gallium nitride chip and a device source region of the package frame are electrically connected; the gate of the low-voltage enhancement chip and a device gate region of the package frame are electrically connected; and the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are electrically connected.

[0013] Optionally, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the same surface of the respective chip; the gallium nitride chip and the low-voltage enhancement chip are mounted side by side on the base island of the package frame; when the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the front surface of the respective chip, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are electrically connected by a metal connecting member; and when the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the back surface of the respective chip, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are respectively in contact with a conductive region on the base island for electrical connection.

[0014] Optionally, the gallium nitride chip is a raw gallium nitride chip, the drain, the source and the gate of which are distributed on the front surface of the chip; the low-voltage enhancement chip is a chip obtained by electrode position transfer on a raw low-voltage enhancement chip, the drain and the gate of which are distributed on the front surface of the chip, and the source of which is distributed on the back surface of the chip; the source of the low-voltage enhancement chip is in contact with a conductive region on the base island for electrical connection; and the gate of the gallium nitride chip and the conductive region on the base island are electrically connected by a metal connecting member.

[0015] Optionally, the gallium nitride chip is a raw gallium nitride chip, the drain, the source and the gate of which are distributed on the front surface of the chip; the low-voltage enhancement chip is a chip obtained by electrode position transfer on a raw low-voltage enhancement chip, the source, the drain and the gate of which are distributed on the front surface of the chip; the gate of the gallium nitride chip and a conductive region on the base island are electrically connected by a metal connecting member; and the source of the low-voltage enhancement chip and the conductive region on the base island are electrically connected by a metal connecting member.

[0016] Preferably, the low-voltage enhancement chip is an original low-voltage enhancement chip, the drain of which is distributed on the back of the chip, and the source and the gate are distributed on the front of the chip; the gallium nitride chip is a chip obtained by transferring the electrode positions of an original gallium nitride chip, the gate and the drain of the gallium nitride chip being located on the front of the chip, and the source being located on the back of the chip; the drain on the back of the low-voltage enhancement chip and the source of the gallium nitride chip are respectively in contact with the conductive region on the base island and are electrically connected; the source on the back of the low-voltage enhancement chip and the gate of the gallium nitride chip are respectively electrically connected with the device source region through the metal connecting member.

[0017] Preferably, the gallium nitride chip is a chip obtained by transferring the electrode positions of an original gallium nitride chip, the drain, the source and the gate of the original gallium nitride chip being distributed on the front of the chip, and the drain and the source of the gallium nitride chip obtained by transferring the electrode positions being located on the front of the chip, and the gate being located on the back of the chip; the low-voltage enhancement chip is a chip obtained by transferring the electrode positions of an original low-voltage enhancement chip, the drain of the original low-voltage enhancement chip being distributed on the back of the chip, and the source and the gate being distributed on the front of the chip, and the drain and the gate of the low-voltage enhancement chip obtained by transferring the electrode positions being located on the front of the chip; the gate of the gallium nitride chip is in contact with the conductive region on the base island and is electrically connected; the drain of the low-voltage enhancement chip and the source of the gallium nitride chip are electrically connected through the metal connecting member.

[0018] Preferably, the source, the drain and the gate of the low-voltage enhancement chip obtained by transferring the electrode positions are all located on the front of the chip, and the source of the low-voltage enhancement chip and the conductive region on the base island are electrically connected through the metal connecting member.

[0019] Preferably, the source of the low-voltage enhancement chip obtained by transferring the electrode positions is located on the back of the chip, and the source of the low-voltage enhancement chip is in contact with the conductive region on the base island and is electrically connected.

[0020] Preferably, the gallium nitride chip is a chip obtained by transferring the electrode positions of an original gallium nitride chip, the drain, the source and the gate of the original gallium nitride chip being distributed on the front of the chip, and the drain and the gate of the gallium nitride chip obtained by transferring the electrode positions being located on the front of the chip, and the source being located on the back of the chip; the low-voltage enhancement chip is a chip obtained by transferring the electrode positions of an original low-voltage enhancement chip, the drain, the source and the gate of the original low-voltage enhancement chip being distributed on the front of the chip, and the drain, the source and the gate of the low-voltage enhancement chip obtained by transferring the electrode positions being located on the front of the chip; the gate of the gallium nitride chip is electrically connected with the device source region through the metal connecting member, the drain of the low-voltage enhancement chip is electrically connected with the conductive region on the base island through the metal connecting member, and the source of the low-voltage enhancement chip is electrically connected with the device source region through the metal connecting member.

[0021] Preferably, the metal connecting member is a bonding wire for a wire bonding process, a metal strip for a ribbon bonding process or a metal sheet for a compression bonding process.

[0022] Preferably, the target chip after electrode position transfer includes an original chip, a rewiring layer and a secondary encapsulation body, the original chip and the rewiring layer are located in the secondary encapsulation body; the rewiring layer re-arranges the target electrode from an original position to a preset position; the target electrode is one or more of a drain electrode, a source electrode and a gate electrode, and the target chip is an original gallium nitride chip and / or an original low-voltage enhancement chip.

[0023] Preferably, the secondary encapsulation body is provided with an electrode hole, the rewiring layer includes a first rewiring layer and a second rewiring layer, the first rewiring layer is in communication with an electrode surface of the target electrode at the preset position and the electrode hole, and the second rewiring layer is in communication with an electrode surface of the target electrode at the original position and the electrode hole, and the original position and the preset position of the target electrode are located on the front surface and the back surface of the chip.

[0024] Preferably, the electrode surface of the target electrode at the original position and the preset position is located on the same surface of the chip, and the rewiring layer is obtained by using a ball planting or electroplating metal column between the original position and the preset position of the target electrode.

[0025] Preferably, the rewiring layer located in the secondary encapsulation body is staggered with an electrode surface of the secondary encapsulation body, and the electrode surface of the secondary encapsulation body is a drain electrode, a source electrode or a gate electrode.

[0026] Preferably, the gallium nitride chip is a chip obtained after electrode position transfer of an original gallium nitride chip, a gallium nitride gate electrode is located on the back surface of the chip, and a gallium nitride drain electrode and a gallium nitride source electrode are located on the front surface of the chip; the low-voltage enhancement chip is an original chip, a source electrode and a gate electrode of the low-voltage enhancement chip are located on the front surface of the chip, and a drain electrode is located on the back surface of the chip.

[0027] The gallium nitride chip is attached to a conductive area of the base island, and a gallium nitride gate electrode on the back surface of the gallium nitride chip is electrically connected to the conductive area of the base island; the low-voltage enhancement chip is attached to a gallium nitride source electrode surface, and a drain electrode on the back surface of the low-voltage enhancement chip is electrically connected to the gallium nitride source electrode surface.

[0028] The utility model discloses a MOS chip and / or HEMT chip's electrode position transfer to the electrode layout position of the transformation, reduced the quantity of soldering wire, can also cancel the large substrate used in the packaging to adapt to small packaging structure, both reduce the cost, also simplify the packaging process flow of gallium nitride cascade device, improve the performance of device, improve the reliability of device. BRIEF DESCRIPTION OF DRAWINGS

[0029] Below, the preferred implementation of the utility model will be further detailed by combining with the drawings, wherein:

[0030] Figure 1 It is a gallium nitride cascade device's electrical schematic diagram in prior art.

[0031] Figure 2 is a device packaging structure schematic diagram of GaN Cascode in the prior art;

[0032] Figure 3 is a device packaging structure schematic diagram of GaN Cascode according to an embodiment of the present application;

[0033] Figure 4 is a GaN Cascode packaging method flow chart according to an embodiment of the present application;

[0034] Figure 5 is a side structure schematic diagram of the device packaging structure of GaN Cascode after completing patching and interconnection according to an embodiment of the present application;

[0035] Figure 6 is a MOS chip structure schematic diagram in the process of electrode position transfer of the MOS chip according to an embodiment of the present application;

[0036] Figure 7 is a chip structure cross section schematic diagram obtained after electrode position transfer of the original MOS chip according to another embodiment of the present application;

[0037] Figure 8 is a device packaging structure schematic diagram of GaN Cascode according to an embodiment of the present application;

[0038] Figure 9 is a MOS chip structure schematic diagram in the process of electrode position transfer of the MOS chip according to another embodiment of the present application;

[0039] Figure 10 is a device packaging structure schematic diagram of GaN Cascode according to an embodiment of the present application;

[0040] Figure 11 is a chip structure cross section schematic diagram obtained after electrode position transfer of the HEMT chip according to an embodiment of the present application;

[0041] Figure 12 is a device packaging structure schematic diagram of GaN Cascode according to an embodiment of the present application;

[0042] Figure 13 is a chip structure cross section schematic diagram obtained after electrode position transfer of the HEMT chip according to another embodiment of the present application;

[0043] Figure 14It is a device packaging structure schematic diagram of GaN Cascode according to the embodiment five of the utility model;

[0044] Figure 15 It is a device packaging structure schematic diagram of GaN Cascode according to the embodiment six of the utility model;

[0045] Figure 16 It is a device packaging structure schematic diagram of GaN Cascode according to the embodiment seven of the utility model;And

[0046] Figure 17 It is a device packaging structure schematic diagram of GaN Cascode according to the embodiment eight of the utility model. DETAILED DESCRIPTION

[0047] To make the purpose, technical scheme and advantages of the utility model embodiment more clear, the technical scheme in the utility model embodiment will be described clearly and completely in the following with the drawings in the utility model embodiment, obviously, the described embodiment is a part of the embodiment of the utility model, not all the embodiment.Based on the embodiment in the utility model, all other embodiments obtained by the ordinary skill in the art without making creative labor belong to the scope of the utility model protection.

[0048] In the following detailed description, each of the drawings used to explain the specific embodiments of the present application can be referred to as part of the present application.In the drawings, similar reference numerals in different figures generally describe similar components.The specific embodiments of the present application are described in sufficient detail in the following so that the ordinary skilled in the art with relevant knowledge and skills can implement the technical scheme of the present application.It should be understood that other embodiments or structural, logical or electrical changes of the embodiments of the present application can also be used.

[0049] The utility model provides a kind of packaging structure of gallium nitride cascade device, the gallium nitride cascade device is the composite switch of high-voltage gallium nitride chip and low-voltage enhancement chip, wherein high-voltage gallium nitride chip such as HEMT, low-voltage enhancement chip such as MOS, JEFT or triode.In the following description, Cascode is taken as an example by HEMT and MOS, however, it can be known that the following packaging method and corresponding structure are also applicable to the Cascode of low-voltage chip JEFT or triode.

[0050] Since the drain of current conventional MOS chip is distributed on the back of chip, source and gate are distributed on the front of chip, while the drain, source and gate of conventional HEMT chip are distributed on the front of chip, so as to realize the electrical connection relationship shown in the figure, its packaging structure is as shown in the figure Figure 1 Figure 2 ​As shown, not only the substrate U3 is needed, but also the HEMT gate G1 of the HEMT chip U1 is needed to be wired, and is electrically connected with the base island conductive area on the packaging frame through the bonding wire. For the packaging structure, the utility model discloses at least one of the electrode position of the conventional HEMT chip and the conventional MOS chip is transferred to change the distribution position of the electrode, so that the purpose of reducing the wiring and simplifying the packaging process flow is achieved. In addition, in the utility model, the chip surface used for contacting the base island or the substrate of the packaging frame in the patching step in the packaging process is called the back surface, and the opposite side is called the front surface.

[0051] In addition, the packaging form of the GaN Cascode in the utility model can include but is not limited to QFN, DFN, TO, CSP, BGA, SOP, FOPLP and FOWLP, so that in the following description, the packaging frame used in the packaging structure can be any form, and the packaging frame in the following embodiment is only used as an example for simple description, and in actual production, any packaging frame suitable for the determined packaging form and the corresponding subsequent packaging process flow can be used according to the needs.

[0052] Embodiment one

[0053] Figure 3 It is a device packaging structure schematic diagram of the GaN Cascode according to the embodiment one of the utility model. The device packaging structure of the GaN Cascode in the embodiment one includes the packaging frame 1, the HEMT chip U1 and the MOS chip U2, the HEMT chip U1 in the embodiment is the conventional HEMT chip, and three electrodes are distributed on the chip front surface, including one long strip HEMT drain D1, one long strip HEMT source S1 and two square HEMT gates G1. The MOS chip U2 is the chip after the electrode position of the conventional MOS chip is transferred, and the MOS drain D2 and the MOS gate G2 of the MOS chip U2 are located on the chip front surface, and the MOS source S2 is located on the chip back surface.

[0054] Referring to Figure 4 , Figure 4 It is a packaging method flow chart of the GaN Cascode according to the embodiment one of the utility model, and the packaging method includes the following steps:

[0055] Step S1, providing the HEMT chip U1 and the MOS chip U2. Wherein, the HEMT chip U1 is the conventional HEMT chip, and the MOS chip U2 is the chip after the electrode position is transferred.

[0056] Step S2, providing a packaging frame 1. According to the packaging category determined according to specific needs, the corresponding packaging frame is adopted. The packaging frame includes a plurality of frame units connected by connecting ribs. Each frame unit includes at least a base island 11 for mounting a chip, a device gate region 12, and a device drain region 13. In this embodiment, the base island 11 is also the device source region. In addition, according to the packaging category applied, the device gate region 12, the device drain region 13, and the device source region in the packaging frame in this embodiment can also be deformed into corresponding pins, so those skilled in the art can understand that the device gate region 12, the device drain region 13, and the device source region in this utility model can have the same function as the pins in other packaging. In order to correspond to the structure in a single device, each frame unit is referred to as a packaging frame 1 in the following description.

[0057] Step S3, the HEMT chip U1 and the MOS chip U2 are arranged side by side on the base island. In this embodiment, an adhesive 31 (see Figure 5 ) is used to attach the back of the HEMT chip U1 to a predetermined position on the base island, and conductive glue is used to attach the back of the MOS chip U2 to the base island 11 in a side-by-side relationship with the HEMT chip U1. Since the MOS source S2 is located on the back of the chip and is attached by conductive glue, the MOS source S2 is electrically connected (referred to as contact electrical connection) with the conductive region on the base island.

[0058] Step S4, electrical interconnection, that is, the electrical connection between the two chip electrodes, the electrodes and the packaging frame is completed. In this utility model, the electrical connection in the interconnection step can adopt any form, and in this embodiment, the interconnection is performed in the form of wire bonding. For example, wire bonding is performed between the HEMT drain D1 and the device drain region 13 through a wire bonding process, so that the HEMT drain D1 and the device drain region 13 are electrically connected. Similarly, wire bonding is performed between the HEMT source S1 and the MOS drain D2, so that the HEMT source S1 and the MOS drain D2 are electrically connected. Wire bonding is performed between the HEMT gate G1 and the base island 11, so that the HEMT gate G1 and the base island 11 are electrically connected. Since the MOS source S1 is electrically connected to the base island 11, the electrical connection between the HEMT gate G1 and the MOS source S1 is achieved. Wire bonding is performed between the MOS gate G2 and the device gate region 12, so that the MOS gate G2 and the device gate region 12 are electrically connected. See Figure 3The base island 11, the device gate region 12 and the device drain region 13 of the packaging frame 1 are solid regions, and the regions between the device gate region 12 and the device drain region 13 and the base island 11 are hollow regions. It can be understood that, in addition to the wire bonding process, a strip bonding process can also be used, for example, a metal strip such as an aluminum strip is bonded by ultrasonic wedge bonding. A metal sheet can also be directly pressure-welded to the electrode surface of the chip and the pin or electrode region of the device by a pressure-welding bridge process. The specific interconnection process can be flexibly selected according to actual conditions.

[0059] Referring to Figure 5 , Figure 5 is a side structure schematic diagram of the device packaging structure of the GaN Cascode after the patching and interconnection according to the embodiment one of the present application. In this embodiment, the wire 41 such as copper wire or aluminum wire is used for interconnection. It can be understood that, when the device needs to be applied in a large current scenario, copper strips, aluminum strips, copper sheets and the like can also be used for interconnection.

[0060] Step S5, plastic packaging. For example, a plastic molding process is used to encapsulate plastic packaging materials such as epoxy resin around the chip, wire and the like, thereby protecting them. According to the actual conditions of production equipment and production lines, a transfer molding method, a compression molding method and the like can be used. This step can also include the step of surface grinding the plastic packaging material, thereby exposing the flat electrode surface.

[0061] Step S6, the electrode surface is plated or electroplated with Ag, Au or sputtered with aluminum and the like metal that can be welded with a wire.

[0062] Step S7, marking on the surface of the plastic body of the device, for example, laser or ink is used to print chip information such as brand, model, batch, production cycle, version, place of origin and the like on the surface of the chip.

[0063] Step S8, cutting the overall plastic body to remove the connecting ribs, flash and the like, thereby obtaining a single GaN Cascode.

[0064] In this embodiment, after the electrode position of the MOS chip U2 is transferred, the MOS drain D2 and the HEMT source S1 to be interconnected are located on the front surface of the respective chips, so they can be directly interconnected by wire bonding and the like, and no longer need a substrate for transfer. Therefore, this embodiment does not need a substrate when packaging, and only needs to mount the chip twice when mounting, shortens the packaging cycle, and also reduces the difficulty of packaging, patching and wire bonding. In addition, compared with Figure 2In comparison, this embodiment significantly reduces bonding wires (by more than 30%), and consequently reduces parasitic inductance / resistance (experiments have shown that parasitic inductance and resistance are reduced by more than 20% each), thus improving the performance of the packaged gallium nitride cascade device. Simultaneously, this embodiment uses less packaging material, reducing packaging costs. Furthermore, the solution provided by this invention effectively reduces device size, thus enabling compatibility with more package frames of various forms and sizes, solving the problem of existing gallium nitride cascade devices being unable to be layered or installed in other sizes and forms of package frames due to their large area.

[0065] Figure 6 This is a schematic diagram of a MOS chip structure during the electrode position transfer process according to an embodiment of the present invention. In this embodiment, the silicon wafer that has not yet been cut after the fabrication of each semiconductor layer, source, and gate of the MOS chip is completed is used as the target for electrode position transfer processing. To simplify the drawings, Figure 6 The image shows only one conventional MOS die on a silicon wafer. The specific steps include:

[0066] Step S11: Add a UBM (Under-Bump Metallurgy) metal layer with a thickness of 1–10 μm to the electrode surface on the front side of the wafer. The addition method can be electroplating, evaporation, or sputtering. Metals that can be used for UBM include, for example, titanium-copper, nickel-gold, nickel-palladium-gold, or titanium-nickel-silver. See also... Figure 6 , Figure 6 The first image shows a conventional MOS die on a wafer, and the second image shows a schematic diagram of the MOS die structure after step S11.

[0067] Step S12: Thinning the back side of the wafer. This step is optional. By grinding the silicon substrate on the back side of the wafer to a certain thickness, the original MOS die thickness is reduced, thus avoiding excessive thickness of the MOS chip after electrode repositioning.

[0068] Step S13 involves applying silver, gold, or copper to the back of the wafer. The back of a conventional MOS chip serves as the drain. After step S13, a layer of metal is added to the original drain location, which facilitates heat dissipation. The thickness ranges from 1-10 μm.

[0069] Step S14: Provide a metal layer on the back of the wafer that is easy to electroplate or brush on a conductive adhesive that can be used for electroplating metal, with a thickness greater than or equal to 10 μm.

[0070] Step S15: Divide the wafer to obtain a single MOS die, hereinafter referred to as a MOS chip.

[0071] Step S16, flip-chip the plurality of MOS chips on the temporary bonding film with a certain interval, and backside molding of the MOS chips, wherein the temporary bonding film is on the temporary substrate / carrier.

[0072] Step S17, thinning the backside molding 51 of the MOS chip until the metal layer or glue layer on the backside of the MOS chip is exposed.

[0073] Step S18, drilling a hole on the molding beside the MOS chip body to form a G electrode hole. In an optional solution, the distance between the G electrode hole and the MOS chip body is small enough to reduce the length of the connecting metal layer between the original gate on the front side of the MOS chip and the metal at the G electrode hole, thereby reducing the parasitic parameters generated between the connecting metal layer and the nearest source S electrode surface.

[0074] Step S19, electroplating a layer of copper on the upper surface of the current structure (i.e. the backside of the MOS chip), and then etching to form a first redistribution layer RDL1, thereby forming a separate MOS drain D and a new MOS gate G, which extends to the backside of the molding through the G electrode hole.

[0075] Step S110, removing the carrier and the temporary bonding film to expose the electrodes on the front side of the MOS, i.e. the source S and the original gate G, flip-chipping the backside of the MOS on the temporary bonding film, electroplating metal on the front side of the MOS, and etching the electroplated metal layer to obtain a second redistribution layer RDL2. The second redistribution layer includes a thickened source S, a thickened original gate, and a connecting metal layer between the original gate and the G electrode hole, thereby electrically connecting the original gate of the MOS and the new gate G. Preferably, the area of the connecting metal layer between the original gate and the G electrode hole is minimized when etching the electroplated metal layer. As can be seen, the electrode surface of the original MOS chip gate G and the electrode surface of the source S are on the front side of the chip, and the pre-positioned electrode surface of the gate is on the backside of the chip. The original position of the gate G is transferred to the backside of the chip through the second redistribution layer RDL2 on the front side, the G electrode hole, and the first redistribution layer RDL1. The G electrode hole is in the second molding.

[0076] Step S111, molding the front side of the MOS chip, and grinding the upper surface of the molding 52 to expose the flat gate G electrode surface and the source S electrode surface.

[0077] Step S112, electroplating metal, such as copper, on the source S electrode surface on the front side of the MOS chip to heighten the source S. In an embodiment, the height of the heightened source S electrode surface is ≥15um.

[0078] Step S113, molding the front side of the MOS chip again, and grinding the upper surface of the molding to expose the flat source S.

[0079] Step S114: Fan out the source S electrode surface to the entire surface of the current molding compound to serve as the source S of the finished MOS, and then remove the carrier plate and temporary bonding film.

[0080] After the above steps, the gate G on the front side of the original MOS chip is rearranged to the back side of the chip, and the source S on the front side of the original MOS chip is arranged on the entire surface. Therefore, the front side of the original MOS chip becomes the back side of the repackaged MOS chip, and the back side of the original MOS chip becomes the front side of the repackaged MOS chip.

[0081] Step S115: Electroplating or plating Ag, Au, or sputtering aluminum or other wire-bonding metals on the electrode surfaces of the gate G and drain D of the repackaged MOS; electroplating or sputtering Ag or Au or other surface-mount metals on the electrode surface of the source S of the repackaged MOS.

[0082] Step S116: Cutting and shaping, thereby obtaining multiple individual MOS chips after electrode position transfer.

[0083] pass Figure 6 As shown in the electrode relocation process flow, this embodiment uses the RDL process to rearrange the gate of the original MOS chip to the back side of the original chip, and fans out the source of the original chip's front side to the current chip size. Therefore, the front and back sides of the MOS chip after electrode relocation are exactly opposite to those of the original MOS chip. In the secondary packaging of the MOS chip, this invention can expand the electrode area of ​​the MOS gate through the RDL process, which can meet the requirements of using larger cross-sectional area aluminum wires, copper strips, or aluminum strips for interconnection in high-current scenarios, without needing to increase the area of ​​the original chip. In the prior art, for high-current scenarios, in order to use large-diameter bonding wires for interconnection, a larger electrode area of ​​the chip is required. Therefore, the chip area is usually increased during wafer processing, resulting in a smaller number of chips that can be made from the same area wafer, leading to wasted chip area. However, the MOS chip used in this invention does not require an increase in chip area during wafer processing, thus avoiding wasted chip area and improving wafer utilization, resulting in a significant cost advantage. In addition, by performing secondary packaging of the chip, this invention eliminates the need to fabricate large-sized chips on the wafer when a large electrode area is required. Instead, the electrode surface is transferred out through the RDL process. Since the packaging cost is much lower than the wafer processing cost, this invention reduces production costs.

[0084] In the foregoing embodiment, the rearranged electrode is a MOS gate, and a source S remains on the chip surface at its original position. Figure 6The electrode schematic diagram of the finally completed MOS chip can be seen that the finally completed source electrode S is fan-out to the whole back surface of the chip, and the original position electrode surface of the gate and the metal layer connected with the electrode hole are encapsulated in the plastic encapsulation body. In order to reduce the parasitic inductance possibly caused by the new source electrode surface and the internal gate metal surface (part of the second re-distribution layer RDL2), in an embodiment, after the source electrode surface is fan-out to the whole back surface of the chip, the source electrode surface of the chip back surface is patterned, so that the source electrode surface of the chip back surface is staggered with the internal gate metal surface, for example, the electrode surface opposite to the internal gate metal surface on the chip back surface is etched.

[0085] Figure 7 The electrode schematic diagram of the finally completed MOS chip can be seen that the finally completed source electrode S is fan-out to the whole back surface of the chip, and the original position electrode surface of the gate and the metal layer connected with the electrode hole are encapsulated in the plastic encapsulation body. In order to reduce the parasitic inductance possibly caused by the new source electrode surface and the internal gate metal surface (part of the second re-distribution layer RDL2), in an embodiment, after the source electrode surface is fan-out to the whole back surface of the chip, the source electrode surface of the chip back surface is patterned, so that the source electrode surface of the chip back surface is staggered with the internal gate metal surface, for example, the electrode surface opposite to the internal gate metal surface on the chip back surface is etched.

[0086] Although the embodiment is taken as the silicon wafer which has not been cut after the preparation of each semiconductor layer of the MOS and the source and the gate as the secondary packaging processing target, it can be known that the single MOS chip which has been packaged and cut can also be taken as the packaging processing target.

[0087] Embodiment two

[0088] Figure 8 The device packaging structure schematic diagram of the GaN Cascode according to the embodiment two of the utility model. The GaN Cascode packaging structure in the embodiment two includes a packaging frame 1, a HEMT chip U1 and a MOS chip U2. The HEMT chip U1 in the embodiment is a conventional HEMT chip, and three electrodes are distributed on the front surface of the chip, including a long strip-shaped HEMT drain D1, a long strip-shaped HEMT source S1 and two square-shaped HEMT gates G1. The MOS chip U2 is a chip after the secondary packaging of a conventional MOS chip, and the MOS drain D2, the MOS source S2 and the MOS gate G2 of the MOS chip U2 are located on the front surface of the chip.

[0089] The packaging process in the embodiment is the same as that in the embodiment one, and will not be repeated here. In the embodiment, the MOS chip U2 is a chip after the electrode position transfer and the secondary packaging of a conventional MOS chip, and the MOS drain D2 originally on the back surface of the chip is transformed to the front surface of the chip after the electrode position transfer and the packaging.

[0090] Figure 9 is a MOS chip structure schematic diagram in the electrode position transfer process of the MOS chip U2 according to another embodiment of the present application, in the embodiment, a single conventional MOS chip is taken as a processing object, and specifically includes the following steps:

[0091] Step S21, a plurality of MOS chips are inversely attached on a temporary carrier, and a UBM (Under-Bump Metallurgy) metal layer with a thickness of 1-10 um is added to the drain D electrode surface on the back of the MOS chip. The added mode is for example electroplating, evaporation or sputtering, and the UBM metal is for example titanium copper or nickel gold or nickel palladium gold or titanium nickel silver used for electroplating. The electrodes on the front of the single conventional MOS chip are source and gate, and the back is drain.

[0092] Step S22, the back of the MOS chip is plastic encapsulated, and the plastic encapsulation body is ground to expose the drain D electrode surface on the back of the MOS chip.

[0093] Step S23, a hole is drilled beside the MOS chip body to form a D electrode hole. In an optional solution, the D electrode hole can be in a strip shape, and the size is about equal to that of the front source S.

[0094] Step S24, a metal layer is electroplated on the back of the current MOS chip to obtain a first redistribution layer (RDL1). The D electrode hole and the MOS drain D are connected together, so that the MOS drain D extends to the front of the plastic encapsulation body through the D electrode hole.

[0095] Step S25, the current structure is plastic encapsulated again.

[0096] Step S26, then the temporary carrier is removed, the current structure body is turned over, and the front of the plastic encapsulation body is ground to expose the electrode surfaces of the drain D, source S and gate G on the front, and at this time, the drain D, source S and gate G of the finished product MOS are obtained.

[0097] Step S27, the gate G, drain D and source S of the finished product MOS are plated with Ag, Au or sputtered with aluminum or other metals that can be soldered, and the back of the encapsulation body is plated / sputtered with Ag or Au or other metals that can be attached.

[0098] Step S28, cutting and forming are performed, and thus a plurality of MOS chips that are twice encapsulated are obtained.

[0099] Embodiment three

[0100] Figure 10is a device packaging structure schematic diagram of GaN Cascode according to the embodiment three of the utility model. The GaN Cascode packaging structure in embodiment three includes packaging frame 1, HEMT chip U1 and MOS chip U2, the MOS chip U2 is original chip, MOS drain D2 (not shown) is distributed on the chip back, MOS source S2 and MOS gate G2 are distributed on the chip front. When pasting MOS chip U2, MOS drain D2 is fixed together with base island 11 through conductive glue, thus with its electrical connection. The HEMT chip U1 is the chip after secondary packaging, HEMT gate G1 and HEMT drain D1 are located on the chip front, and HEMT source S1 is located on the chip back, when pasting HEMT chip U1, HEMT source S1 is fixed together with base island 11 through conductive glue, thus with its electrical connection state. Thus, HEMT source S1 and MOS drain D2 are all located on the back of respective chip, and are respectively electrically connected with base island 11, thereby realizing the electrical connection of both. In the embodiment, HEMT gate G1 and MOS source S2 are electrically connected to device source area 14 through the mode of wire bonding respectively. HEMT drain D1 is electrically connected with device drain area 13 through the mode of wire bonding. MOS gate G2 and device gate area 12 are electrically connected through the mode of wire bonding.

[0101] The packaging method of the embodiment is similar to that of embodiment one, and will not be repeated here.

[0102] Figure 11 is a chip structure cross section schematic diagram obtained after the secondary packaging of HEMT chip according to an embodiment of the utility model, and the secondary packaging process is similar to the secondary packaging of MOS chip in embodiment one and embodiment two, and will not be repeated here.

[0103] Embodiment four

[0104] Figure 12Is the device packaging structure schematic diagram of GaN Cascode according to the fourth embodiment of the utility model. The GaN Cascode packaging structure in the fourth embodiment includes the packaging frame 1, the HEMT chip U1 and the MOS chip U2, the HEMT chip U1 and the MOS chip U2 are respectively the chip after secondary packaging;Wherein, the drain D1 and the source S1 of the HEMT chip U1 after secondary packaging are located at the front of the chip, and the grid G1 is located at the back of the chip, when being attached to the base island 11 of the packaging frame, the electric connection with the conductive area on the base island 11. The source S2, the drain D2 and the grid G2 of the MOS chip U2 after secondary packaging are all located at the front of the chip;When being attached to the base island 11 of the packaging frame, the electrical insulation is realized with the conductive area on the base island 11 through the insulating glue. The drain D2 of the MOS chip U2 and the source S1 of the HEMT chip U1 are electrically connected in the way of wire bonding. The source S2 of the MOS chip U2 is electrically connected to the conductive area on the base island 11 in the way of wire bonding, thereby realizing the electrical connection with the grid G1 of the HEMT chip U1.

[0105] The packaging method of the embodiment is similar to the first embodiment, and will not be repeated here.

[0106] Figure 13 Is the chip structure cross section schematic diagram obtained after the secondary packaging of the HEMT chip according to another embodiment of the utility model, and the secondary packaging process is similar to the secondary packaging of the MOS chip in the first embodiment, and will not be repeated here.

[0107] Embodiment five

[0108] Figure 14 Is the device packaging structure schematic diagram of GaN Cascode according to the fifth embodiment of the utility model. The GaN Cascode packaging structure in the fifth embodiment includes the packaging frame 1, the HEMT chip U1 and the MOS chip U2, the HEMT chip U1 and the MOS chip U2 are respectively the chip after secondary packaging;Wherein, the drain D1 and the source S1 of the HEMT chip U1 after secondary packaging are located at the front of the chip, and the grid G1 is located at the back of the chip, when being attached to the base island 11 of the packaging frame, the grid G1 of the HEMT chip U1 is electrically connected with the conductive area on the base island 11. The drain D2 and the grid G2 of the MOS chip U2 after secondary packaging are located at the front of the chip, and the source S2 is located at the back of the chip. When being attached to the base island 11 of the packaging frame, the source S2 of the MOS chip U2 is electrically connected with the conductive area on the base island 11. The drain D2 of the MOS chip U2 and the source S1 of the HEMT chip U1 are electrically connected in the way of wire bonding.

[0109] The packaging method of the embodiment is similar to the first embodiment, and will not be repeated here.

[0110] Embodiment six

[0111] Figure 15 is a device packaging structure diagram of GaN Cascode according to the embodiment six of the present application. The GaN Cascode packaging structure in the embodiment six comprises a packaging frame 1, a HEMT chip U1 and a MOS chip U2, the MOS chip U2 is a chip after secondary packaging by modifying the electrodes of an original chip, a MOS source S2, a MOS gate G2 and a MOS drain D2 are distributed on the front face of the chip. When the MOS chip U2 is attached, the MOS chip U2 is attached to the base island 11 through insulating glue. The MOS drain D2 is electrically connected with the conductive area on the base island 11 through wire bonding. The HEMT chip U1 is a chip after secondary packaging, a HEMT gate G1 and a HEMT drain D1 are located on the front face of the chip, and a HEMT source S1 is located on the back face of the chip. When the HEMT chip U1 is attached, the HEMT source S1 is fixed with the base island 11 through conductive glue, so that the electrical connection between the HEMT source S1 and the MOS drain D2 is realized. In the embodiment, the HEMT gate G1 and the MOS source S2 are electrically connected to the device source area 14 through wire bonding. The HEMT drain D1 is electrically connected with the device drain area 13 through wire bonding. The MOS gate G2 and the device gate area 12 are electrically connected through wire bonding.

[0112] Embodiment seven

[0113] Figure 16 is a device packaging structure diagram of GaN Cascode according to the embodiment seven of the present application. The GaN Cascode packaging structure in the embodiment seven comprises a packaging frame 1, a HEMT chip U1, a MOS chip U2 and a substrate U3, the MOS chip U2 is an original chip, a MOS drain D2 is located on the back face of the chip, and a MOS source S2 and a MOS gate G2 are located on the front face of the chip. The HEMT chip U1 is a HEMT chip after secondary packaging; wherein the drain, the source and the gate of the original HEMT chip are distributed on the front face of the chip, the HEMT drain D1 and the HEMT source S1 of the HEMT chip U1 obtained after secondary packaging are located on the front face of the chip, and the HEMT gate G1 is located on the back face of the chip.

[0114] The packaging method comprises the following steps: firstly, providing a twice-packaged HEMT chip U1; then, arranging the HEMT chip U1 and a substrate U3 on the base island 11 of the packaging frame 1 in parallel, and the gate of the HEMT chip is electrically connected with the conductive area on the base island; the front surface of the substrate comprises a conductive area, and the substrate is arranged on the base island in an insulating manner; then, arranging a MOS chip U2 on the conductive area on the front surface of the substrate U3, and electrically connecting the MOS drain D2 on the back surface of the MOS chip U2; then, interconnecting; in the embodiment, the MOS source S2 and the conductive area on the base island 11 are electrically connected by wire, the HEMT source S2 and the conductive area on the front surface of the substrate U3 are electrically connected, the HEMT drain D2 and the device drain area 13 of the packaging frame are electrically connected, and the MOS gate G2 and the device gate area 12 of the packaging frame 1 are electrically connected.

[0115] By Figure 16 It can be seen that, although the substrate is still used in the embodiment, the number of welding wires is reduced by modifying the electrodes of the HEMT, so that the parasitic inductance / resistance is reduced, and the overall performance of the device is improved.

[0116] Embodiment eight

[0117] Figure 17 It is a schematic diagram of a GaN Cascode packaging structure according to the embodiment eight of the present application. The GaN Cascode packaging structure in the embodiment eight comprises a packaging frame 1, an HEMT chip U1 and a MOS chip U2. The MOS chip U2 is an original chip, the MOS drain D2 is located on the back surface of the chip, and the MOS source S2 and the MOS gate G2 are located on the front surface of the chip. The HEMT chip U1 is a twice-packaged HEMT chip after electrode position transfer, the drain, the source and the gate of the original HEMT chip are distributed on the front surface of the chip, the HEMT drain D1 and the HEMT source S1 of the HEMT chip U1 obtained after the electrode position transfer are located on the front surface of the chip, the HEMT gate G1 is transferred to the back surface of the chip through a rewiring layer and an electrode hole, and the original HEMT source S1 electrode located on the front surface of the chip is fanned out to increase the electrode area.

[0118] In the packaging process, when the HEMT chip U1 and the MOS chip U2 are attached on the base island, the HEMT chip U1 is first attached on the conductive area of the base island, since the back of the HEMT chip U1 is the gate G1, thus when attaching, conductive glue or the like is used to make the gate G1 electrically connected with the conductive area of the base island 11. Then the MOS chip U2 is attached on the electrode surface of the HEMT source S1 through conductive glue. Then in the electrical interconnection process, the HEMT drain D1 and the device drain area 13 are electrically connected through wire bonding, the source S2 of the MOS chip U2 is electrically connected with the conductive area of the base island 11 through wire bonding, in the embodiment, the conductive area of the base island 11 is used as the device source area, and the gate G1 of the MOS chip U2 is electrically connected with the device gate area 12 through wire bonding.

[0119] In addition, in some embodiments, in order to improve the performance of the GaN Cascode, a boosting device such as a resistor, a capacitor and an inductor can also be added. These boosting devices can be integrated in the MOS or HEMT device body, or can be attached on the base island or the MOS or HEMT chip, and then packaged together.

[0120] The utility model discloses a change the electrode layout of original chip can reduce the use of big substrate, reduce the number of soldering wire, reduced cost and process difficulty, improved the performance and reliability of product. The utility model discloses can effectively reduce the actual use area of packaged chip, realizes more reasonable chip layout and thus can adapt to smaller packaging form. The utility model discloses when the electrode surface of original chip is reformed, through RDL process can realize arbitrary wiring layout, make the shape of electrode surface can be compatible with traditional frame, better compatible thick bonding wire, aluminum strip, copper sheet etc., more conducive to high -power device.

[0121] The above embodiments are only used to illustrate the utility model, and are not limited to the utility model. Those skilled in the art can make various changes and modifications without departing from the scope of the utility model. Therefore, all equivalent technical solutions shall belong to the scope of the utility model.

Claims

1. A packaging structure for a gallium nitride cascade device, characterized in that, The application relates to a packaging structure of a gallium nitride chip and a low-voltage enhancement chip. The packaging structure comprises a packaging frame, a gallium nitride chip, a low-voltage enhancement chip and a plastic package. The packaging frame comprises a base island for mounting the chips, a device gate region, a device drain region and a device source region. The gallium nitride chip is an original gallium nitride chip or a chip obtained by electrode position transfer of the original gallium nitride chip. The low-voltage enhancement chip is an original low-voltage enhancement chip or a chip obtained by electrode position transfer of the original low-voltage enhancement chip. The drain of the gallium nitride chip is electrically connected with the device drain region of the packaging frame. The gate of the gallium nitride chip, the source of the low-voltage enhancement chip and the device source region of the packaging frame are electrically connected. The gate of the low-voltage enhancement chip is electrically connected with the device gate region of the packaging frame.

2. The packaging structure for a gallium nitride cascade device according to claim 1, wherein The source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the same surface of the respective chips.

3. The packaging structure for a gallium nitride cascade device according to claim 2, wherein The gallium nitride chip and the low-voltage enhancement chip are mounted side by side on the base island of the packaging frame.

4. The packaging structure for a gallium nitride cascade device according to claim 2, wherein When the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the front surface of the respective chips, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are electrically connected through a metal connecting piece.

5. The packaging structure for a gallium nitride cascade device according to claim 2, wherein When the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the back surface of the respective chips, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are respectively in contact with the conductive region on the base island for electrical connection. The gallium nitride chip is an original gallium nitride chip, and the drain, the source and the gate of the gallium nitride chip are distributed on the front surface of the chip. The low-voltage enhancement chip is a chip obtained by electrode position transfer of an original low-voltage enhancement chip, and the source, the drain and the gate of the low-voltage enhancement chip are distributed on the front surface of the chip. The source of the low-voltage enhancement chip is in contact with the conductive region on the base island for electrical connection. The low-voltage enhancement chip is an original low-voltage enhancement chip, and the drain of the low-voltage enhancement chip is distributed on the back surface of the chip. The gallium nitride chip is a chip obtained by electrode position transfer of an original gallium nitride chip, and the gate and the drain of the gallium nitride chip are located on the front surface of the chip, and the source is located on the back surface of the chip. The drain on the back surface of the low-voltage enhancement chip and the source of the gallium nitride chip are respectively in contact with the conductive region on the base island for electrical connection. The source on the back surface of the low-voltage enhancement chip and the gate of the gallium nitride chip are respectively electrically connected with the device source region through a metal connecting piece.

6. The packaging structure for a gallium nitride cascade device according to claim 2, wherein The gallium nitride chip is a chip obtained by electrode position transfer of an original gallium nitride chip, the drain, the source and the gate of the original gallium nitride chip being distributed on the front surface of the chip, the drain and the source of the gallium nitride chip obtained by electrode position transfer being located on the front surface of the chip, and the gate being located on the back surface of the chip; The low-voltage enhancement chip is a chip obtained by electrode position transfer of an original low-voltage enhancement chip, the drain of the original low-voltage enhancement chip being distributed on the back surface of the chip, the source and the gate being distributed on the front surface of the chip, the drain and the gate of the low-voltage enhancement chip obtained by electrode position transfer being located on the front surface of the chip; the gate of the gallium nitride chip is in contact and electrically connected with the conductive region on the base island; the drain of the low-voltage enhancement chip and the source of the gallium nitride chip are electrically connected through the metal connecting member.

7. The packaging structure for a gallium nitride cascade device according to claim 6, wherein The source, the drain and the gate of the low-voltage enhancement chip obtained by electrode position transfer are all located on the front surface of the chip, and the source of the low-voltage enhancement chip is in contact and electrically connected with the conductive region on the base island through the metal connecting member.

8. The packaging structure for a gallium nitride cascade device according to claim 7, wherein The source of the low-voltage enhancement chip obtained by electrode position transfer is located on the back surface of the chip, and the source of the low-voltage enhancement chip is in contact and electrically connected with the conductive region on the base island.

9. The packaging structure for a gallium nitride cascade device according to claim 2, wherein The gallium nitride chip is a chip obtained by electrode position transfer of an original gallium nitride chip, the drain, the source and the gate of the original gallium nitride chip being distributed on the front surface of the chip, the drain and the gate of the gallium nitride chip obtained by electrode position transfer being located on the front surface of the chip, and the source being located on the back surface of the chip; The low-voltage enhancement chip is a chip obtained by electrode position transfer of an original low-voltage enhancement chip, the drain, the source and the gate of the original low-voltage enhancement chip being distributed on the front surface of the chip, the drain, the source and the gate of the low-voltage enhancement chip obtained by electrode position transfer being located on the front surface of the chip; the gate of the gallium nitride chip is electrically connected with the source region of the device through the metal connecting member, the drain of the low-voltage enhancement chip is electrically connected with the conductive region on the base island through the metal connecting member, and the source of the low-voltage enhancement chip is electrically connected with the source region of the device through the metal connecting member.

10. The packaging structure for a gallium nitride cascade device according to any one of claims 2 to 9, wherein The metal connecting member is a bonding wire, a metal strip or a metal sheet.

11. The packaging structure for a gallium nitride cascade device according to claim 1, wherein The target chip obtained by electrode position transfer includes an original chip, a rewiring layer and a secondary encapsulation body, the original chip and the rewiring layer being located in the secondary encapsulation body; the rewiring layer re-arranges the target electrode from an original position to a preset position; The target electrode is one or more of a drain, a source and a gate, and the target chip is an original gallium nitride chip and / or an original low-voltage enhancement chip.

12. The packaging structure of a cascode device according to claim 11, wherein, The secondary encapsulation body is provided with an electrode hole, the rewiring layer includes a first rewiring layer and a second rewiring layer, the first rewiring layer being in communication with an electrode surface of the target electrode at the preset position and the electrode hole, the second rewiring layer being in communication with an electrode surface of the target electrode at the original position and the electrode hole, the original position and the preset position of the target electrode being located on the front surface and the back surface of the chip.

13. The packaging structure of a cascode device according to claim 11, wherein The electrode surface at the original position and the electrode surface at the preset position of the target electrode are located on the same surface of the chip, and the rewiring layer is obtained by using a ball planting or metal plating column method between the electrode surface at the original position and the electrode surface at the preset position of the target electrode.

14. The packaging structure of a cascode device according to claim 11, wherein, The rewiring layer located in the secondary encapsulation body is staggered with the electrode surface on the surface of the secondary encapsulation body, and the electrode surface on the surface of the secondary encapsulation body is a drain, a source or a gate.

15. The packaging structure of a cascaded device according to claim 1, wherein, The gallium nitride chip is a chip obtained by transferring the electrode position of an original gallium nitride chip, wherein the gallium nitride gate is located on the back of the chip, and the gallium nitride drain and the gallium nitride source are located on the front of the chip; the low-voltage enhancement chip is an original chip, wherein the source and the gate of the low-voltage enhancement chip are located on the front of the chip, and the drain is located on the back of the chip; The gallium nitride chip is attached to the conductive area of the base island, and the gallium nitride gate on the back of the gallium nitride chip is electrically connected to the conductive area of the base island; the low-voltage enhancement chip is attached to the gallium nitride source electrode surface, and the drain on the back of the low-voltage enhancement chip is electrically connected to the gallium nitride source electrode surface.

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