Pixel circuit and pixel driving array

Abstract

The utility model discloses a pixel driving circuit and a pixel driving array composed of the pixel circuit, and the pixel circuit comprises a latch unit which receives a row control signal and a column control signal, and latches the column control signal based on the row control signal to output a first control signal; the gating unit is connected with the latch unit and is controlled to be conducted based on the received first control signal so as to output the received driving signal; the control end of the driving tube is connected with the gating unit to receive the driving signal so as to switch on or switch off the driving tube, the first end of the driving tube serves as an output node of the pixel circuit, and the output node provides driving current. According to the pixel driving circuit, the latch unit is arranged, and a digital latch mode replaces a traditional capacitance holding mode, so that the whole frame period can be kept after the corresponding driving current is written into each pixel, and the influence of electric leakage on the pixel driving array of the pixel driving circuit can be reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to LED drive technical field, especially, relate to a pixel circuit and pixel drive array. BACKGROUND

[0002] LED products are mainly applied to three major fields of backlight, color screen and illumination. In the field of illumination, the emerging Micro LED (Micro Light Emitting Diode Display) pixel big lamp will gradually become the mainstream of future market automobile intelligent lighting. The plurality of Micro LED in the Micro LED pixel big lamp is usually arranged in an array, and the area of each pixel unit in the Micro LED array used for car lamp illumination is extremely small.

[0003] However, the Micro LED currently applied in the field of color screen usually only needs a driving current of uA or several hundred nA level, which is different from the level of the driving current required by each Micro LED in the Micro LED pixel big lamp in automobile lighting. Therefore, the traditional nTnC structure (a structure composed of multiple transistors and multiple capacitors, n Transistor and n Capacitor) pixel circuit cannot meet the needs of the Micro LED pixel big lamp. SUMMARY

[0004] In view of the above problems, the purpose of the utility model is to provide a pixel circuit and pixel drive array which are less affected by electric leakage.

[0005] According to an aspect of the utility model, a pixel circuit is provided, which comprises:

[0006] A latch unit receives a row control signal and a column control signal, and latches the column control signal based on the row control signal to output a first control signal;

[0007] A gating unit is connected with the latch unit, and controls conduction based on the received first control signal to output a received driving signal;

[0008] A driving tube, a control end of the driving tube is connected with the gating unit to receive the driving signal, so as to turn on or turn off the driving tube, a first end of the driving tube serves as an output node of the pixel circuit, and the output node provides a driving current.

[0009] Optionally, the output node is connected with an external light emitting element, and the light emitting element receives the driving current.

[0010] Optionally, it further comprises:

[0011] a test unit connected to the first end of the driving tube and configured to determine whether to collect the output voltage at the output node according to a received test row selection signal and a test column selection signal.

[0012] Optionally, the display panel further comprises:

[0013] an electrostatic protection unit connected to the output node and configured to form an electrostatic discharge path for the light emitting element.

[0014] Optionally, the display panel further comprises:

[0015] a first bias unit configured to receive a driving voltage, a reference voltage and a voltage at the first end of the driving tube, and generate the driving signal and a first bias current, and provide the driving signal to the control end of the driving tube via the gating unit and adjust the driving current based on the first bias current.

[0016] Optionally, the display panel further comprises:

[0017] a second bias unit configured to receive a second bias current and a voltage at the first end of the driving tube, and generate the driving signal to be provided to the control end of the driving tube via the gating unit and adjust the driving current based on the second bias current.

[0018] Optionally, the driving signal is a driving voltage provided outside the pixel circuit.

[0019] Optionally, the latch unit receives the row control signal at a first level, and the latch unit outputs an inverted signal of the column control signal as the first control signal,

[0020] the latch unit receives the row control signal at a second level, and the latch unit outputs a signal that remains unchanged.

[0021] Optionally, the gating unit comprises:

[0022] a first NOT gate, an input end of the first NOT gate being connected to the latch unit to receive the first control signal, and an output end of the first NOT gate outputting a second control signal;

[0023] a first transistor, a control end of the first transistor receiving the first control signal, a first end of the first transistor receiving the driving signal, and a second end of the first transistor being connected to the control end of the driving tube;

[0024] a second transistor, a control end of the second transistor receiving the second control signal, a first end of the second transistor receiving the driving signal, and a second end of the second transistor being connected to the control end of the driving tube;

[0025] a third transistor, a control terminal of the third transistor receiving the first control signal, a first terminal of the third transistor being connected with the control terminal of the driving transistor, and a second terminal of the third transistor being grounded,

[0026] a second terminal of the driving transistor being grounded, an anode of the light emitting element being connected with the power supply terminal, and a cathode of the light emitting element being connected with the output node.

[0027] Optionally, the gating unit comprises:

[0028] a first NOT gate, an input terminal of the first NOT gate being connected with the latching unit to receive the first control signal, and an output terminal of the first NOT gate outputting a second control signal;

[0029] a first transistor, a control terminal of the first transistor receiving the first control signal, a first terminal of the first transistor receiving the driving signal, and a second terminal of the first transistor being connected with the control terminal of the driving transistor;

[0030] a second transistor, a control terminal of the second transistor receiving the second control signal, a first terminal of the second transistor receiving the driving signal, and a second terminal of the second transistor being connected with the control terminal of the driving transistor;

[0031] a third transistor, a control terminal of the third transistor receiving the second control signal, a first terminal of the third transistor being connected with the control terminal of the driving transistor, and a second terminal of the third transistor being connected with the power supply terminal,

[0032] a second terminal of the driving transistor being connected with the power supply terminal, an anode of the light emitting element being connected with the output node, and a cathode of the light emitting element being grounded.

[0033] Optionally, the electrostatic protection unit comprises:

[0034] a fifth transistor, a first terminal of the fifth transistor being connected with the output node, a second terminal of the fifth transistor being connected with a control terminal of the fifth transistor and being connected with the power supply terminal; and

[0035] a sixth transistor, a first terminal of the sixth transistor being connected with the first terminal of the fifth transistor, a second terminal of the sixth transistor being connected with a control terminal of the sixth transistor and being grounded.

[0036] Optionally, the electrostatic protection unit comprises:

[0037] a first diode, an anode of the first diode being connected with the output node, and a cathode of the first diode being connected with the power supply terminal; and

[0038] a second diode, an anode of the second diode being connected to ground, a cathode of the second diode being connected to an anode of the first diode.

[0039] Optionally, further comprising

[0040] a first resistor connected between the first end of the driving tube and the output node.

[0041] Optionally, the latch unit comprises:

[0042] a first inverter, an input end of the first inverter receiving the row control signal;

[0043] a second inverter, an input end of the second inverter receiving the column control signal, an enable end of the second inverter being connected to an output end of the first inverter, an output end of the second inverter outputting the first control signal;

[0044] a third inverter, an input end of the third inverter being connected to an output end of the second inverter;

[0045] a fourth inverter, an input end of the fourth inverter being connected to an output end of the third inverter, an enable end of the fourth inverter receiving the row control signal, an output end of the fourth inverter being connected to an output end of the second inverter.

[0046] Optionally, the latch unit comprises:

[0047] a first inverter, an input end of the first inverter receiving the row control signal;

[0048] a fifth inverter, an input end of the fifth inverter receiving the column control signal;

[0049] a first switch, a first end of the first switch being connected to an output end of the fifth inverter, a control end of the first switch being connected to an output end of the first inverter;

[0050] a third inverter, an input end of the third inverter being connected to a second end of the first switch and outputting the first control signal;

[0051] a sixth inverter, an input end of the sixth inverter being connected to an output end of the third inverter; and

[0052] a second switch, a first end of the second switch being connected to an output end of the sixth inverter, a control end of the second switch being connected to an input end of the first inverter, a second end of the second switch being connected to an input end of the third inverter.

[0053] According to another aspect of the present application, a pixel driving array is provided, comprising:

[0054] a plurality of scan lines;

[0055] a plurality of data lines;

[0056] a plurality of arrayed pixel circuits;

[0057] a row control circuit connected to the pixel circuits of a corresponding row via each scan line to provide a corresponding row control signal;

[0058] a column control circuit connected to the pixel circuits of a corresponding column via each data line to provide a corresponding column control signal,

[0059] each pixel circuit comprising:

[0060] a latch unit receiving the row control signal and the column control signal, and latching the column control signal based on the row control signal to output a first control signal;

[0061] a gating unit connected to the latch unit, and controlling to turn on based on the received first control signal to output a received driving signal;

[0062] a driving tube, a control end of the driving tube being connected to the gating unit to receive the driving signal, so as to turn on or turn off the driving tube, a first end of the driving tube being an output node of the pixel circuit, the output node providing a driving current.

[0063] Optionally, an integrated area of a single pixel circuit is less than 50umx50um.

[0064] Optionally, further comprising:

[0065] a plurality of first test lines;

[0066] a plurality of second test lines;

[0067] a plurality of third test lines; and

[0068] a test circuit connected to the pixel circuits of a corresponding row via each first test line to provide a corresponding test row gating signal, connected to the pixel circuits of a corresponding column via each second test line to provide a corresponding test column gating signal, and receiving a plurality of output voltages of the pixel circuits of a corresponding row or a corresponding column via each third test line.

[0069] Optionally, further comprising:

[0070] a plurality of driving voltage lines;

[0071] a plurality of reference voltage lines;

[0072] The driving voltage and reference voltage generating circuit is connected to the pixel circuit of the corresponding row or column via each driving voltage line to provide a driving voltage, and is connected to the pixel circuit of the corresponding row or column via each reference voltage line to provide a reference voltage.

[0073] Optionally, further comprising:

[0074] A plurality of current signal lines;

[0075] A reference current generating circuit is connected to the bias current generating circuit of the corresponding row or column via each current signal line to provide a reference current.

[0076] A plurality of bias current generating circuits, each of which generates k bias currents to provide to k pixel circuits, each bias current being provided to the corresponding pixel circuit via a bias current line, wherein k is a positive integer.

[0077] Optionally, the output node is connected to an external light emitting element, and the light emitting element receives the driving current.

[0078] Optionally, further comprising:

[0079] A test unit connected to the first end of the driving tube and determining whether to collect the output voltage at the output node according to the received test row and test column gate signals.

[0080] Optionally, further comprising:

[0081] An electrostatic protection unit connected to the output node and forming an electrostatic discharge path for the light emitting element.

[0082] Optionally, further comprising:

[0083] A first bias unit receiving the driving voltage, the reference voltage and the first end voltage of the driving tube, and generating the driving signal and the first bias current, and providing the driving signal to the control end of the driving tube via the gating unit, and adjusting the driving current based on the first bias current.

[0084] Optionally, further comprising:

[0085] A second bias unit receiving the second bias current and the first end voltage of the driving tube, and generating the driving signal to be provided to the control end of the driving tube via the gating unit, and adjusting the driving current based on the second bias current.

[0086] Optionally, the driving signal is a driving voltage provided externally to the pixel circuit.

[0087] Optionally, the latch unit receives the row control signal at a first level, the latch unit outputs an inverted signal of the column control signal as the first control signal,

[0088] the latch unit receives the row control signal at a second level, the latch unit outputs a signal unchanged.

[0089] Optionally, the gating unit comprises:

[0090] a first NOT gate, an input end of the first NOT gate is connected with the latch unit to receive the first control signal, an output end of the first NOT gate outputs a second control signal;

[0091] a first transistor, a control end of the first transistor receives the first control signal, a first end of the first transistor receives the driving signal, a second end of the first transistor is connected with a control end of the driving tube;

[0092] a second transistor, a control end of the second transistor receives the second control signal, a first end of the second transistor receives the driving signal, a second end of the second transistor is connected with the control end of the driving tube;

[0093] a third transistor, a control end of the third transistor receives the first control signal, a first end of the third transistor is connected with the control end of the driving tube, a second end of the third transistor is grounded,

[0094] a source end of the driving tube is grounded, an anode of the light emitting element is connected with a power supply end, a cathode of the light emitting element is connected with the output node.

[0095] Optionally, the gating unit comprises:

[0096] a first NOT gate, an input end of the first NOT gate is connected with the latch unit to receive the first control signal, an output end of the first NOT gate outputs a second control signal;

[0097] a first transistor, a control end of the first transistor receives the first control signal, a first end of the first transistor receives the driving signal, a second end of the first transistor is connected with a control end of the driving tube;

[0098] a second transistor, a control end of the second transistor receives the second control signal, a first end of the second transistor receives the driving signal, a second end of the second transistor is connected with the control end of the driving tube;

[0099] a third transistor, a control terminal of the third transistor receiving the second control signal, a first terminal of the third transistor being connected with a control terminal of the drive transistor, and a second terminal of the third transistor being connected with a power terminal,

[0100] a source terminal of the drive transistor being connected with the power terminal, an anode of the light emitting element being connected with the output node, and a cathode of the light emitting element being grounded.

[0101] Optionally, the static protection unit comprises:

[0102] a fifth transistor, a first terminal of the fifth transistor being connected with the output node, a second terminal of the fifth transistor being connected with a control terminal of the fifth transistor and a power terminal; and

[0103] a sixth transistor, a first terminal of the sixth transistor being connected with the first terminal of the fifth transistor, and a second terminal of the sixth transistor being connected with a control terminal of the sixth transistor and grounded.

[0104] Optionally, the static protection unit comprises:

[0105] a first diode, an anode of the first diode being connected with the output node, and a cathode of the first diode being connected with the power terminal; and

[0106] a second diode, an anode of the second diode being grounded, and a cathode of the second diode being connected with the anode of the first diode.

[0107] Optionally, further comprising

[0108] a first resistor, connected between the first terminal of the drive transistor and the output node.

[0109] Optionally, the latch unit comprises:

[0110] a first inverter, an input terminal of the first inverter receiving the row control signal;

[0111] a second inverter, an input terminal of the second inverter receiving the column control signal, an enable terminal of the second inverter being connected with an output terminal of the first inverter, and an output terminal of the second inverter outputting the first control signal;

[0112] a third inverter, an input terminal of the third inverter being connected with the output terminal of the second inverter;

[0113] a fourth inverter, an input terminal of the fourth inverter being connected with an output terminal of the third inverter, an enable terminal of the fourth inverter receiving the row control signal, and an output terminal of the fourth inverter being connected with the output terminal of the second inverter.

[0114] Optionally, the latch unit comprises:

[0115] a first inverter, an input end of the first inverter receiving the row control signal;

[0116] a fifth inverter, an input end of the fifth inverter receiving the column control signal;

[0117] a first switch, a first end of the first switch being connected with an output end of the fifth inverter, a control end of the first switch being connected with an output end of the first inverter;

[0118] a third inverter, an input end of the third inverter being connected with a second end of the first switch and outputting the first control signal;

[0119] a sixth inverter, an input end of the sixth inverter being connected with an output end of the third inverter; and

[0120] a second switch, a first end of the second switch being connected with an output end of the sixth inverter, a control end of the second switch being connected with an input end of the first inverter, a second end of the second switch being connected with an input end of the third inverter.

[0121] The pixel circuit and the pixel driving array provided by the utility model can keep the whole frame period after each pixel writes in the corresponding driving current through the setting of the latch unit. That is, the digital latch mode is used to replace the capacitor keeping mode of the traditional pixel circuit, so that the influence of the pixel circuit caused by the leakage can be reduced. The design of the pixel circuit provided by the utility model can realize that the area of a single pixel is less than 50um*50um, and the driving current can reach 2mA-3mA.

[0122] Further, the pixel circuit of the utility model is adopted in the transistor unit controlled by the PWM signal in the gating unit between the latch unit and the driving tube control end, so that the PWM dimming of each pixel circuit can be realized.

[0123] Further, the pixel circuit of the utility model also integrates the test unit, each pixel unit can control the test switch through the test row selection signal and the test column selection signal, so as to collect the output voltage and output to the outside of the pixel circuit array, so as to realize the output diagnosis of each pixel circuit.

[0124] Further, the pixel circuit of the utility model also integrates the static protection unit, so that the light emitting element is reduced in the process of sealing the pixel circuit array. Further, the reliability of the pixel circuit is improved.

[0125] Further, the driving signal in the pixel circuit of the present application adopts voltage (driving voltage, reference voltage) transmission, and the first bias unit is internally arranged to clamp the drain-source voltage between the reference transistor and the output transistor of each current mirror to be consistent, so that the reference current outside the array is more accurately imaged to the driving current in each pixel circuit, thereby greatly improving the influence of the output voltage on the driving current of the pixel circuit. Further, the driving signal in the pixel circuit of the present application adopts voltage transmission, and the driving signal is shared on the pixel circuit of the row or column, so that the voltage signal line (referring to the driving voltage line and the reference voltage line) of each row and each column is extremely small, which simplifies the layout design and is more conducive to small area integration.

[0126] Further, the driving signal in the pixel circuit of the present application adopts current transmission, and the second bias unit is arranged to make the driving current in each pixel circuit more accurate based on the received bias current. Further, the plurality of pixel circuits in the present application share one bias current generation circuit, so that the number of bias current lines from the array outside to the array inside is greatly reduced, which greatly reduces the difficulty of small area pixel circuit layout wiring, and further facilitates the area optimization of the pixel circuit and the array integration of the pixel circuit. BRIEF DESCRIPTION OF DRAWINGS

[0127] The above and other objects, features and advantages of the present application will become more apparent from the following description of the preferred embodiments of the present application with reference to the accompanying drawings, in which:

[0128] Figure 1 show a schematic diagram of a pixel circuit according to the first embodiment of the present application;

[0129] Figure 2 show another schematic diagram of a pixel circuit according to the first embodiment of the present application;

[0130] Figure 3 show a schematic diagram of a pixel circuit according to the second embodiment of the present application;

[0131] Figure 4 show another schematic diagram of a pixel circuit according to the second embodiment of the present application;

[0132] Figure 5 show a partial connection schematic diagram of the first bias unit in the pixel circuit according to the second embodiment of the present application and the external circuit;

[0133] Figure 6 show a schematic diagram of a pixel circuit according to the third embodiment of the present application;

[0134] Figure 7 show another schematic diagram of a pixel circuit according to the third embodiment of the present application;

[0135] Figure 8 Fig. 1 shows a circuit schematic diagram of a latch unit in a pixel circuit according to the first to third embodiments of the present application;

[0136] Figure 9 Fig. 2 shows another circuit schematic diagram of a latch unit in a pixel circuit according to the first to third embodiments of the present application;

[0137] Figure 10 Fig. 3 shows a circuit schematic diagram of an ESD protection unit in a pixel circuit according to the first to third embodiments of the present application;

[0138] Figure 11 Fig. 4 shows another circuit schematic diagram of an ESD protection unit in a pixel circuit according to the first to third embodiments of the present application;

[0139] Figure 12 Fig. 5 shows a structural schematic diagram of a pixel array in a pixel driving array according to the fourth embodiment of the present application;

[0140] Figure 13 Fig. 6 shows a timing schematic diagram of a pixel array in a pixel driving array according to the fourth embodiment of the present application;

[0141] Figure 14 Fig. 7 shows a schematic diagram of a bias current generation circuit in a pixel driving array according to the fifth embodiment of the present application;

[0142] Figure 15 Fig. 8 shows another schematic diagram of a bias current generation circuit in a pixel driving array according to the fifth embodiment of the present application;

[0143] Figure 16 Fig. 9 shows a structural schematic diagram of a pixel array in a pixel driving array according to the fifth embodiment of the present application. DETAILED DESCRIPTION

[0144] Various embodiments of the present application will be described in detail with reference to the drawings. In the drawings, like reference numerals refer to like elements throughout. For clarity, each part of the drawings is not drawn to scale.

[0145] The nTnC of the conventional pixel circuit adopts a capacitor storage voltage holding mode, so that the corresponding pixel unit maintains the newly written state in the entire frame period. However, the capacitor holding mode is easily affected by the leakage of transistors, or parasitic transistors or parasitic diodes, and the jump disturbance of the output voltage, especially for the application of each pixel in the vehicle headlamp requiring mA level driving current, the conventional pixel circuit cannot be applied.

[0146] The pixel circuit and the pixel driving array of the present application adopt a digital latch mode instead of a traditional capacitor holding mode, which can reduce the influence of leakage on the light emitting effect under the condition of meeting the mA level current demand.

[0147] Figure 1 A schematic diagram of a pixel circuit provided by the first embodiment of the present application is shown. Figure 8 A circuit schematic diagram of a latch unit in the pixel circuit provided by the first to third embodiments of the present application is shown. Figure 9 Another circuit schematic diagram of a latch unit in the pixel circuit provided by the first to third embodiments of the present application is shown. Figure 10 A circuit schematic diagram of an ESD protection unit in the pixel circuit provided by the first to third embodiments of the present application is shown. Figure 11 Another circuit schematic diagram of an ESD protection unit in the pixel circuit provided by the first to third embodiments of the present application is shown. Figure 13 A timing schematic diagram of a pixel array in the pixel driving array provided by the fourth embodiment of the present application is shown.

[0148] As shown in Figure 1 The pixel circuit 110 includes a latch unit 111, a gating unit 112, a driving tube M0, and a light emitting element 113.

[0149] The latch unit 111 receives a row control signal VClk-Row and a column control signal VData-Col, and latches the column control signal VData-Col based on the row control signal VClk-Row to output a first control signal VPWMn.

[0150] Further, the latch unit 111 receives the row control signal VClk-Row at a first level (for example, a low level), and the latch unit 111 outputs the inverted signal of the column control signal VData-Col as the first control signal VPWMn. The latch unit 111 receives the row control signal VClk-Row at a second level (for example, a high level), and the latch unit 111 outputs unchanged.

[0151] The latch unit 111 adopts a latch, the input end of the latch receives the column control signal VData-Col, the clock end of the latch receives the row control signal VClk-Row, and the output end of the latch outputs the first control signal VPWMn.

[0152] Exemplarily, in combination with Figure 8The latch unit 111 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4. The input of the first inverter INV1 receives the row control signal VClk-Row. The input of the second inverter INV2 receives the column control signal VData-Col. The enable terminal of the second inverter INV2 is connected to the output of the first inverter INV1, and the output of the second inverter INV2 outputs the first control signal VPWMn. The input of the third inverter INV3 is connected to the output of the second inverter INV2. The input of the fourth inverter INV4 is connected to the output of the third inverter INV3. The enable terminal of the fourth inverter INV4 receives the row control signal VClk-Row, and the output of the fourth inverter INV4 is connected to the output of the second inverter INV2.

[0153] In alternative embodiments, combined with Figure 9 The latch unit 211 includes a first inverter INV1, a fifth inverter INV5, a third inverter INV3, a sixth inverter INV6, a first switch S1, and a second switch S2. The input terminal of the first inverter INV1 receives the row control signal VClk-Row. The input terminal of the fifth inverter INV5 receives the column control signal VData-Col. The first terminal of the first switch S1 is connected to the output terminal of the fifth inverter INV5, and the control terminal of the first switch S1 is connected to the output terminal of the first inverter INV1. The input terminal of the third inverter INV3 is connected to the second terminal of the first switch S1 and outputs a first control signal VPWMn. The input terminal of the sixth inverter INV6 is connected to the output terminal of the third inverter INV3. The first terminal of the second switch S2 is connected to the output terminal of the sixth inverter INV6, the control terminal of the second switch S2 is connected to the input terminal of the first inverter INV1, and the second terminal of the second switch S2 is connected to the input terminal of the third inverter INV3.

[0154] The gating unit 112 is connected to the latching unit 111 and is turned on based on the received first control signal VPWMn to output the received drive signal. Further, the gating unit 112 includes a switching transistor controlled by the PWM signal. In this embodiment, the drive signal is an externally provided drive voltage Vgate.

[0155] The gating unit 112 includes a first NOT gate NOT1, a first transistor M1, a second transistor M2, and a third transistor M3. The first NOT gate NOT1 is connected to the latch unit 111 to receive the first control signal VPWMn, and outputs the second control signal VPWMp. The first transistor M1 receives the first control signal VPWMn at a control terminal, receives the driving signal at a first terminal, and is connected to the control terminal of the driving transistor M0 at a second terminal. The second transistor M2 receives the second control signal VPWMp at a control terminal, receives the driving signal at a first terminal, and is connected to the control terminal of the driving transistor M0 at a second terminal. The third transistor M3 receives the first control signal VPWMn at a control terminal, is connected to the control terminal of the driving transistor M0 at a first terminal, and is grounded at a second terminal.

[0156] The control terminal of the driving transistor M0 is connected to the gating unit 112 to receive the driving signal, so as to turn on or turn off the driving transistor M0. The first terminal of the driving transistor M0 provides the driving current as the output node OUT of the pixel circuit 110, and the second terminal of the driving transistor M0 is grounded.

[0157] The external light emitting element 113 is connected to the output node OUT to receive the driving current. The anode of the light emitting element 113 is connected to the power supply terminal to receive the power supply voltage VDDP, and the cathode of the light emitting element 113 is connected to the output node OUT.

[0158] The row control signal VClk-Row and the column control signal VData-Col pass through the latch unit 111. When the level of the row control signal VClk-Row is low, the second inverter INV2 normally works, the fourth inverter INV4 does not work, the column control signal VData-Col is written into the latch unit 111, and the first control signal VPWMn output by the latch unit 111 is inverted from the input column control signal VData-Col. When the level of the row control signal VClk-Row is high, the second inverter INV2 does not work, the fourth inverter INV4 normally works, the output terminal of the second inverter INV2 is in a high resistance state, the column control signal VData-Col is latched by the latch formed by the third inverter INV3 and the fourth inverter INV4, and the output terminal of the latch unit 111 maintains the previous state.

[0159] In an alternative embodiment, the row control signal VClk-Row and the column control signal VData-Col pass through the latch unit 211. When the level of the row control signal VClk-Row is low, the first switch S1 is turned on and the second switch S2 is turned off. The column control signal VData-Col is written into the latch unit 111, and the first control signal VPWMn output by the latch unit 211 is inverted with respect to the input column control signal VData-Col. When the level of the row control signal VClk-Row is high, the first switch S1 is turned off and the second switch S2 is turned on. The column control signal VData-Col is latched by the latch formed by the third inverter INV3 and the sixth inverter INV6, and the output end of the latch unit 211 maintains the previous state.

[0160] In the embodiment, the latch unit 111 and the latch unit 211 can be 1-bit latch units or multi-bit latch units. Preferably, 1-bit latch units are used in the embodiment because they use fewer signal lines, which is conducive to the integration of the pixel array.

[0161] In other embodiments, the pixel circuit 110 further includes a test unit 114 connected to the first end of the driving tube M0 and configured to determine whether to collect the output voltage VLED at the output node OUT according to the received test row selection signal Test-Row and the test column selection signal Test-Col.

[0162] Further, the test row selection signal Test-Row and the test column selection signal Test-Col pass through an AND logic circuit, and control the switch S in the test unit 114. The output voltage VLED in each pixel circuit 110 is time-multiplexed and output to the outside of the array through the switch S in the test unit 114, so that individual testing and diagnosis of each pixel circuit 110 can be achieved.

[0163] For example, the test unit 114 includes a switch S, an NAND gate, and a second NOT gate. The first end of the switch S is connected to the first end of the driving tube M0, and the second end of the switch S outputs the output voltage VLED. The first input end of the NAND gate receives the test row selection signal Test-Row, and the second input end of the NAND gate receives the test column selection signal Test-Col. The input end of the second NOT gate is connected to the output end of the NAND gate, and the output end of the second NOT gate is connected to the control end of the switch S.

[0164] In other embodiments, the pixel circuit 110 further includes an electrostatic protection unit 115 connected to the output node OUT and configured to form an electrostatic discharge path for the light emitting element 113.

[0165] For example, in combination with the pixel circuit 110, the display panel 100 further includes a plurality of pixel circuits 110 arranged in an array, and a plurality of test units 114 corresponding to the plurality of pixel circuits 110. Figure 10An electrostatic discharge (ESD) protection unit 115 includes a fifth transistor M5 and a sixth transistor M6. The first terminal of the fifth transistor M5 is connected to the output node OUT, and the second terminal of the fifth transistor M5 is connected to the control terminal and the power supply terminal. The first terminal of the sixth transistor M6 is connected to the first terminal of the fifth transistor M5, and the second terminal of the sixth transistor M6 is connected to the control terminal and grounded.

[0166] For example, combined Figure 11 Another electrostatic discharge (ESD) protection unit 215 includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the output node OUT, and the cathode of the first diode D1 is connected to the power supply terminal. The anode of the second diode D2 is grounded, and the cathode of the second diode D2 is connected to the anode of the first diode D1.

[0167] The diodes and transistors mentioned above can also be replaced with other devices that have ESD functionality.

[0168] In other embodiments, the pixel circuit 110 further includes a first resistor R1 connected between the first end of the driving transistor M0 and the output node OUT to further achieve electrostatic protection.

[0169] It should be noted that in this embodiment, the second transistor M2, the third transistor M3, and the driving transistor M0 are, for example, NMOS transistors, and the first transistor M1 is, for example, a PMOS transistor. The first terminal of the transistor is, for example, the drain terminal, the second terminal of the transistor is, for example, the source terminal, and the control terminal of the transistor is, for example, the gate terminal.

[0170] This embodiment provides a digital latching method to maintain normal voltage drive within a frame period, no longer affected by leakage current. Furthermore, the PWM signal output by the latching unit controls the control terminal of the transistor in the gating unit to further control the drive signal provided to the control terminal of the drive transistor M0, thereby achieving PWM dimming control.

[0171] In this embodiment, the driving current is the sink current provided by the driving transistor M0.

[0172] For example, the drive voltage Vgate is a constant voltage value. Figure 13As shown, when the control signal VClk-Row(i) of the i-th row is low and the control signal VData-Col(j) of the j-th row and column is high, the pixel circuit of the i-th row and j-th column is selected to work. When the second control signal VPWMp is high, and the row control signal VClk-Row(i+1) selects the next row (i+1 row), the current control signal VClk-Row(i) of the i-th row becomes high. The latch unit 111 or latch unit 211 of the i-th row latches the previous state. The second control signal VPWMp remains high. The gate voltage of the driving transistor M0 is equal to the driving voltage Vgate throughout the entire frame period. The driving current will be maintained throughout the entire frame period until the next frame period.

[0173] In other embodiments, if the column control signal VData-Col is a PWM square wave signal, the PWM dimming function can be implemented through the gating unit 112.

[0174] Figure 2 This illustration shows another schematic diagram of a pixel circuit provided according to a first embodiment of this application.

[0175] like Figure 2 As shown, the difference between pixel circuit 120 and pixel circuit 110 is that the driving current of light-emitting element 113 is the current of the second terminal provided by driving transistor M0.

[0176] Correspondingly, in this embodiment, the first transistor M1, the third transistor M3, and the driving transistor M0 are, for example, PMOS transistors, and the second transistor M2 is, for example, an NMOS transistor.

[0177] The gating unit 122 in the pixel circuit 120 includes a first NOT gate (NOT1), a first transistor M1, a second transistor M2, and a third transistor M3. The input terminal of the first NOT gate (NOT1) is connected to the latch unit 111 to receive a first control signal VPWMn, and the output terminal of the first NOT gate (NOT1) outputs a second control signal VPWMp. The control terminal of the first transistor M1 receives the first control signal VPWMn, the first terminal of the first transistor M1 receives a drive signal, and the second terminal of the first transistor M1 is connected to the control terminal of the drive transistor M0. The control terminal of the second transistor M2 receives the second control signal VPWMp, the first terminal of the second transistor M2 receives the drive signal, and the second terminal of the second transistor M2 is connected to the control terminal of the drive transistor M0. The control terminal of the third transistor M3 receives the second control signal VPWMp, the first terminal of the third transistor M3 is connected to the control terminal of the drive transistor M0, and the second terminal of the third transistor M3 is connected to the power supply terminal.

[0178] The control terminal of the driving transistor M0 is connected to the gating unit 122 to receive the driving signal, so as to turn the driving transistor M0 on or off. The first terminal of the driving transistor M0 serves as the output node OUT of the pixel circuit 110 to provide driving current, and the second terminal of the driving transistor M0 is connected to the power supply terminal.

[0179] An external light-emitting element 113 is connected to the output node OUT and receives drive current. Exemplarily, the anode of the light-emitting element 113 is connected to the output node OUT, and the cathode of the light-emitting element 113 is grounded.

[0180] The pixel circuit provided in the first embodiment of this application can realize individual control of pixels, PWM dimming function, and ESD protection of output node OUT. At the same time, the drive signal from outside the array to inside the array adopts the drive voltage Vgate transmission method. Each pixel circuit can share the same drive voltage Vgate. The drive voltage Vgate can be shared during array wiring or row and column wiring, which greatly reduces the number of traces, the area required for wiring, and the complexity of wiring, which is beneficial for the integration of small-area pixel arrays.

[0181] Figure 3 A schematic diagram of a pixel circuit provided according to a second embodiment of this application is shown. Figure 4 This illustrates another schematic diagram of a pixel circuit provided according to a second embodiment of the present application. Figure 5 This diagram illustrates a partial connection between the first bias unit and the external circuit in a pixel circuit according to a second embodiment of this application.

[0182] Compared to the first embodiment, the second embodiment adds a first bias unit to the pixel circuit, which receives the driving voltage, reference voltage, first terminal voltage of the driving transistor, and generates a driving signal and a first bias current. The driving signal is provided to the control terminal of the driving transistor via a gating unit, and the driving current is adjusted based on the first bias current.

[0183] like Figure 3As shown, the first bias unit 216 in the pixel circuit 210 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a first operational amplifier AMP1, and a second operational amplifier AMP2. The control terminal of the seventh transistor M7 receives the driving voltage Vgate, the second terminal of the seventh transistor M7 is connected to the power supply terminal, and the first terminal of the seventh transistor M7 outputs a first bias current IREF1. The first input terminal (non-inverting input terminal) of the first operational amplifier AMP1 receives the reference voltage VB, and the second input terminal (inverting input terminal) of the first operational amplifier AMP1 is connected to the first terminal of the seventh transistor M7. The control terminal of the eighth transistor M8 is connected to the output terminal of the first operational amplifier AMP1, and the second terminal of the eighth transistor M8 is connected to the first terminal of the seventh transistor M7. The first input terminal (non-inverting input terminal) of the second operational amplifier AMP2 is connected to the first terminal of the eighth transistor M8, and the second input terminal (inverting input terminal) of the second operational amplifier AMP2 is connected to the drain terminal of the driving transistor M0. The control terminal of the ninth transistor M9 is connected to the output terminal of the second operational amplifier AMP2 and outputs a drive signal. The first terminal of the ninth transistor M9 is connected to the first terminal of the eighth transistor M8, and the second terminal of the ninth transistor M9 is grounded.

[0184] like Figure 4 As shown, the first bias unit 226 in the pixel circuit 220 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a first operational amplifier AMP1, and a second operational amplifier AMP2. The control terminal of the seventh transistor M7 receives the driving voltage Vgate, the second terminal of the seventh transistor M7 is grounded, and the first terminal of the seventh transistor M7 outputs a first bias current IREF1. The first input terminal of the first operational amplifier AMP1 receives the reference voltage VB, and the second input terminal of the first operational amplifier AMP1 is connected to the first terminal of the seventh transistor M7. The control terminal of the eighth transistor M8 is connected to the output terminal of the first operational amplifier AMP1, and the second terminal of the eighth transistor M8 is connected to the first terminal of the seventh transistor M7. The first input terminal of the second operational amplifier AMP2 is connected to the first terminal of the eighth transistor M8, and the second input terminal of the second operational amplifier AMP2 is connected to the drain terminal of the driving transistor M0. The control terminal of the ninth transistor M9 is connected to the output terminal of the second operational amplifier AMP2 and outputs a driving signal. The first terminal of the ninth transistor M9 is connected to the first terminal of the eighth transistor M8, and the second terminal of the ninth transistor M9 is connected to a current source to receive the power supply voltage VDDP.

[0185] like Figure 5As shown, the external driving voltage and reference voltage generation circuit 550 of the pixel circuit array provides the driving voltage Vgate and the reference voltage VB. The first terminal of transistor M5A is grounded via current source J1, the second terminal of transistor M5A is connected to the power supply terminal, and the control terminal of transistor M5A is connected to its first terminal and provides the driving voltage Vgate. The first terminal of transistor M5A provides the reference voltage VB.

[0186] If the drive voltage Vgate generated by the drive voltage and reference voltage generation circuit 550 directly drives the drive transistor M0 in the diagram, then when the source-drain voltage of transistor M5A, which generates the reference current IREF0 in the drive voltage and reference voltage generation circuit 550, is equal to the... Figure 1 and Figure 2 When the source and drain voltages of the driving transistor M0 are mismatched, the driving current in the driving transistor M0 of each pixel circuit will deviate significantly from the reference current IREF0.

[0187] Furthermore, in this embodiment, the seventh transistor M7 in the first bias unit 216 / 226 and the transistor M5A in the driving voltage and reference voltage generation circuit 550 form a current mirror, which is clamped by an operational amplifier to make the driving current closer to the first bias current IREF1, and thus closer to the reference current IREF0. That is, the first bias unit can make the driving current in the pixel circuit more accurate.

[0188] For example, in this embodiment, the first operational amplifier AMP1 clamps the drain of the seventh transistor M7 through the eighth transistor M8, thereby making the drain-source voltage of transistor M5A and the drain-source voltage of the seventh transistor M7 in the pixel circuit essentially the same, thus reducing the possibility of current mismatch caused by the difference in drain-source voltage. Furthermore, the second operational amplifier AMP2 clamps the drain-source voltages of the ninth transistor M9 and the driving transistor M0 to the same voltage, ensuring accurate replication of the driving current mirrored by the ninth transistor M9 into the driving transistor M0, thereby improving the matching degree and uniformity of the driving current in the array pixel circuit of the pixel driving array.

[0189] Figure 6 A schematic diagram of a pixel circuit provided according to a third embodiment of this application is shown. Figure 7 This illustrates another schematic diagram of a pixel circuit provided according to a third embodiment of this application.

[0190] Compared to the first embodiment, the third embodiment adds a second bias unit to the pixel circuit, which receives the second bias current and the first terminal voltage of the driving transistor, generates a driving signal to be provided to the control terminal of the driving transistor via the gating unit, and adjusts the driving current based on the second bias current.

[0191] like Figure 6As shown, the second bias unit 316 in the pixel circuit 310 includes a tenth transistor M10 and a third operational amplifier AMP3. The first input terminal (non-inverting input terminal) of the third operational amplifier AMP3 receives a second bias current IREF2, and the second input terminal (inverting input terminal) of the third operational amplifier AMP3 is connected to the drain terminal of the driving transistor M0. The control terminal of the tenth transistor M10 is connected to the output terminal of the third operational amplifier AMP3 and outputs a driving signal. The first terminal of the tenth transistor M10 receives the second bias current IREF2, and the second terminal of the tenth transistor M10 is grounded.

[0192] like Figure 7 As shown, the second bias unit 326 in the pixel circuit 320 includes a tenth transistor M10 and a third operational amplifier AMP3. The first input terminal (non-inverting input terminal) of the third operational amplifier AMP3 receives a second bias current IREF2, and the second input terminal (inverting input terminal) of the third operational amplifier AMP3 is connected to the drain terminal of the driving transistor M0. The control terminal of the tenth transistor M10 is connected to the output terminal of the third operational amplifier AMP3 and outputs a driving signal. The first terminal of the tenth transistor M10 receives the second bias current IREF2, and the second terminal of the tenth transistor M10 is connected to the power supply terminal.

[0193] In this embodiment, the third operational amplifier AMP3 is used to clamp the drain-source voltages of the tenth transistor M10 and the driving transistor M0 to the same voltage, so as to ensure the accurate replication of the driving current mirrored by the tenth transistor M10 to the driving transistor M0, thereby improving the matching degree and uniformity of the driving current of the pixel circuit in the pixel driving array.

[0194] In this embodiment, the driving signal for each pixel circuit is input from outside the array via current transmission. The magnitude of the current signal will not change due to the distance of transmission. The current transmission design enables precise matching of the driving current between each pixel in the array, thereby improving the array current uniformity.

[0195] Figure 12 This diagram illustrates the structure of a pixel array in a pixel driving array according to a fourth embodiment of this application. Figure 13 This diagram illustrates the timing of the pixel array in the pixel driving array according to the fourth embodiment of this application.

[0196] like Figure 12 As shown, the pixel driving array includes multiple scan lines, multiple data lines, multiple pixel circuits 210 or 220 arranged in an array, row control circuit 410, and column control circuit 420.

[0197] The row control circuit 410 is connected to the pixel circuit of the corresponding row via each scan line to provide the corresponding row control signal (VClk-Row1, VClk-Row2...VClk-Row). The column control circuit 420 is connected to the pixel circuit of the corresponding column via each data line to provide the corresponding column control signal (VData-Col1, VData-Col2...VData-Col1).

[0198] Furthermore, it also includes multiple first test lines, multiple second test lines, multiple third test lines, and a test circuit 440. The test circuit 440 is connected to the pixel circuit of the corresponding row via each first test line to provide the corresponding test row strobe signal (Test-Row1, Test-Row2...Test-Rown), and is connected to the pixel circuit of the corresponding column via each second test line to provide the corresponding test column strobe signal (Test-Col1, Test-Col2...Test-Colm), and receives multiple output voltages VLED from the pixel circuit of the corresponding row or column via each third test line.

[0199] Furthermore, it also includes multiple driving voltage lines, multiple reference voltage lines, driving voltage and reference voltage generation circuits 450, the driving voltage and reference voltage generation circuits 450 being connected to the pixel circuits of the corresponding row or corresponding column via each driving voltage line to provide a driving voltage Vgate, and the driving voltage and reference voltage generation circuits 450 being connected to the pixel circuits of the corresponding row or corresponding column via each reference voltage line to provide a reference voltage VB.

[0200] For example, multiple drive voltage and reference voltage generation circuits 550 are integrated in the drive voltage and reference voltage generation circuit 450, such that each drive voltage and reference voltage generation circuit 550 provides a drive voltage Vgate and a reference voltage VB to a row or column of pixel circuits. In an alternative embodiment, for example, a single drive voltage and reference voltage generation circuit 550 is integrated in the drive voltage and reference voltage generation circuit 450, such that pixel circuits in the array share a single drive voltage Vgate and a single reference voltage VB.

[0201] In other embodiments, the pixel circuit in the pixel driving array may be, for example, pixel circuit 110 or pixel circuit 120. Furthermore, the driving voltage and reference voltage generation circuit 450 only provides the driving voltage Vgate to the pixel circuit.

[0202] Preferably, each pixel circuit in the pixel driving array of this embodiment can be implemented within an integration area of ​​40um × 40um.

[0203] like Figure 13As shown, in conjunction with the latch unit in the pixel circuit, the driving current of each pixel circuit can maintain its original state within the corresponding frame period. For example, when the first row control signal Vclk-Row1 is low, data writing is performed, writing new data VData-Col1 to VData-Colm to the m pixel circuits in the first row of columns 1 to m, refreshing them to a new state. For example, the first control signal output by the latch unit is the inverted signal of the column control signal. Taking pixel circuit 210 as an example, when the column control signal is low, transistor M3 is pulled low, and driving transistor M0 is turned off. When the column control signal is high, transistor M3 is turned off, and driving transistor M0 receives the driving signal and turns on. When the first row control signal Vclk-Row1 changes from low to high, data latching is performed, and the latch unit latches the new data state. The first control signal output by the latch unit maintains the previous state. When the next row control signal Vclk-Row2 is low, data is written, writing new data VData-Col1 to VData-Colm to the corresponding m pixels in the second row of columns 1 to m, refreshing them to a new state. After the second row control signal Vclk-Row2 changes from low to high, data latching occurs, and the latch unit latches the new data state. This process continues until the last row and the nth row are refreshed, completing one frame's data refresh. Then, a new frame cycle repeats. During each frame cycle, while data is being written to one row, the other rows are held in their previous state by the digital latch unit.

[0204] Figure 14 A schematic diagram of a bias current generation circuit in a pixel driving array according to a fifth embodiment of this application is shown. Figure 15 A schematic diagram of another bias current generation circuit in a pixel driving array according to a fifth embodiment of this application is shown. Figure 16 This diagram illustrates the structure of a pixel array in a pixel driving array according to a fifth embodiment of this application.

[0205] like Figure 16 As shown, the pixel driving array provided in the fifth embodiment replaces the pixel circuit with pixel circuit 310 / 320 based on the fourth embodiment, and replaces the driving voltage and reference voltage generation circuit 450 with reference current generation circuit 430. Furthermore, the pixel driving array provided in the fifth embodiment also includes multiple bias current generation circuits 650 / 750.

[0206] like Figure 14 As shown, the bias current generating circuit 650 generates k bias currents (IREF2-1, IREF2-2...IREF2-k) to provide to k pixel circuits 310. Each bias current is provided to the corresponding pixel circuit 310 via a bias current line, where k is a positive integer.

[0207] Furthermore, the bias current generating circuit 650 includes a reference unit and k output units. Each output unit and the reference unit form a current mirror circuit to provide multiple different bias circuits by setting corresponding mirror ratios. The reference unit includes transistors M11-0 and M12-0. The control terminal of transistor M11-0 is connected to its first terminal, and the second terminal of transistor M11-0 is connected to the power supply terminal to receive the power supply voltage VDDP. The second terminal of transistor M12-0 is connected to the first terminal of transistor M11-0, and the control terminal of transistor M12-0 is connected to its first terminal and grounded via current source J2, and receives the reference current IREF0. Each output unit includes transistors M11-g and M12-g, where g is 1, 2...k. The control terminal of transistor M11-g is connected to the control terminal of transistor M11-0. The second terminal of transistor M11-g is connected to the power supply terminal to receive the power supply voltage VDDP. The second terminal of transistor M12-g is connected to the first terminal of transistor M11-g. The control terminal of transistor M12-g is connected to the control terminal of transistor M12-0. The first terminal of transistor M12-g is connected to the corresponding pixel circuit 310 to output the second bias current IREF2-g. For example, the above transistors are PMOS transistors.

[0208] like Figure 15 As shown, the bias current generating circuit 750 generates k bias currents (IREF2-1, IREF2-2...IREF2-k) to provide to k pixel circuits 310 / 320. Each bias current is provided to the corresponding pixel circuit 310 / 320 via a bias current line, where k is a positive integer.

[0209] Furthermore, the bias current generating circuit 750 includes a reference unit and k output units. Each output unit and the reference unit form a current mirror circuit to provide multiple different bias circuits by setting corresponding mirror ratios. The reference unit includes transistors M11-0 and M12-0. The control terminal of transistor M11-0 is connected to its first terminal, and the second terminal of transistor M11-0 is grounded. The second terminal of transistor M12-0 is connected to the first terminal of transistor M11-0. The control terminal of transistor M12-0 is connected to its first terminal and connected to the power supply terminal via current source J3. The first terminal of transistor M12-0 receives the reference current IREF0. Each output unit includes transistors M11-g and M12-g, where g is 1, 2, ..., k. The control terminal of transistor M11-g is connected to the control terminal of transistor M11-0, the second terminal of transistor M11-g is grounded, the second terminal of transistor M12-g is connected to the first terminal of transistor M11-g, the control terminal of transistor M12-g is connected to the control terminal of transistor M12-0, and the first terminal of transistor M12-g is connected to the corresponding pixel circuit 310 / 320 to output the second bias current IREF2-g. For example, the above transistors are NMOS transistors.

[0210] The reference current generation circuit 430 provides, for example, n reference currents (IREF0(1), IREF0(2), ..., IREF0(n)) to the bias current generation circuit 650 / 750.

[0211] In the fifth embodiment, a single bias current generation circuit 650 / 750 is used to multiplex k pixel circuits. The bias current generation circuit 650 / 750 receives a reference current IREF0 via a current mirror, generating a second bias current of the same or different magnitudes. When all k pixel circuits require the same second bias current, the mirror ratio of the current mirror is set to the same ratio. By placing the relatively large current source J3 in the reference current generation circuit outside the pixel array, and by sharing a single bias current generation circuit 650 / 750 with all or part of the pixel circuits in each row, both the area of ​​the pixel array and the wiring between the pixel array and the external reference current generation circuit are reduced.

[0212] When k pixel circuits require the same second bias current, the current mirror structure of the bias current generation circuit is designed in a cascade form, reducing the impact of drain-source voltage on the output current and ensuring the accuracy of the current mirror. If k equals 10, taking 10 pixel circuits as a group as an example, the current signal lines in this embodiment will become one-tenth of the original, greatly reducing the difficulty of layout and routing, reducing the trace area, and is very beneficial for the integration of small-area pixel unit circuit arrays. k can take different values ​​depending on the actual situation, such as 4, 5, 8, etc. That is, when the pixel array is relatively large, the pixel circuits in each row can be divided into at least two groups, and each group of pixel circuits shares a corresponding bias current generation circuit 650 / 750.

[0213] The pixel circuit design of this application can be implemented within an integration area of ​​30um*30um~50um×50um to provide a driving current of 2~3mA to a single light-emitting element (MicroLED).

[0214] The pixel circuit and pixel driving array provided by this utility model, by setting up a latching unit, enable each pixel to maintain its position for the entire frame period after the corresponding driving current is written. In other words, this application uses digital latching instead of the traditional capacitor-based pixel circuit, which reduces the impact of leakage current on the pixel circuit. The pixel circuit design provided by this application can achieve a single pixel area of ​​less than 50µm × 50µm and a driving current of 2mA~3mA.

[0215] Furthermore, the pixel circuit of this application incorporates a transistor unit controlled by a PWM signal in series in the gating unit between the latch unit and the drive transistor control terminal, which can realize PWM dimming of each pixel circuit.

[0216] Furthermore, the pixel circuit of this application also integrates a test unit. Each pixel unit can control a test switch through a test row strobe signal and a test column strobe signal to acquire the output voltage and output it to the outside of the pixel circuit array, so as to realize the output diagnosis of each pixel circuit.

[0217] Furthermore, the pixel circuit of this application also integrates an electrostatic protection unit, which reduces the electrostatic damage to the light-emitting elements during the pixel circuit array sealing process, thereby improving the reliability of the pixel circuit.

[0218] Furthermore, the driving signals in the pixel circuit of this application are transmitted using voltage (driving voltage, reference voltage), and the drain-source voltage between the reference transistor and the output transistor of each current mirror is clamped to be consistent through an internally configured first bias unit. This makes the mirroring of the external reference current to the driving current in each pixel circuit more accurate, thereby greatly improving the effect of the output voltage on the driving current of the pixel circuit. Furthermore, the driving signals in the pixel circuit of this application are transmitted using voltage, and by sharing the driving signals on the pixel circuits in rows or columns, the number of voltage signal lines (driving voltage lines, reference voltage lines) in each row and column is minimized, simplifying the layout design and facilitating small-area integration.

[0219] Furthermore, the driving signal in the pixel circuit of this application uses current transmission, and by setting a second bias unit, the driving current in each pixel circuit is made more accurate based on the received bias current. Furthermore, multiple pixel circuits in this application reuse a single bias current generation circuit, which greatly reduces the number of bias current lines from outside the pixel circuit array to inside the array, significantly reducing the difficulty of layout and routing of small-area pixel circuits, thereby facilitating pixel circuit area optimization and array integration.

[0220] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to effectively utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A pixel circuit, characterized in that, include: The latching unit receives a row control signal and a column control signal, and latches the column control signal based on the row control signal to output a first control signal; The gating unit is connected to the latching unit and controls the conduction based on the received first control signal to output the received drive signal; A driving transistor, the control terminal of which is connected to the gating unit to receive the driving signal, so as to turn the driving transistor on or off. The first end of the driving transistor serves as the output node of the pixel circuit, and the output node provides driving current.

2. The pixel circuit according to claim 1, characterized in that, The output node is connected to an external light-emitting element, which receives the driving current.

3. The pixel circuit according to claim 1, characterized in that, Also includes: The test unit is connected to the first end of the drive transistor and determines whether to acquire the output voltage at the output node based on the received test row strobe signal and test column strobe signal.

4. The pixel circuit according to claim 1, characterized in that, Also includes: An electrostatic discharge protection unit is connected to the output node to form an electrostatic discharge path for the light-emitting element.

5. The pixel circuit according to claim 1, characterized in that, Also includes: The first bias unit receives the drive voltage, the reference voltage, and the first terminal voltage of the drive transistor, generates the drive signal and the first bias current, provides the drive signal to the control terminal of the drive transistor via the gating unit, and adjusts the drive current based on the first bias current.

6. The pixel circuit according to claim 1, characterized in that, Also includes: The second bias unit receives the second bias current and the first terminal voltage of the driving transistor, generates the driving signal to be provided to the control terminal of the driving transistor via the gating unit, and adjusts the driving current based on the second bias current.

7. The pixel circuit according to claim 1, characterized in that, The driving signal is a driving voltage provided externally to the pixel circuit.

8. The pixel circuit according to claim 1, characterized in that, The latch unit receives the row control signal at a first level, and outputs the inverted signal of the column control signal as the first control signal. The latch unit receives the row control signal at the second level, and the output of the latch unit remains unchanged.

9. The pixel circuit according to claim 2, characterized in that, The gating unit includes: The first NOT gate has its input connected to the latch unit to receive the first control signal, and its output output is the second control signal. A first transistor, wherein the control terminal of the first transistor receives the first control signal, the first terminal of the first transistor receives the drive signal, and the second terminal of the first transistor is connected to the control terminal of the drive transistor; The second transistor has a control terminal that receives the second control signal, a first terminal that receives the drive signal, and a second terminal that is connected to the control terminal of the drive transistor. The third transistor has a control terminal that receives the first control signal, a first terminal that is connected to the control terminal of the driving transistor, and a second terminal that is grounded. The second end of the driving tube is grounded, the anode of the light-emitting element is connected to the power supply terminal, and the cathode of the light-emitting element is connected to the output node.

10. The pixel circuit according to claim 2, characterized in that, The gating unit includes: The first NOT gate has its input connected to the latch unit to receive the first control signal, and its output output is the second control signal. A first transistor, wherein the control terminal of the first transistor receives the first control signal, the first terminal of the first transistor receives the drive signal, and the second terminal of the first transistor is connected to the control terminal of the drive transistor; The second transistor has a control terminal that receives the second control signal, a first terminal that receives the drive signal, and a second terminal that is connected to the control terminal of the drive transistor. The third transistor has a control terminal that receives the second control signal, a first terminal that is connected to the control terminal of the driving transistor, and a second terminal that is connected to the power supply terminal. The second end of the driving tube is connected to the power supply terminal, the anode of the light-emitting element is connected to the output node, and the cathode of the light-emitting element is grounded.

11. The pixel circuit according to claim 4, characterized in that, The electrostatic protection unit includes: A fifth transistor, wherein a first terminal of the fifth transistor is connected to the output node, and a second terminal of the fifth transistor is connected to the control terminal of the fifth transistor and to the power supply terminal; and The sixth transistor has its first terminal connected to the first terminal of the fifth transistor, and its second terminal connected to the control terminal of the sixth transistor and grounded.

12. The pixel circuit according to claim 4, characterized in that, The electrostatic protection unit includes: A first diode, the anode of which is connected to the output node, and the cathode of which is connected to the power supply terminal; and The second diode has its anode grounded and its cathode connected to the anode of the first diode.

13. The pixel circuit according to claim 1, characterized in that, Also includes A first resistor is connected between the first end of the driving transistor and the output node.

14. The pixel circuit according to claim 8, characterized in that, The latch unit includes: A first inverter, the input of which receives the row control signal; The second inverter receives the column control signal at its input terminal, its enable terminal is connected to the output terminal of the first inverter, and its output terminal outputs the first control signal. A third inverter, wherein the input terminal of the third inverter is connected to the output terminal of the second inverter; The fourth inverter has its input terminal connected to the output terminal of the third inverter, its enable terminal receiving the row control signal, and its output terminal connected to the output terminal of the second inverter.

15. The pixel circuit according to claim 8, characterized in that, The latch unit includes: A first inverter, the input of which receives the row control signal; The fifth inverter receives the column control signal at its input terminal; A first switch, the first end of the first switch is connected to the output end of the fifth inverter, and the control end of the first switch is connected to the output end of the first inverter; The third inverter has its input terminal connected to the second terminal of the first switch and outputs the first control signal. A sixth inverter, the input of which is connected to the output of the third inverter; and The second switch has its first terminal connected to the output terminal of the sixth inverter, its control terminal connected to the input terminal of the first inverter, and its second terminal connected to the input terminal of the third inverter.

16. A pixel driving array, characterized in that, include: Multiple scan lines; Multiple data cables; Pixel circuits arranged in multiple arrays; The row control circuit is connected to the pixel circuit of the corresponding row via each scan line to provide the corresponding row control signal; The column control circuit is connected to the pixel circuit of the corresponding column via each data line to provide the corresponding column control signal. Each pixel circuitry includes: The latching unit receives the row control signal and the column control signal, and latches the column control signal based on the row control signal to output a first control signal; The gating unit is connected to the latching unit and controls the conduction based on the received first control signal to output the received drive signal; A driving transistor, the control terminal of which is connected to the gating unit to receive the driving signal, so as to turn the driving transistor on or off. The first end of the driving transistor serves as the output node of the pixel circuit, and the output node provides driving current.

17. The pixel driving array according to claim 16, characterized in that, The integrated area of ​​a single pixel circuit is less than 50um × 50um.

18. The pixel driving array according to claim 16, characterized in that, Also includes: Multiple first test lines; Multiple second test lines; Multiple third test lines; as well as The test circuit is connected to the pixel circuit of the corresponding row via each first test line to provide the corresponding test row strobe signal, connected to the pixel circuit of the corresponding column via each second test line to provide the corresponding test column strobe signal, and receives multiple output voltages of the pixel circuit of the corresponding row or column via each third test line.

19. The pixel driving array according to claim 16, characterized in that, Also includes: Multiple drive voltage lines; Multiple reference voltage lines; The driving voltage and reference voltage generation circuits are connected to the pixel circuits of the corresponding row or column via each driving voltage line to provide a driving voltage, and to the pixel circuits of the corresponding row or column via each reference voltage line to provide a reference voltage.

20. The pixel driving array according to claim 16, characterized in that, Also includes: Multiple current signal lines; The reference current generation circuit is connected to the bias current generation circuit of the corresponding row or column via each current signal line to provide a reference current. Multiple bias current generating circuits, each generating k bias currents to supply to k pixel circuits, each bias current being supplied to the corresponding pixel circuit via a bias current line, where k is a positive integer.

21. The pixel driving array according to claim 16, characterized in that, The output node is connected to an external light-emitting element, which receives the driving current.

22. The pixel driving array according to claim 16, characterized in that, Also includes: The test unit is connected to the first end of the drive transistor and determines whether to acquire the output voltage at the output node based on the received test row strobe signal and test column strobe signal.

23. The pixel driving array according to claim 16, characterized in that, Also includes: An electrostatic discharge protection unit is connected to the output node to form an electrostatic discharge path for the light-emitting element.

24. The pixel driving array according to claim 16, characterized in that, Also includes: The first bias unit receives the drive voltage, the reference voltage, and the first terminal voltage of the drive transistor, generates the drive signal and the first bias current, provides the drive signal to the control terminal of the drive transistor via the gating unit, and adjusts the drive current based on the first bias current.

25. The pixel driving array according to claim 16, characterized in that, Also includes: The second bias unit receives the second bias current and the first terminal voltage of the driving transistor, generates the driving signal to be provided to the control terminal of the driving transistor via the gating unit, and adjusts the driving current based on the second bias current.

26. The pixel driving array according to claim 16, characterized in that, The driving signal is a driving voltage provided externally to the pixel circuit.

27. The pixel driving array according to claim 16, characterized in that, The latch unit receives the row control signal at a first level, and outputs the inverted signal of the column control signal as the first control signal. The latch unit receives the row control signal at the second level, and the output of the latch unit remains unchanged.

28. The pixel driving array according to claim 21, characterized in that, The gating unit includes: The first NOT gate has its input connected to the latch unit to receive the first control signal, and its output output is the second control signal. A first transistor, wherein the control terminal of the first transistor receives the first control signal, the first terminal of the first transistor receives the drive signal, and the second terminal of the first transistor is connected to the control terminal of the drive transistor; The second transistor has a control terminal that receives the second control signal, a first terminal that receives the drive signal, and a second terminal that is connected to the control terminal of the drive transistor. The third transistor has a control terminal that receives the first control signal, a first terminal that is connected to the control terminal of the driving transistor, and a second terminal that is grounded. The source end of the driving transistor is grounded, the anode of the light-emitting element is connected to the power supply, and the cathode of the light-emitting element is connected to the output node.

29. The pixel driving array according to claim 21, characterized in that, The gating unit includes: The first NOT gate has its input connected to the latch unit to receive the first control signal, and its output output is the second control signal. A first transistor, wherein the control terminal of the first transistor receives the first control signal, the first terminal of the first transistor receives the drive signal, and the second terminal of the first transistor is connected to the control terminal of the drive transistor; The second transistor has a control terminal that receives the second control signal, a first terminal that receives the drive signal, and a second terminal that is connected to the control terminal of the drive transistor. The third transistor has a control terminal that receives the second control signal, a first terminal that is connected to the control terminal of the driving transistor, and a second terminal that is connected to the power supply terminal. The source end of the driving transistor is connected to the power supply end, the anode of the light-emitting element is connected to the output node, and the cathode of the light-emitting element is grounded.

30. The pixel driving array according to claim 23, characterized in that, The electrostatic protection unit includes: A fifth transistor, wherein a first terminal of the fifth transistor is connected to the output node, and a second terminal of the fifth transistor is connected to the control terminal of the fifth transistor and to the power supply terminal; and The sixth transistor has its first terminal connected to the first terminal of the fifth transistor, and its second terminal connected to the control terminal of the sixth transistor and grounded.

31. The pixel driving array according to claim 23, characterized in that, The electrostatic protection unit includes: A first diode, the anode of which is connected to the output node, and the cathode of which is connected to the power supply terminal; and The second diode has its anode grounded and its cathode connected to the anode of the first diode.

32. The pixel driving array according to claim 16, characterized in that, Also includes A first resistor is connected between the first end of the driving transistor and the output node.

33. The pixel driving array according to claim 27, characterized in that, The latch unit includes: A first inverter, the input of which receives the row control signal; The second inverter receives the column control signal at its input terminal, its enable terminal is connected to the output terminal of the first inverter, and its output terminal outputs the first control signal. A third inverter, wherein the input terminal of the third inverter is connected to the output terminal of the second inverter; The fourth inverter has its input terminal connected to the output terminal of the third inverter, its enable terminal receiving the row control signal, and its output terminal connected to the output terminal of the second inverter.

34. The pixel driving array according to claim 27, characterized in that, The latch unit includes: A first inverter, the input of which receives the row control signal; The fifth inverter receives the column control signal at its input terminal; A first switch, the first end of the first switch is connected to the output end of the fifth inverter, and the control end of the first switch is connected to the output end of the first inverter; The third inverter has its input terminal connected to the second terminal of the first switch and outputs the first control signal. A sixth inverter, the input of which is connected to the output of the third inverter; and The second switch has its first terminal connected to the output terminal of the sixth inverter, its control terminal connected to the input terminal of the first inverter, and its second terminal connected to the input terminal of the third inverter.

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