Protection circuit, battery management system, battery pack and electric equipment

Abstract

A protection circuit comprises a control unit, a watchdog, a first power supply, a second power supply, a first switch unit, an analog front-end chip and a second switch unit. The first power supply is electrically connected with the control unit, the second power supply is electrically connected with the watchdog, the control unit is electrically connected with the watchdog, and the watchdog comprises an enabling pin and an output pin. The first switch unit is electrically connected with the first power supply, the second power supply, the output pin and the grounding end. The analog front-end chip is electrically connected with the second switch unit, and the second switch unit is electrically connected with the second power supply, the enabling pin and the grounding end. The first power source is configured to power the control unit. The second power source is configured to power the watchdog. The first switch unit is configured to respond to the condition that the watchdog does not receive the dog feeding signal within the preset time, and the first switch unit is conducted to electrically connect the first power supply to the grounding end.

Description

Technical Field

[0001] This application relates to the field of battery technology, and more particularly to a protection circuit, a battery management system, a battery pack, and an electrical device. Background Technology

[0002] In the battery management system architecture, the microcontroller (MCU) plays a crucial role as the control center.

[0003] However, when faced with challenges from the external environment, such as electrostatic discharge interference, unstable fluctuations in power supply voltage, or large current pulse impacts caused by inductive loads at the moment of initial power-on, the MCU may experience latch-up. When the MCU is in a latch-up state, its internal circuitry may short-circuit, potentially causing permanent damage to the MCU chip. Utility Model Content

[0004] In a first aspect, embodiments of this application provide a protection circuit, which includes a control unit, a watchdog timer, a first power supply, a second power supply, a first switching unit, an analog front-end chip, and a second switching unit. The first power supply is electrically connected to the control unit, and the second power supply is electrically connected to the watchdog timer. The watchdog timer includes an enable pin and an output pin. The first switching unit is electrically connected to the first power supply, the second power supply, the output pin, and a ground terminal, respectively. The analog front-end chip is electrically connected to the second switching unit, and the second switching unit is electrically connected to the second power supply, the enable pin, and a ground terminal. The first power supply is configured to power the control unit, and the second power supply is configured to power the watchdog timer. The first switching unit is configured to turn on to electrically connect the first power supply to the ground terminal in response to the watchdog timer not receiving a feed signal within a preset time.

[0005] By setting up a watchdog timer and a first switch unit, when a latch-up effect occurs in the control unit, the power supply (first power supply) of the control unit is grounded, thereby disconnecting the power supply to the control unit and preventing damage to the control unit due to a latch-up effect, thus improving the reliability and stability of the battery management system.

[0006] In one or more embodiments, the first switching unit includes: a first switch, a second switch, a first resistor, a second resistor, a third resistor, and a fourth resistor. A first terminal of the fourth resistor is electrically connected to an output pin, and a second terminal of the fourth resistor is electrically connected to both the first terminal of the second resistor and the first terminal of the second switch. A second terminal of the second resistor is electrically connected to both a second power supply and the second terminal of the second switch. A third terminal of the second switch is electrically connected to the first terminal of the first resistor. A second terminal of the first resistor is electrically connected to both the first terminal of the third resistor and the first terminal of the first switch. A second terminal of the first switch is electrically connected to the first power supply, and both the third terminal of the first switch and the second terminal of the third resistor are electrically connected to a ground terminal.

[0007] By setting the above-mentioned device, the first power supply will be grounded when the watchdog does not receive a feeding signal within a preset time.

[0008] In one or more embodiments, the first switch is an N-type FET or an NPN transistor, and the second switch is a PNP transistor or a P-type FET.

[0009] By setting the above-mentioned devices as the first and second switches, the switching devices can be selected according to actual needs in practical applications, thereby improving design flexibility.

[0010] In one or more embodiments, the first switching unit further includes: a first capacitor; a first terminal of the first capacitor is electrically connected to a second terminal of a first resistor, a first terminal of a third resistor and a first terminal of a first switch, respectively, and a second terminal of the first capacitor is electrically connected to a ground terminal.

[0011] The first capacitor filters the signal output to the first switch, thereby filtering out high-frequency noise and interference signals, and improving the accuracy and reliability of the protection circuit.

[0012] In one or more embodiments, the second switching unit includes: a third switch, a fifth resistor, a sixth resistor, and a seventh resistor. A first terminal of the sixth resistor is electrically connected to the analog front-end chip, and a second terminal of the sixth resistor is electrically connected to both the first terminal of the third switch and the first terminal of the seventh resistor. The second terminals of both the third switch and the seventh resistor are electrically connected to ground. The third terminal of the third switch is electrically connected to both the enable pin and the first terminal of the fifth resistor. The second terminal of the fifth resistor is electrically connected to a second power supply.

[0013] By configuring the aforementioned devices, the watchdog timer is enabled based on the signal output from the analog front-end chip.

[0014] In one or more embodiments, the third switch is an NPN transistor; or the third switch is an N-type FET.

[0015] By setting an NPN transistor or an N-type FET as the third switch, the switching device can be selected according to actual needs in practical applications, thereby improving design flexibility.

[0016] In one or more embodiments, the second switching unit further includes a second capacitor. A first terminal of the second capacitor is electrically connected to a second terminal of a sixth resistor, a first terminal of a third switch, and a first terminal of a seventh resistor, respectively, and a second terminal of the second capacitor is electrically connected to a ground terminal.

[0017] The second capacitor filters the signal output to the third switch, thereby filtering out high-frequency noise and interference signals and improving the accuracy and reliability of the protection circuit.

[0018] Secondly, embodiments of this application also provide a battery management system, which includes a protection circuit as described in any embodiment of the first aspect.

[0019] Thirdly, embodiments of this application also provide a battery pack, which includes a cell module and a battery management system as described in any of the embodiments of the second aspect; the cell module is electrically connected to the battery management system.

[0020] Fourthly, embodiments of this application also provide an electrical device, which includes a load and a battery pack as described in any embodiment of the third aspect; wherein the battery pack is used to supply power to the load. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, which are not intended to limit the embodiments, and elements having the same reference numerals in the drawings are designated as similar elements.

[0022] Figure 1 This is a schematic diagram of the structure of a battery pack provided in an embodiment of this application;

[0023] Figure 2 A structural block diagram of a protection circuit provided in an embodiment of this application;

[0024] Figure 3 This is a structural diagram of a protection circuit provided in an embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0026] It should be noted that when an element is described as "connected" to another element, it can be directly connected to the other element, or there may be one or more intervening elements. Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not constitute a conflict.

[0027] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a battery pack provided in an embodiment of this application. Figure 1As shown, the battery pack includes a battery management system 100 and cell modules 200, with the battery management system 100 electrically connected to the cell modules 200. The battery pack is equivalent to an energy storage product, and the cell modules 200 serve as the energy storage units of this product. Each cell module 200 includes one cell, or multiple cells connected in series and / or parallel. The battery management system 100 is configured to acquire the real-time operating status of the cell modules 200, such as current signals, voltage signals, and temperature signals, and to control, monitor, or protect the cell modules 200. The battery management system 100 is typically equipped with a control unit.

[0028] When the control unit is exposed to external interference factors such as external electrostatic discharge, power supply voltage fluctuations, or strong current pulses released by inductive loads at startup, the parasitic effect unique to Complementary Metal Oxide Semiconductor (CMOS) technology induces the switching elements inside the control unit to enter an abnormal strong conduction state. Once this state is formed, a large current will be generated rapidly, causing a latch-up effect in the control unit and causing irreversible damage to the chip.

[0029] Based on the above reasons, this application provides a protection circuit that uses a watchdog timer to monitor the feeding signal of the control unit. When the watchdog timer does not receive the feeding signal within a preset time, it controls the first switch unit to turn on, grounding the power supply (first power supply) of the control unit, thereby releasing the latch-up effect of the control unit, protecting the control unit from damage, and improving the reliability and stability of the battery management system.

[0030] like Figure 2 As shown, the protection circuit provided in this application embodiment includes: a control unit 10, a watchdog timer 20, a first power supply VCC1, a second power supply VCC2, a first switching unit 30, an analog front-end chip 40, and a second switching unit 50.

[0031] The first power supply VCC1 is electrically connected to the control unit 10, and the second power supply VCC2 is electrically connected to the watchdog timer 20. The control unit 10 is also electrically connected to the watchdog timer 20, which includes an enable pin and an output pin. The first switching unit 30 is electrically connected to the first power supply VCC1, the second power supply VCC2, the output pin, and the ground terminal GND. The analog front-end chip 40 is electrically connected to the second switching unit 50, which is also electrically connected to the second power supply VCC2, the enable pin, and the ground terminal GND.

[0032] The first power supply VCC1 is configured to power the control unit 10, and the second power supply VCC2 is configured to power the watchdog 20. The first switching unit 30 is configured to turn on in response to the watchdog 20 not receiving a feeding signal within a preset time, so as to electrically connect the first power supply VCC1 to the ground terminal GND.

[0033] In some embodiments of this application, the first power supply VCC1 and the second power supply VCC2 are independent of each other. The first power supply VCC1 is an independent power supply, or its voltage is obtained by converting the voltage of the battery pack through a voltage conversion circuit. The voltage of the first power supply VCC1 is set as needed. For example, the voltage of the first power supply VCC1 relative to the ground terminal GND is 3.3V or 5V. The second power supply VCC2 is an independent power supply, or its voltage is obtained by converting the voltage of the battery pack through a voltage conversion circuit. The voltage of the second power supply VCC2 is set as needed. For example, the voltage of the second power supply VCC2 relative to the ground terminal GND is 2.5V or 5V.

[0034] As a specific example of this application, the control unit 10 is a microcontroller unit (MCU). It is understood that in other embodiments of this application, the control unit 10 includes a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a microcontroller, an Acorn RISC Machine (ARM), or other programmable logic, discrete gate or transistor logic, discrete hardware components, or any combination of these components.

[0035] The watchdog timer 20 is a device that determines whether the control unit 10 is working properly by detecting whether the control unit 10 periodically sends a "feed" signal, and outputs a signal to the first switching unit 30 through an output pin after determining the working state of the control unit 10. The "feed" signal is a periodic signal, such as a pulse-width modulated signal.

[0036] In this protection circuit, when the control unit 10 is operating normally, it outputs a "feed" signal to the watchdog timer 20. Upon receiving the "feed" signal within a preset time, the watchdog timer 20 determines that the control unit 10 is in normal operating condition. The watchdog timer 20 then outputs a first control signal through its output pin to disconnect the first switching unit 30, allowing the first power supply VCC1 to power the control unit 10. If the control unit 10 malfunctions, such as experiencing a latch-up effect, it cannot output the "feed" signal to the watchdog timer. If the watchdog timer 20 does not receive the "feed" signal within the preset time, it determines that the control unit 10 has malfunctioned. The watchdog timer 20 then outputs a second control signal through its output pin to turn on the first switching unit 30, electrically connecting the first power supply VCC1 to the ground terminal GND, thereby de-energizing the control unit 10, releasing the latch-up effect, and reducing the risk of damage to the control unit. The preset time can be set according to actual needs and is not limited in this application.

[0037] In this application, by setting a watchdog 20 and a first switch unit 30, when the control unit 10 experiences a latch-up effect, the power supply (first power supply VCC1) of the control unit 10 is grounded, thereby disconnecting the power supply of the control unit 10 and preventing the control unit 10 from being damaged by a latch-up effect.

[0038] In this application, the analog front-end chip 40 collects at least one parameter such as voltage, temperature, and current of the battery cells in the battery pack and sends the collected parameters to the control unit 10. The analog front-end chip 40 is powered by the battery cell module 200. When the analog front-end chip 40 is in a sleep state, it outputs a first-level signal to the second switching unit 50. When the analog front-end chip 40 is in an operating state, it outputs a second-level signal to the second switching unit 50.

[0039] The second switching unit 50 is configured to output different enable signals to the enable pin of the watchdog 20 based on the level signal output by the analog front-end chip 40, in order to control the operation of the watchdog 20. Specifically, after receiving the first level signal, the second switching unit 50 outputs a first enable signal to the watchdog 20; after receiving the second level signal, the second switching unit 50 outputs a second enable signal to the watchdog 20.

[0040] In this application, the high-level signal is used as the first level signal, the low-level signal is used as the second level signal, the low-level signal is used as the first enable signal, and the high-level signal is used as the second enable signal for illustration. In actual application, there is no limitation.

[0041] In this protection circuit, when the analog front-end chip 40 is in sleep mode, it outputs a low-level signal to the second switching unit 50, causing the second switching unit 50 to turn off. The second switching unit 50 then outputs a high-level signal to the enable pin of the watchdog timer 20, disabling the watchdog timer 20. When the analog front-end chip 40 is in working mode, it outputs a high-level signal to the second switching unit 50, turning the second switching unit 50 on. The second switching unit 50 then outputs a low-level signal to the enable pin of the watchdog timer 20, enabling the watchdog timer 20 to operate.

[0042] That is, in this application, the watchdog 20 is enabled by the analog front-end chip 40. When the analog front-end chip 40 is in a sleep state, the watchdog 20 does not work, thereby reducing the power consumption of the overall system.

[0043] In some embodiments, see Figure 3 The first switching unit 30 includes: a first switch Q1, a second switch Q2, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0044] The first end of the fourth resistor R4 is electrically connected to the output pin of the watchdog 20. The second end of the fourth resistor R4 is electrically connected to the first end of the second resistor R2 and the first end of the second switch Q2. The second end of the second resistor R2 is electrically connected to the second power supply VCC2 and the second end of the second switch Q2. The third end of the second switch Q2 is electrically connected to the first end of the first resistor R1. The second end of the first resistor R1 is electrically connected to the first end of the third resistor R3 and the first end of the first switch Q1. The second end of the first switch Q1 is electrically connected to the first power supply VCC1. The third end of the first switch Q1 and the second end of the third resistor R3 are both electrically connected to the ground terminal GND.

[0045] The fourth resistor R4 and the second resistor R2 form a voltage divider circuit to divide the voltage of the second power supply VCC2, so as to ensure that the signal output to the second switch Q2 will not damage the second switch Q2. When the electrical signal at the output pin is unstable, the second resistor R2 pulls the first terminal of the second switch Q2 up to the level of the second power supply VCC2, ensuring that the second switch Q2 is reliably turned off, reducing the second switch Q2 from being falsely triggered and turned on, and improving the reliability of the circuit operation.

[0046] When the second switch Q2 is turned on, the first resistor R1 limits the current input from the second power supply VCC2 to the first switch Q1 in order to protect the first switch Q1.

[0047] When the electrical signal sent from the second switch Q2 to the first switch Q1 is unstable, the third resistor R3 ensures that the first switch Q1 is reliably grounded, guaranteeing that the first switch Q1 is reliably turned off, reducing the chance of the first switch Q1 being falsely triggered and turned on, and improving the reliability of the circuit operation.

[0048] In some embodiments, if the watchdog 20 receives a feed signal within a preset time, it will leave the output pin floating, i.e., the output pin will be in a high-impedance state, and the output pin will neither output a high-level signal nor a low-level signal; alternatively, it will output a third-level signal through the output pin. If the watchdog 20 does not receive a feed signal within the preset time, it will output a fourth-level signal through the output pin. The third-level signal is a high-level signal, and the fourth-level signal is a low-level signal.

[0049] In this protection circuit, when the watchdog 20 receives a feed signal within a preset time, the output pin is left floating or outputs a high-level signal, the second switch Q2 is turned off, and the first switch Q1 is also turned off, without affecting the operation of the first power supply VCC1; when the watchdog 20 does not receive a feed signal within a preset time, the output pin outputs a low-level signal, the second switch Q2 is turned on, and the first switch Q1 is also turned on, so that the first power supply VCC1 is connected to the ground terminal.

[0050] In some embodiments, the first switch Q1 is an N-type FET, with its first terminal serving as the gate, second terminal as the drain, and third terminal as the source. Alternatively, the first switch Q1 is an NPN transistor, and the second switch Q2 is a P-type FET. The first terminal of the first switch Q1 serves as the base, second terminal as the collector, and third terminal as the emitter.

[0051] In some embodiments, the second switch Q2 is a PNP transistor, with its first terminal serving as the base, its second terminal as the emitter, and its third terminal as the collector. Alternatively, the second switch Q2 is a P-type FET, with its first terminal serving as the gate, its second terminal as the source, and its third terminal as the drain.

[0052] In some embodiments, see Figure 3 The first switching unit 30 further includes a first capacitor C1. The first end of the first capacitor C1 is electrically connected to the second end of the first resistor R1, the first end of the third resistor R3, and the first end of the first switch Q1, respectively. The second end of the first capacitor C1 is electrically connected to the ground terminal GND.

[0053] The first capacitor C1 filters the signal output to the first switch Q1, thereby filtering out high-frequency noise and interference signals and improving the accuracy and reliability of the protection circuit.

[0054] In some embodiments, see Figure 3The second switching unit 50 includes: a third switch Q3, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7.

[0055] The first terminal of the sixth resistor R6 is electrically connected to the analog front-end chip 40. The second terminal of the sixth resistor R6 is electrically connected to the first terminal of the third switch Q3 and the first terminal of the seventh resistor R7. The second terminals of the third switch Q3 and the seventh resistor R7 are both electrically connected to the ground terminal GND. The third terminal of the third switch Q3 is electrically connected to the enable pin of the watchdog timer 20 and the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is electrically connected to the second power supply VCC2.

[0056] In the second switching unit 50, when the analog front-end chip 40 is in sleep mode, it outputs a low-level signal to the third switch Q3, causing Q3 to open. The second power supply VCC2 then outputs a high-level signal through the fifth resistor R5 to the enable pin of the watchdog timer 20, disabling it and putting the system into a low-power state. When the analog front-end chip 40 is in working mode, it outputs a high-level signal to the third switch Q3, turning it on. The second switching unit 50 then outputs a low-level signal to the enable pin of the watchdog timer 20, enabling it to operate.

[0057] The sixth resistor R6 limits the current input from the analog front-end chip 40 to the third switch Q3 to protect the third switch Q3.

[0058] When the electrical signal sent by the analog front-end chip 40 is unstable, the seventh resistor R7 reliably grounds the first terminal of the third switch Q3, ensuring that the third switch Q3 is reliably turned off, reducing the chance of the third switch Q3 being falsely triggered and turned on, and improving the reliability of the circuit operation. Moreover, when the third switch Q3 is turned off, it discharges the energy of the parasitic capacitance of the third switch Q3.

[0059] When the electrical signal of the third switch Q3 is unstable, the fifth resistor R5 pulls the first terminal of the third switch Q3 up to the level of the first power supply VCC1, ensuring that the third switch Q3 is reliably turned off, reducing the chance of the third switch Q3 being falsely triggered and turned on, and improving the reliability of the circuit operation.

[0060] In some embodiments, the third switch Q3 is an NPN transistor, with its first terminal serving as the base, second terminal as the emitter, and third terminal as the collector. Alternatively, the third switch Q3 is an N-type FET, with its first terminal serving as the gate, second terminal as the source, and third terminal as the drain.

[0061] In some embodiments, the second switching unit 50 further includes a second capacitor C2. The first terminal of the second capacitor C2 is electrically connected to the second terminal of the sixth resistor R6, the first terminal of the third switch Q3, and the first terminal of the seventh resistor R7, respectively, and the second terminal of the second capacitor C2 is electrically connected to the ground terminal GND.

[0062] The second capacitor C2 filters the signal output to the third switch Q3, thereby filtering out high-frequency noise and interference signals and improving the accuracy and reliability of the protection circuit.

[0063] The following is Figure 3 The working process of the embodiments of this application is illustrated by taking the illustrated example.

[0064] When the analog front-end chip 40 is in sleep mode, the analog front-end chip 40 outputs a low-level signal to the third switch Q3. The third switch Q3 is turned off, and the second power supply VCC2 outputs a high-level signal to the enable pin of the watchdog 20 through the fifth resistor R5. The watchdog 20 does not work, and the system enters a low-power state.

[0065] When the analog front-end chip 40 is in operation, it outputs a high-level signal to the third switch Q3, turning on Q3. The second switch unit 50 then outputs a low-level signal to the enable pin of the watchdog 20, enabling the watchdog 20 to operate. Next, if the control unit 10 is operating normally, it outputs a feed signal to the watchdog 20. If the watchdog 20 receives the feed signal within a preset time, its output pin either floats or outputs a high-level signal. The second switch Q2 turns off, and the first switch Q1 also turns off, without affecting the operation of the first power supply VCC1. If the control unit 10 malfunctions, such as experiencing a latch-up effect, it cannot output a feed signal to the watchdog. If the watchdog 20 does not receive the feed signal within a preset time, its output pin outputs a low-level signal. The second switch Q2 turns on, and the first switch Q1 also turns on, connecting the first power supply VCC1 to ground (GND). This de-energizes the control unit 10, releasing the latch-up effect and protecting it. Then, when the watchdog timer 20 reaches its operating time, the output pin will either float again or output a high-level signal again, the second switch Q2 will turn off, the first switch Q1 will also turn off, the first power supply VCC1 will resume power supply to the control unit 10, and the control unit 10 will be powered on and reset.

[0066] exist Figure 3 In the embodiment shown, resistor R7 provides a stable low-level signal to the watchdog 20 when the dog-feeding signal output by control unit 10 is unstable.

[0067] The protection circuit provided in this application has a simple circuit topology. When a latch-up effect occurs in the control unit 10, the latch-up effect is released by power-off, thereby improving the overall circuit lifespan and preventing the control unit 10 from becoming unrecoverable due to latch-up, which could lead to battery product malfunction or even cell depletion. This improves the reliability and stability of the battery product. Furthermore, restoring power to the control unit 10 after a power outage not only reduces the maintenance workload and costs caused by latch-up but also reduces system downtime caused by latch-up, improving system response speed and overall performance.

[0068] As another aspect of this application, this application also provides a battery management system, which includes the protection circuit described in any of the above embodiments. In this embodiment, the signal transmission circuit has the same structure and function as the protection circuit in the above embodiments, and will not be described again here.

[0069] As another aspect of this application, this application also provides a battery pack, which includes a cell module and a battery management system as described in any of the embodiments of the first aspect above. In this embodiment, the battery management system has the same structure and function as the battery management system in the above embodiments, and will not be described again here.

[0070] As another aspect of the embodiments of this application, this application also provides an electrical device, which includes a load and a battery pack as described in any of the embodiments of the third aspect above; wherein the battery pack is used to supply power to the load. In this embodiment, the battery pack has the same structure and function as the battery pack in the above embodiments, and will not be described in detail here.

[0071] In some embodiments, electrical equipment includes, but is not limited to, energy storage products, drones, power tools, and electric vehicles.

[0072] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A protection circuit, characterized in that, include: A control unit and a watchdog timer electrically connected to the control unit, the watchdog timer including an enable pin and an output pin; A first power source is electrically connected to the control unit and configured to power the control unit; A second power source is electrically connected to the watchdog timer and configured to power the watchdog timer. A first switching unit is electrically connected to the first power supply, the second power supply, the output pin, and the ground terminal. The first switching unit is configured to: in response to the watchdog not receiving a dog-feeding signal within a preset time, the first switching unit is turned on to electrically connect the first power supply to the ground terminal. An analog front-end chip and a second switching unit electrically connected to the analog front-end chip, the second switching unit being electrically connected to the second power supply, the enable pin, and the ground terminal.

2. The protection circuit according to claim 1, characterized in that, The first switching unit includes: a first switch, a second switch, a first resistor, a second resistor, a third resistor, and a fourth resistor; The first end of the fourth resistor is electrically connected to the output pin, and the second end of the fourth resistor is electrically connected to the first end of the second resistor and the first end of the second switch, respectively. The second end of the second resistor is electrically connected to the second power supply and the second end of the second switch, respectively. The third terminal of the second switch is electrically connected to the first terminal of the first resistor; The second end of the first resistor is electrically connected to the first end of the third resistor and the first end of the first switch, respectively. The second terminal of the first switch is electrically connected to the first power source, and the third terminal of the first switch and the second terminal of the third resistor are both electrically connected to the ground terminal.

3. The protection circuit according to claim 1, characterized in that, The first switch is an N-type FET or an NPN transistor, and the second switch is a PNP transistor or a P-type FET.

4. The protection circuit according to claim 2 or 3, characterized in that, The first switching unit further includes: a first capacitor; The first terminal of the first capacitor is electrically connected to the second terminal of the first resistor, the first terminal of the third resistor, and the first terminal of the first switch, respectively, and the second terminal of the first capacitor is electrically connected to the ground terminal.

5. The protection circuit according to any one of claims 1 to 4, characterized in that, The second switching unit includes: a third switch, a fifth resistor, a sixth resistor, and a seventh resistor; The first end of the sixth resistor is electrically connected to the analog front-end chip, and the second end of the sixth resistor is electrically connected to the first end of the third switch and the first end of the seventh resistor, respectively. The second terminal of the third switch and the second terminal of the seventh resistor are both electrically connected to the ground terminal, and the third terminal of the third switch is electrically connected to the enable pin and the first terminal of the fifth resistor, respectively. The second end of the fifth resistor is electrically connected to the second power supply.

6. The protection circuit according to claim 5, characterized in that, The third switch is an NPN transistor; or The third switch is an N-type FET.

7. The protection circuit according to claim 5 or 6, characterized in that, The second switching unit further includes: a second capacitor; The first terminal of the second capacitor is electrically connected to the second terminal of the sixth resistor, the first terminal of the third switch, and the first terminal of the seventh resistor, respectively, and the second terminal of the second capacitor is electrically connected to the ground terminal.

8. A battery management system, characterized in that, Includes the protection circuit as described in any one of claims 1 to 7.

9. A battery pack, characterized in that, Includes a cell module and a battery management system as described in claim 8; The cell module is electrically connected to the battery management system.

10. An electrical appliance, characterized in that, Includes the load and the battery pack as described in claim 9; The battery pack is used to supply power to the load.

Images