MOS device

Abstract

The utility model provides an MOS device. The MOS device comprises a substrate and a gate structure located on the substrate, a drain region and an isolation structure are formed in the substrate, the drain region is located on the side edge of the gate structure, and the isolation structure comprises an isolation oxide layer and is at least partially located on the side, away from the gate structure, of the drain region. And the distance between the drain region and the isolation structure is greater than 0. Thus, the distance between the drain region and the isolation structure is increased, the electric leakage problem of the MOS device can be improved, the breakdown voltage of the MOS device is improved, and the reliability of the device is improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor device technology, and in particular to a MOS device. Background Technology

[0002] MOS (MOSFET) devices have advantages such as high efficiency, low loss, high reliability, low noise and fast switching, and are widely used in the field of electronic circuits.

[0003] Figure 1 This is a schematic diagram of the cross-sectional structure of an existing LDMOS device. Figure 2 This is a schematic diagram of the layout structure of an existing LDMOS device, in which... Figure 2 The active region AA is surrounded by an isolation structure. Taking the LDMOS (Laterally Diffused Metal Oxide Semiconductor) device as an example, refer to... Figure 1 and Figure 2 As shown, the LDMOS device includes a drain region 104 located in a substrate 100 and a gate structure 103 located on the substrate 100. An isolation structure 105 is formed in the substrate on the side of the drain region 104 away from the gate structure 103, and the drain region 104 and the isolation structure 105 are laterally connected. Since the isolation oxide layer of the isolation structure 105 is prone to defects (such as cracks, impurities, or high interface state density) during the manufacturing process, these defects can easily form leakage channels, which increases the leakage current of the MOS device. In severe cases, it can even lead to a decrease in the breakdown voltage of the device, affecting the reliability of the device. Utility Model Content

[0004] One of the objectives of this invention is to provide a MOS device that can improve leakage current, increase breakdown voltage, and enhance reliability.

[0005] To achieve the above objectives, the MOS device provided by this utility model includes a substrate and a gate structure located on the substrate. A drain region and an isolation structure are formed in the substrate. The drain region is located on the side of the gate structure. The isolation structure includes an isolation oxide layer and is at least partially located on the side of the drain region away from the gate structure. The distance between the drain region and the isolation structure is greater than 0.

[0006] Optionally, the distance between the boundary of the drain region and the boundary of the active region where the drain region is located is greater than 0.

[0007] Optionally, the spacing between the leak area and the isolation structure is greater than or equal to 0.05 μm and less than or equal to 0.5 μm.

[0008] Optionally, the isolation structure is a shallow trench isolation structure or a local silicon oxide isolation structure.

[0009] Optionally, an active region is formed in the substrate, and the source region and the drain region are disposed on both sides of the gate structure.

[0010] Optionally, a substrate interface region is formed in the substrate, the substrate interface region surrounding the isolation structure, the source region and the drain region, and the substrate interface region is laterally connected to the isolation structure.

[0011] Optionally, the MOS device is an LDMOS device or a CMOS device.

[0012] Optionally, the MOS device is an N-type MOS device or a P-type MOS device.

[0013] Optionally, the MOS device may be a discrete device or integrated in a BCD structure.

[0014] Optionally, the substrate includes a substrate and an epitaxial layer, wherein the isolation structure and the drain region are formed in the epitaxial layer.

[0015] The MOS device provided by this utility model includes a substrate and a gate structure located on the substrate. A drain region and an isolation structure are formed in the substrate. The drain region is located on the side of the gate structure. The isolation structure includes an isolation oxide layer and is at least partially located on the side of the drain region away from the gate structure. The distance between the drain region and the isolation structure is greater than 0, that is, the drain region and the isolation structure do not contact each other. Increasing the distance between the drain region and the isolation structure can weaken the direct influence of the drain electric field on the defect region of the isolation oxide layer in the isolation structure, avoid the high electric field from concentrating at the defect, and prevent the charge carriers from having to travel a longer path to reach the defect location. Thus, the leakage path is physically blocked, which can improve the leakage problem of the device and prevent the breakdown voltage of the device from decreasing due to the increase in leakage, thereby improving the reliability of the device. In addition, the MOS device provided by this application can use layout modifications to separate the drain region and the isolation structure by a certain distance, so that the drain region and the isolation structure do not contact each other. This does not require changes to the manufacturing process and is simple to implement. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the cross-sectional structure of an existing LDMOS device.

[0017] Figure 2 This is a schematic diagram of the layout structure of an existing LDMOS device.

[0018] Figure 3 This is a cross-sectional structural diagram of a MOS device provided in an embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram of the layout structure of a MOS device provided in an embodiment of the present invention.

[0020] Figure 5 The breakdown curves of an NLDMOS device provided in an embodiment of this application and a conventional NLDMOS device are shown.

[0021] Explanation of reference numerals in the attached figures: 100-substrate; 101-substrate; 102-epitaxy layer; 103-gate structure; 104-drain region; 105-isolation structure; 106-source region; 107-substrate interface region; 108-first well region; 109-drift region. Detailed Implementation

[0022] As described in the background art, the isolation oxide layer of the isolation structure in MOS devices is prone to process defects (such as cracks, impurities, or high interface state density) during manufacturing. These process defects can easily form leakage channels, resulting in increased leakage current and decreased breakdown voltage of MOS devices. The specific mechanisms are as follows: (1) Electric field concentration and defect coupling: Refer to Figure 1 As shown, under high voltage operation, the electric field near the drain region 104 will be highly concentrated at the edge of the isolation structure 105. If there are defects in the isolation oxide layer of the isolation structure 105, these defects will become traps or tunneling paths for charge carriers (such as electrons or holes), causing leakage current to flow from the drain region 104 to the substrate through the defect region. The defects may also cause local electric field distortion, further aggravating leakage current. (2) Interface state and hot carrier injection: There may be unsaturated dangling bonds (interface state) at the interface between the isolation structure 105 and the silicon substrate. Under high electric field, hot carriers (such as high-energy electrons) may be captured by the interface state or tunnel through the isolation oxide layer to form a leakage path. This effect is particularly significant when the drain region 104 and the isolation structure 105 are in direct contact. (3) Breakdown voltage reduction: When the leakage current increases due to defects in the isolation structure, the avalanche breakdown point of the device under high voltage will be advanced, resulting in a decrease in breakdown voltage (BV). Local breakdown in the defect region may also trigger a chain reaction, causing the entire device to fail prematurely.

[0023] To address the aforementioned problems, this invention provides a MOS device. The MOS device includes a substrate and a gate structure located on the substrate. A drain region and an isolation structure are formed in the substrate. The drain region is located on the side of the gate structure. The isolation structure includes an isolation oxide layer and is at least partially located on the side of the drain region away from the gate structure. The distance between the drain region and the isolation structure is greater than zero, meaning the drain region and the isolation structure do not contact each other. Increasing the distance between the drain region and the isolation structure weakens the direct impact of the drain-end electric field on the defect region of the isolation oxide layer in the isolation structure, preventing high electric field concentration at the defect location. This avoids the need for charge carriers to travel a longer path to reach the defect location, thus physically blocking the leakage path and improving the leakage problem of the device. It also prevents the device's breakdown voltage from decreasing due to increased leakage, improving the device's reliability. Furthermore, the MOS device provided in this application can utilize layout modifications to separate the drain region and the isolation structure by a certain distance, preventing them from contacting each other. This requires no changes to the manufacturing process, making the implementation simple.

[0024] The MOS device proposed in this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.

[0025] In the description of this utility model, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device referred to must have a specific orientation or be constructed in a specific orientation, and therefore should not be construed as a limitation on this utility model. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature.

[0026] Figure 3 This is a cross-sectional structural diagram of a MOS device provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the layout structure of a MOS device according to an embodiment of the present invention, wherein, Figure 4 The outer perimeter of the active region AA is the isolation structure.

[0027] refer to Figure 3 and Figure 4As shown, the MOS device includes a substrate 100 and a gate structure 103 located on the substrate 100. A drain region 104 and an isolation structure 105 are formed in the substrate 100. The drain region 104 is located on the side of the gate structure 103. The isolation structure 105 includes an isolation oxide layer and the isolation structure 105 is at least partially located on the side of the drain region 104 away from the gate structure 103. The distance D1 between the drain region 104 and the isolation structure 105 is greater than 0, that is, the drain region 104 and the isolation structure 105 are not in contact.

[0028] In this application, the MOS device can be an LDMOS device or a CMOS device, but is not limited thereto. For example, the LDMOS device can be an N-type LDMOS device or a P-type LDMOS device; the CMOS device can be an N-type CMOS device or a P-type CMOS device.

[0029] LDMOS devices possess advantages such as high power density and efficiency, excellent linearity, high breakdown voltage, strong thermal stability, and cost-effectiveness, occupying a key position in fields such as communications, defense, and automotive, and are particularly suitable for large-scale applications requiring high frequency and high voltage. Currently, for LDMOS devices, achieving a high breakdown voltage (BV) and low on-resistance (Rsp) is required, and the mainstream approach is to achieve optimal results through reduced surface field (RESURF) technology.

[0030] The following description uses an LDMOS device as an example to illustrate the MOS device proposed in this application.

[0031] In this embodiment, reference Figure 3 As shown, the substrate 100 may include a substrate 101 and an epitaxial layer 102, with the isolation structure 105 and the drain region 104 formed in the epitaxial layer 102. The epitaxial layer 102 can help the substrate 100 achieve material matching and control lattice defects, and can also adjust material properties, which helps to achieve device integration and improve device performance. In other embodiments, the substrate 100 may also include only the substrate 101.

[0032] In this embodiment, a MOS device is fabricated on the epitaxial layer 102. Specifically, the isolation structure 105, drain region 104, and other well regions and doped regions of the MOS device are formed in the epitaxial layer 102 to improve the device performance. For example, the material of the epitaxial layer 102 includes, but is not limited to, silicon or germanium; the substrate 101 can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate; the epitaxial layer 102 and the substrate 101 can also be implanted with certain dopant ions to change the electrical parameters according to design requirements.

[0033] In this embodiment, the substrate 101 may be a P-type substrate, but is not limited thereto.

[0034] In this embodiment, reference Figure 4 As shown, the substrate 100 has an active region AA defined by an isolation structure. Figure 4 The blank area surrounding the active region AA is an isolation structure. The isolation structure includes an isolation oxide layer, and the material of the isolation oxide layer includes, but is not limited to, silicon dioxide.

[0035] For example, the isolation structure 105 can be a shallow trench isolation structure (STI) or a localized silicon oxide isolation structure (LOCOS). Reference Figure 3 As shown, when the isolation structure 105 is a shallow trench isolation structure, the isolation structure 105 includes a shallow trench formed in the substrate 100 and an isolation oxide layer filled in the trench. The cross-section of the shallow trench is an inverted trapezoid, a rectangle, or a U-shape, etc. The local silicon oxide isolation structure can be formed by selectively oxidizing the silicon in the substrate 100 using silicon nitride or the like as a mask.

[0036] In this application, the isolation structure 105 is at least partially located on the side of the drain region 104 away from the gate structure 103. For example, the isolation structure 105 may surround the active region AA where the drain region 104 is located.

[0037] In this embodiment, reference Figure 3 and Figure 4 As shown, the drain region 104 can be an N+ doped region. The drain region 104 can be formed by an ion implantation process.

[0038] In this application, references Figure 3 The distance between the drain region 104 and the isolation structure 105 is greater than 0, meaning that the drain region 104 and the isolation structure 105 do not contact each other. This can weaken the direct influence of the drain electric field on the defect area of ​​the isolation oxide layer in the isolation structure 105, avoid the high electric field from concentrating at the defect, and prevent the charge carriers from having to travel a longer path to reach the defect location. As a result, the leakage path is physically blocked, which can improve the leakage problem of the device, prevent the breakdown voltage of the device from decreasing due to the increase in leakage, and improve the reliability of the device.

[0039] Further reference Figure 4 As shown, the drain region 104 is formed within the active region AA, and the distance between the boundary of the drain region 104 and the boundary of the active region AA in which the drain region 104 is located is greater than 0. For example, refer to... Figure 4As shown, in the X direction, the distance between the drain region 104 and the boundary of the active region AA is D1, and in the Y direction, the distances between the drain region 104 and the boundary of the active region AA are D2 and D3, respectively, and D1, D2, and D3 are all greater than 0. The distance between the drain region 104 and the boundary of the active region AA is also equivalent to the distance between the drain region 104 and the isolation structure 105. Thus, the drain region 104 does not contact the isolation structure 105 in either the X or Y directions, effectively avoiding the influence of defects in the isolation oxide layer in the isolation structure 105 on the device leakage current.

[0040] In this embodiment, an excessively large spacing between the drain region 104 and the isolation structure 105 would increase the chip area occupied by the MOS device, while an excessively small spacing would fail to effectively mitigate the direct impact of the drain-end electric field on the defective region of the isolation oxide layer in the isolation structure 105. Therefore, in this embodiment, the spacing between the drain region 104 and the isolation structure 105 is greater than or equal to 0.05 μm and less than or equal to 0.5 μm. For example, D1, D2, and D3 can all be greater than or equal to 0.05 μm and less than or equal to 0.5 μm. The specific spacing between the drain region 104 and the isolation structure 105 needs to be determined based on the capabilities of different process nodes.

[0041] refer to Figure 3 and Figure 4 As shown, the MOS device further includes a source region 106, which is formed in the active region AA of the substrate 100, and the source region 106 and the drain region 104 are disposed on opposite sides of the gate structure 103. In this embodiment, the source region 106 can be an N+ doped region.

[0042] refer to Figure 3 and Figure 4 As shown, a substrate interface region 107 is also formed in the substrate 100. The substrate interface region 107 can be annular. Figure 3 In the diagram, a portion of the substrate interface region 107 is located to the left of the gate structure 103 and a portion is located to the right of the gate structure 103. The substrate interface region 107 surrounds the isolation structure 105, the source region 106, and the drain region 104, and the substrate interface region 107 is laterally aligned with the isolation structure 105 (i.e.,...). Figure 3 The device is connected horizontally, and its Bulk terminal is led out from the substrate interface region 107. For example, the substrate interface region 107 can be a P+ doped region.

[0043] It should be noted that, Figure 2 and Figure 4The diagrams shown depict the layout openings of the drain region 104, source region 106, and substrate interface region 107, specifically the mask openings corresponding to these regions when forming them using ion implantation. When forming the source region 106 and substrate interface region 107 using ion implantation, to ensure that the source region 106 and substrate interface region 107 cover the active region AA in the Y direction, the mask openings of both regions slightly extend beyond the active region. Since the doped ions cannot penetrate the isolation structure outside the active region AA, the formed source region 106 and substrate interface region 107 are actually located only within the active region AA and tangent to the isolation structure. (Reference) Figure 2 As shown, in the prior art, when forming the drain region 104, since the issue of increasing the spacing between the drain region 104 and the isolation structure 105 is not considered, the mask opening of the drain region 104 will expose part of the isolation structure to the left of the active region AA and extend beyond the active region AA. Since the doped ions cannot penetrate the isolation structure outside the active region AA, the actually formed drain region 104 will be tangent to the isolation structure 105 (see reference). Figure 1 (as shown); In this embodiment, refer to Figure 3 As shown, since the spacing between the leak area 104 and the isolation structure 105 needs to be greater than 0, thus... Figure 4 As shown, the mask openings of the drain region 104 do not exceed the boundary of the active region AA, thus ensuring that the actually formed drain region 104 does not come into contact with the isolation structure.

[0044] For example, continue to refer to Figure 3 As shown, a first well region 108 and a drift region 109 are also formed in the substrate 100, and the first well region 108 and the drift region 109 are laterally connected. For example, the first well region 108 is a P-well, and the drift region 109 is an N-type doped region, but it is not limited thereto.

[0045] The gate structure 103 is located at the junction of the first well region 108 and the drift region 109. One end of the gate structure 103 extends onto the first well region 108 and the other end extends onto the drift region 109. The source region 106 is located above the first well region 108 and on one side of the gate structure 103. The drain region 104 is located above the drift region 109 and on the other side of the gate structure 103. The isolation structure 105 is at least partially located on the side of the drain region 104 away from the gate structure 103. The isolation structure 105 is partially located above the drift region 109 and partially located above the first well region 108. The substrate interface region 107 is located above the first well region 108.

[0046] In this embodiment, the doping concentration of the drain region 104 is greater than the doping concentration of the drift region 109; the doping concentration of the substrate interface region 107 is greater than the doping concentration of the first well region 108.

[0047] refer to Figure 3 As shown, the gate structure 103 may include a gate oxide layer and a gate located above the gate oxide layer. The material of the gate oxide layer includes, but is not limited to, silicon oxide, and the material of the gate includes, but is not limited to, polysilicon.

[0048] In this embodiment, the MOS device may include multiple device units, as referenced. Figure 4 As shown, a device unit may include a gate structure 103, a source region 106 and a drain region 104 located on both sides of the gate structure 103, and an isolation structure located at least partially on the side of the drain region 104 away from the gate structure 103. Two adjacent device units may share the same source region 106. When the device unit also includes a substrate interface region 107, the substrate interface regions 107 of two adjacent device units may also be partially shared.

[0049] In this embodiment, the MOS device is a discrete device or integrated in a BCD (Bipolar-CMOS-DMOS) structure, but is not limited thereto.

[0050] The LDMOS device provided in this embodiment can withstand a voltage greater than or equal to 6V and less than or equal to 1000V.

[0051] Figure 5 The breakdown curves of an NLDMOS device provided in an embodiment of this application and a conventional NLDMOS device are shown. In the conventional NLDMOS device, the drain region is in contact with the isolation structure (e.g., Figure 1 As shown), the spacing between the drain region 104 and the isolation structure 105 of the NLDMOS device provided in this application is greater than 0 (as shown). Figure 3 As shown in the image), after testing and comparison, as... Figure 5 As shown, under the same drain voltage, the drain current of the NLDMOS device of this application is less than that of the conventional NLDMOS device. This proves that by setting the spacing between the drain region 104 and the isolation structure 105 to be greater than 0, this application can improve the leakage current problem of the device and increase the breakdown voltage of the MOS device.

[0052] The MOS device provided in this application includes a substrate 100 and a gate structure 103 located on the substrate 100. A drain region 104 and an isolation structure 105 are formed in the substrate 100. The drain region 104 is located on the side of the gate structure 103. The isolation structure 105 includes an isolation oxide layer and is at least partially located on the side of the drain region 104 away from the gate structure 103. The spacing between the drain region 104 and the isolation structure 105 is greater than 0, that is, the drain region 104 and the isolation structure 105 do not contact each other, thus increasing the spacing between the drain region 104 and the isolation structure 105. The distance can weaken the direct impact of the drain electric field on the defect region of the isolation oxide layer in the isolation structure 105, avoid the high electric field from concentrating at the defect, and prevent the charge carriers from having to travel a longer path to reach the defect location. This physically blocks the leakage path, thereby improving the leakage problem of the device and preventing the breakdown voltage of the device from decreasing due to the increase in leakage, thus improving the reliability of the device. In addition, the MOS device provided in this application can use layout modifications to separate the drain region from the isolation structure by a certain distance, so that the drain region does not contact the isolation structure. This does not require changes to the manufacturing process and is simple to implement.

[0053] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. Any person skilled in the art can make possible changes and modifications to the technical solution of the present utility model by using the methods and techniques disclosed above without departing from the spirit and scope of the present utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model shall fall within the protection scope of the technical solution of the present utility model.

Claims

1. A MOS device, characterized in that, The device includes a substrate and a gate structure located on the substrate. A drain region and an isolation structure are formed in the substrate. The drain region is located on the side of the gate structure. The isolation structure includes an isolation oxide layer and is at least partially located on the side of the drain region away from the gate structure. The spacing between the drain region and the isolation structure is greater than 0.

2. The MOS device as described in claim 1, characterized in that, The distance between the boundary of the leak region and the boundary of the active region where the leak region is located is greater than 0.

3. The MOS device as described in claim 1, characterized in that, The distance between the leak area and the isolation structure is greater than or equal to 0.05 μm and less than or equal to 0.5 μm.

4. The MOS device as described in claim 1, characterized in that, The isolation structure is a shallow trench isolation structure or a local silicon oxide isolation structure.

5. The MOS device as described in claim 1, characterized in that, An active region is formed in the substrate, and the source region and the drain region are disposed on both sides of the gate structure.

6. The MOS device as described in claim 5, characterized in that, A substrate interface region is formed in the substrate, the substrate interface region surrounds the isolation structure, the source region and the drain region, and the substrate interface region is laterally connected to the isolation structure.

7. The MOS device as claimed in claim 1, characterized in that, The MOS device is either an LDMOS device or a CMOS device.

8. The MOS device as claimed in claim 1, characterized in that, The MOS device is an N-type MOS device or a P-type MOS device.

9. The MOS device as claimed in claim 1, characterized in that, The MOS device is either a discrete device or integrated in a BCD structure.

10. The MOS device as claimed in claim 1, characterized in that, The substrate includes a substrate and an epitaxial layer, and the isolation structure and the drain region are formed in the epitaxial layer.

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