Short circuit protector based on silicon carbide material

Abstract

The utility model provides a short-circuit protector based on silicon carbide material, which belongs to the technical field of short-circuit protectors, and sequentially comprises a bottom ohmic metal layer, a first N + substrate layer, a second N + substrate layer, a third N + substrate layer and a fourth N + substrate layer from bottom to top, the first N + substrate layer is located on the upper surface of the bottom ohmic metal layer; the N layer is located on the first N + substrate layer; the depletion region is a space charge region and is located between the N layer or the first N + substrate layer and the P + region; the P + regions are located on the upper surface of the first N + substrate layer, a conductive channel is formed between the two P + regions, and the P + regions are used for forming PN junctions and controlling current; the second N + substrate layer is located on the upper surface of the N layer; and the top ohmic metal layer is positioned on the upper surfaces of the P + region and the second N + substrate layer. The SIC MOSFET can be quickly responded and protected in a short-circuit state.

Description

Technical Field

[0001] This utility model belongs to the field of short circuit protection technology, specifically, it relates to a short circuit protection device based on silicon carbide material. Background Technology

[0002] Silicon carbide (SiC) is a wide-bandgap semiconductor material with excellent properties such as high thermal conductivity, high breakdown electric field strength, and high electron saturation drift velocity, making it widely used in high-temperature, high-frequency, and high-power electronic devices. However, compared with traditional silicon-based power devices (such as silicon-based IGBTs), SiC MOSFETs have poor short-circuit withstand capability and short short-time, affecting the reliability and lifespan of the devices. A short-circuit protector is a device primarily used to quickly interrupt current when a short circuit occurs, protecting other devices in the circuit (such as SiC MOSFETs) from damage. These traditional short-circuit protection designs include fuses, relays, gas discharge tubes, etc.

[0003] While short-circuit protectors can effectively protect traditional silicon-based power devices (such as silicon IGBTs), they cannot effectively protect SiC MOSFETs. This is mainly due to the following reasons: Traditional short-circuit protectors have a slow response time in short-circuit events, which may cause damage to the SiC MOSFET device in the circuit before the protection action occurs. Under normal operating conditions, the on-resistance of some traditional devices is high, leading to increased energy loss and reduced overall system efficiency. Furthermore, the design of certain composite high short-circuit withstand devices often requires complex multilayer structures and manufacturing processes, increasing manufacturing costs and process complexity. Utility Model Content

[0004] In view of this, the present invention provides a short-circuit protector based on silicon carbide material, which can solve the problem of fast response protection of SiC MOSFET under short-circuit conditions.

[0005] This utility model is implemented as follows:

[0006] This utility model provides a short-circuit protector based on silicon carbide material, comprising an N+ substrate layer, wherein the N+ substrate layer includes a first N+ substrate layer and a second N+ substrate layer, and the device structure comprises, from bottom to top:

[0007] The bottom ohmic metal layer is connected to the first N+ substrate layer;

[0008] The first N+ substrate layer is located on the upper surface of the bottom ohmic metal layer and serves as a low-resistance contact layer.

[0009] The N layer, located above the first N+ substrate layer, serves as a conductive channel layer.

[0010] The depletion region, or space charge region, is located between the N layer or the first N+ substrate layer and the P+ region.

[0011] The P+ region is located on the upper surface of the first N+ substrate layer. There is a conductive channel between the two P+ regions. The P+ region is used to form a PN junction and control the current.

[0012] The second N+ substrate layer is located on the upper surface of the N layer; the top ohmic metal layer is located in the P+ region and on the upper surface of the second N+ substrate layer.

[0013] The N+ region refers to a highly doped N-type semiconductor region. Here, "N" indicates the presence of donor impurities (such as nitrogen, phosphorus, arsenic, etc.) in the semiconductor material, resulting in a much higher concentration of free electrons than holes; "+" indicates a high doping concentration.

[0014] The P+ region refers to a highly doped P-type semiconductor region. Here, "P" indicates the presence of acceptor impurities (such as boron or aluminum) in the semiconductor material, resulting in a hole concentration much higher than the free electron concentration; "+" indicates a high doping concentration.

[0015] The protected devices of this invention include, but are not limited to, silicon carbide (SiC) MOSFETs. Through a bottom-up multilayer structure design, efficient current conduction and immediate protection are achieved under normal operation and short-circuit conditions. The bottom and top ohmic metal layers ensure good electrical contact, and the PN junction design formed by the N+ substrate and P+ region enables the device to respond quickly under short-circuit conditions, limiting short-circuit current.

[0016] Based on the above technical solution, the short-circuit protector based on silicon carbide material of this utility model can be further improved as follows:

[0017] The bottom ohmic metal layer is deposited on the lower surface of the first N+ substrate layer by electron beam evaporation or sputtering.

[0018] Electron beam evaporation is a physical vapor deposition (PVD) technology that uses a high-energy electron beam to bombard a target material, causing the material on the target surface to evaporate and deposit onto a substrate to form a thin film.

[0019] Furthermore, the top ohmic metal layer is deposited on the upper surface of the P+ region and the second N+ substrate layer by electron beam evaporation or sputtering.

[0020] The doping concentration of the first N+ substrate layer and the second N+ substrate layer is 1×10⁻⁶. 8 cm -3 In summary, the N+ substrate layer serves as the main conductive channel of the device, forming a good ohmic contact with the bottom ohmic metal layer to ensure that current can flow efficiently from the bottom to the top.

[0021] Electron beam evaporation is used to deposit bottom and top ohmic metal layers, ensuring good ohmic contact between the metal layers and the semiconductor material and reducing contact resistance.

[0022] To further reduce contact resistance, N-type ion implantation can be performed on the lower surface of the first N+ substrate and the upper surface of the second N+ substrate before depositing the ohmic metal material, thereby further increasing the surface doping concentration.

[0023] Furthermore, the doping concentration of the first N+ substrate layer is greater than or equal to the doping concentration of the N layer.

[0024] The doping concentration of the second N+ substrate layer is approximately equal to that of the first N+ substrate layer. The P+ region forms a PN junction with the N+ substrate layer. Under normal operating conditions, it does not participate in current conduction, but under short-circuit conditions, it limits and protects the current by extending the depletion region.

[0025] Furthermore, the top ohmic metal layer is a metal layer located on the upper surface of the device, forming an ohmic contact with the P+ region and the second N+ substrate layer or N layer. The bottom ohmic metal layer is a metal layer located on the lower surface of the device, forming an ohmic contact with the first N+ substrate layer. Both the top and bottom ohmic metal layers are made of suitable ohmic contact metal materials. These include highly conductive metal materials such as aluminum, titanium, nickel, gold, or alloys thereof.

[0026] Furthermore, the P+ region has a rectangular structure.

[0027] Furthermore, the depletion region is disposed around the P+ region and is in close contact with the sidewall of the P+ region.

[0028] Furthermore, the P+ region is formed in the N+ substrate layer by an ion implantation process.

[0029] The beneficial effects of adopting the above-mentioned improved scheme are: forming a P+ region through ion implantation and controlling its doping concentration to be 5×10⁻⁶. 15 cm -3 Up to 5×10 18 cm -3 This ensures the formation of a stable PN junction between the P+ region and the N+ substrate layer, providing a reliable basis for depletion layer expansion for short-circuit protection.

[0030] Ion implantation is a technique that uses a high-energy ion beam to implant impurity atoms into the surface of a semiconductor material. The implanted ions can alter the conductivity type (N-type or P-type) of the semiconductor material or modulate its electrical properties (such as doping concentration, carrier mobility, etc.).

[0031] Compared with the prior art, the advantages of the short-circuit protector based on silicon carbide material provided by this utility model are:

[0032] Fast response and efficient short-circuit protection:

[0033] This invention optimizes the design of the PN junction, enabling the device to rapidly expand the depletion layer under short-circuit conditions, clamping down the conductive channel and significantly increasing the on-resistance, thereby limiting the short-circuit current. This fast-response mechanism effectively protects other devices in the circuit (such as SiC MOSFETs) from damage caused by excessive short-circuit current.

[0034] Low on-resistance and high efficiency:

[0035] Under normal operating conditions, the on-resistance of this device is extremely low (less than 10mΩ), which significantly reduces energy loss and improves the overall efficiency of the system.

[0036] Simple structure and low manufacturing cost:

[0037] This invention employs a bottom-up multilayer structure design, including a bottom ohmic metal layer, an N+ substrate layer, a depletion region, a P+ region, and a top ohmic metal layer. This structural design not only simplifies the manufacturing process and reduces manufacturing costs, but also ensures the high performance and reliability of the device.

[0038] Excellent thermal management performance:

[0039] The high thermal conductivity of silicon carbide material, combined with the optimized structural design of this invention, effectively improves the thermal management performance of the device. In high-power applications, the device can dissipate heat quickly, avoiding localized overheating and improving its reliability and lifespan.

[0040] High reliability and long lifespan:

[0041] This novel device maintains stable performance even under extreme conditions (such as high voltage, high current, and high temperature environments), exhibiting high reliability and long lifespan. By precisely controlling the doping concentration and manufacturing process, the device's anti-aging ability and environmental adaptability are further improved. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1This is an example diagram of a first embodiment of a short-circuit protector based on silicon carbide material;

[0044] Figure 2 This is an example diagram of a second embodiment of a short-circuit protector based on silicon carbide material;

[0045] The attached diagram lists the components represented by each number as follows:

[0046] 1. Bottom ohmic metal layer; 2. First N+ substrate layer; 3. N layer; 4. P+ region; 5. Top ohmic metal layer; 6. Second N+ substrate layer. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings.

[0048] like Figure 1 The image shows a first embodiment of a short-circuit protector based on silicon carbide material provided by this utility model. In this embodiment, it includes an N+ substrate layer, which comprises a first N+ substrate layer and a second N+ substrate layer. The device structure, from bottom to top, includes:

[0049] The bottom ohmic metal layer 1 is connected to the first N+ substrate layer 2;

[0050] The first N+ substrate layer 2 is located on the upper surface of the bottom ohmic metal layer 1 and serves as a low-resistance contact layer.

[0051] N layer 3, located above the first N+ substrate layer 2, serves as a conductive channel layer;

[0052] The depletion region, or space charge region, is located between the N layer 3 or the first N+ substrate layer 2 and the P+ region 4.

[0053] P+ region 4 is located on the upper surface of the first N+ substrate layer 2. There is a conductive channel between the two P+ regions 4. The P+ region 4 is used to form a PN junction and control the current.

[0054] The second N+ substrate layer 6 is located on the upper surface of the N layer 3; the top ohmic metal layer 5 is located on the upper surface of the P+ region 4 and the second N+ substrate layer 6.

[0055] The boundary line between the first N+ substrate layer and the N layer is located below the P+ layer. During normal operation without shutdown, the overall resistance of the device is relatively high due to the lower position of the boundary line, resulting in some power loss when current flows. However, when the device faces a short circuit and needs to be shut off, this boundary line position allows the depletion region of the P+ region and the N+ substrate layer to expand significantly under negative voltage. This effectively promotes rapid pinch-off of the conductive channel, resulting in excellent shutdown performance. This greatly improves the response speed under short-circuit conditions, significantly enhancing the reliability of the device in short-circuit protection scenarios and effectively solving the problem of slow response in traditional silicon carbide short-circuit protectors. Point A is located in the top ohmic metal layer. * Point B is located in the P+ region, and point B is located in the first N+ substrate layer.

[0056] Under normal operating conditions, the operating current flows in from the bottom ohmic metal layer, passes through the N-type substrate layer, and finally flows out from the top ohmic metal layer. At this time, the P+ region does not participate in current conduction; the current mainly flows through the N-type substrate layer. The main resistance of the device is composed of the resistance of the N-type substrate layer, with a total resistance of less than 10 mΩ. The N-type substrate layer specifically includes a first N+ substrate layer, a second N+ substrate layer, and an N layer, among which the N layer contributes the highest resistance.

[0057] Potential distribution: point A and A * The same potential at point B indicates a uniform potential distribution in the upper half of the channel of the N+ substrate. A higher potential at point B indicates a slightly higher potential in the lower half of the channel of the N+ substrate.

[0058] VBA refers to the connection between point B and point A (or A... * The voltage difference between points B and A, i.e., the voltage at point B is higher than that at point A. Under normal operating conditions, VBA is 0.5V, which is due to the voltage drop generated when current flows through the N+ substrate.

[0059] According to Ohm's law, VBA = I × R, where I is the operating current (70A) and R is the upper channel resistance (approximately 6.67mΩ, accounting for 2 / 3 of the total resistance). Therefore, VBA = 70A × 0.00667Ω ≈ 0.5V.

[0060] Voltage in the P+ region: Since VBA is 0.5V, a voltage of -0.5V is applied to the P+ region (relative to the N+ substrate).

[0061] This negative voltage will slightly expand the depletion region between the P+ region and the N+ substrate, but due to the small voltage, the expansion of the depletion region is limited and will not significantly affect the on-resistance of the device.

[0062] Current path: Current flows through the N-type substrate layer; the P+ region does not participate in current conduction. The device exhibits highly efficient conduction characteristics under normal operating conditions.

[0063] Under short-circuit conditions, the short-circuit current increases sharply (e.g., reaching 200A or more), and the electrical behavior of the device changes significantly, thereby achieving fast short-circuit protection.

[0064] Changes in potential distribution: An increase in short-circuit current leads to a significant increase in VBA. According to Ohm's law, VBA = I × R, where I is the short-circuit current (200A) and R is the upper channel resistance (approximately 6.67mΩ). Therefore, VBA = 200A × 0.00667Ω ≈ 1.33V.

[0065] Voltage variation in the P+ region: An increase in VBA results in a larger negative voltage being applied to the P+ region (relative to the N+ substrate). For example, when VBA is 1.33V, a voltage of -1.33V is applied to the P+ region. This larger negative voltage significantly expands the depletion region between the P+ region and the N-type substrate, with the depletion layer extending into the N-type doped region.

[0066] Depletion layer expansion and channel pinch-off: The expansion of the depletion layer can lead to narrowing or even complete pinch-off of the conductive channel. When the conductive channel is pinched off, the on-resistance of the device increases significantly, and the current path is confined to an extremely narrow region, or even cannot pass through at all.

[0067] Short-circuit current limitation: Due to the significant increase in on-resistance, the device bears most of the bus voltage, thus limiting the further increase of short-circuit current.

[0068] This fast response mechanism enables the device to limit short-circuit current in a very short time, protecting the series-connected SiC MOSFETs from damage.

[0069] In the above technical solution, the bottom ohmic metal layer 1 is deposited on the lower surface of the N+ substrate layer 2 by electron beam evaporation or sputtering.

[0070] Electron beam generation: High-energy electron beams are generated using an electron gun.

[0071] Target heating: Electron beam bombardment of the target causes the surface material of the target to evaporate.

[0072] Thin film deposition: Evaporated material is deposited onto the substrate surface in a vacuum environment to form a uniform thin film.

[0073] Furthermore, in the above technical solution, the top ohmic metal layer 5 is deposited on the upper surface of the P+ region 4 and the second N+ substrate layer 6 by electron beam evaporation or sputtering.

[0074] Furthermore, in the above technical solution, the doping concentration of the N+ substrate layer is greater than or equal to the doping concentration of the N layer 3.

[0075] Furthermore, in the above technical solution, the ratio of the channel width of the P+ region 4 to the width of the first N+ substrate layer 2 is 1 / 3.

[0076] Furthermore, in the above technical solution, the top ohmic metal layer 5 is a metal layer located on the upper surface of the device, forming an ohmic contact with the P+ region 4 and the second N+ substrate layer 6 or N layer 3, and the bottom ohmic metal layer 1 is a metal layer located on the lower surface of the device, forming an ohmic contact with the first N+ substrate layer 2. The top ohmic metal layer 5 and the bottom ohmic metal layer 1 are made of highly conductive metal materials.

[0077] Furthermore, in the above technical solution, the P+ region 4 has a rectangular structure.

[0078] Furthermore, in the above technical solution, the depletion region is arranged around the P+ region 4, and the depletion region is close to the left wall, right wall and bottom wall of the P+ region 4.

[0079] Furthermore, in the above technical solution, the P+ region 4 is formed in the N+ substrate layer 2 by ion implantation.

[0080] like Figure 2 The image shows a second embodiment of a short-circuit protector based on silicon carbide material provided by this utility model. In this embodiment, it includes an N+ substrate layer, which comprises a first N+ substrate layer and a second N+ substrate layer. The device structure, from bottom to top, includes:

[0081] The bottom ohmic metal layer 1 is connected to the first N+ substrate layer 2;

[0082] The first N+ substrate layer 2 is located on the upper surface of the bottom ohmic metal layer 1 and serves as a low-resistance contact layer.

[0083] N layer 3, located above the first N+ substrate layer 2, serves as a conductive channel layer;

[0084] The depletion region, or space charge region, is located between the N layer 3 or the first N+ substrate layer 2 and the P+ region 4.

[0085] P+ region 4 is located on the upper surface of the first N+ substrate layer 2. There is a conductive channel between the two P+ regions 4. The P+ region 4 is used to form a PN junction and control the current.

[0086] The second N+ substrate layer 6 is located on the upper surface of the N layer 3; the top ohmic metal layer 5 is located on the upper surface of the P+ region 4 and the second N+ substrate layer 6.

[0087] The top ohmic metal layer 5 is located on the upper surface of the P+ region 4 and the N layer 3.

[0088] The boundary line between the first N+ substrate layer and the N layer is located in the middle of the P+ layer. Under normal conduction conditions, due to the relatively high position of the boundary line, the conductive structure formed by the first N+ substrate layer and the N layer results in a low on-resistance. Current can flow efficiently from the bottom ohmic metal layer through the first N+ substrate layer, the N layer, the second N+ substrate layer, and finally out from the top ohmic metal layer, exhibiting good conduction performance. When a short circuit occurs and turn-off is required, the expansion of the depletion region between the P+ region and the first N+ substrate layer is affected by the boundary line position. Although turn-off can be achieved, the increase in resistance during turn-off is relatively limited compared to the case where the boundary line is lower. However, it still meets the basic short-circuit protection requirements and improves the response speed under short-circuit conditions to a certain extent, thus enhancing the device reliability.

[0089] Furthermore, in the above technical solution, the top ohmic metal layer 5 is deposited on the upper surface of the P+ region 4 and the second N+ substrate layer 6 by electron beam evaporation or sputtering.

[0090] Furthermore, in the above technical solution, the doping concentration of the N+ substrate layer is greater than or equal to the doping concentration of the N layer 3.

[0091] Furthermore, in the above technical solution, the ratio of the channel width of the P+ region 4 to the width of the first N+ substrate layer 2 is 1 / 3.

[0092] Furthermore, in the above technical solution, the ratio of the channel thickness of the P+ region 4 to the thickness of the first N+ substrate layer 2 is 2 / 3.

[0093] Furthermore, in the above technical solution, the top ohmic metal layer 5 is a metal layer located on the upper surface of the device, forming an ohmic contact with the P+ region 4 and the second N+ substrate layer 6 or N layer 3, and the bottom ohmic metal layer 1 is a metal layer located on the lower surface of the device, forming an ohmic contact with the first N+ substrate layer 2. The top ohmic metal layer 5 and the bottom ohmic metal layer 1 are made of highly conductive metal materials.

[0094] Furthermore, in the above technical solution, the P+ region 4 has a rectangular structure.

[0095] Furthermore, in the above technical solution, the depletion region is arranged around the P+ region 4, and the depletion region is close to the left wall, right wall and bottom wall of the P+ region 4.

[0096] Furthermore, in the above technical solution, the P+ region 4 is formed in the N+ substrate layer 2 by ion implantation.

[0097] Specifically, the principle of this invention is as follows: Based on the excellent properties of silicon carbide material, combined with optimized device structure design and advanced manufacturing process, this invention achieves a highly efficient and reliable short-circuit protection device. Its core lies in the synergistic effect of a multi-layer structure, providing a low-resistance conduction path during normal operation, and responding rapidly in a short-circuit state to limit the short-circuit current, thereby protecting other critical components in the circuit (such as SiC MOSFETs).

[0098] The device structure of this invention adopts a bottom-up multi-layer design, with each layer having a specific function, collectively forming the device's efficient operating mechanism. The bottom ohmic metal layer forms a good ohmic contact with the first N+ substrate layer, ensuring efficient current flow into the device. The N+ substrate layer, as the main conductive channel, has a high doping concentration and low resistance, providing a foundation for current conduction under normal operating conditions. Above the first N+ substrate layer, a P+ region formed by ion implantation forms a PN junction with the N+ substrate layer. This structural design allows the device to maintain low resistance conduction during normal operation, while rapidly limiting current in a short-circuit state by extending the depletion layer. The top ohmic metal layer forms a good ohmic contact with the P+ region and the N+ substrate layer, ensuring efficient current flow out of the device. This synergistic design of the multi-layer structure not only simplifies the manufacturing process but also significantly improves the device's performance and reliability.

[0099] The operating mechanism of this novel device is based on the dynamic response characteristics of a PN junction. Under normal operating conditions, current flows in from the bottom ohmic metal layer, through the N+ substrate layer, and finally out from the top ohmic metal layer. At this time, the P+ region does not participate in current conduction, the depletion region expands relatively little, and the device exhibits a low resistance state, ensuring efficient current flow. However, when a short circuit occurs, the short-circuit current increases dramatically, and the PN junction formed by the N+ substrate layer and the P+ region generates a large depletion layer. This dynamic response mechanism allows the device to limit the short-circuit current in a very short time, bearing most of the bus voltage, thereby protecting the series-connected SiC MOSFET from damage.

Claims

1. A short-circuit protector based on silicon carbide material, characterized in that, Including an N+ substrate layer, the N+ substrate layer includes a first N+ substrate layer (2) and a second N+ substrate layer (6), and the device structure from bottom to top includes: The bottom ohmic metal layer (1) is connected to the first N+ substrate layer (2); The first N+ substrate layer (2) is located on the upper surface of the bottom ohmic metal layer (1) and serves as a low-resistance contact layer. The N layer (3) is located above the first N+ substrate layer (2) and serves as a conductive channel layer; The depletion region, i.e. the space charge region, is located between the N layer (3) or the first N+ substrate layer (2) and the P+ region (4); The P+ region (4) is located on the upper surface of the first N+ substrate layer (2), and there is a conductive channel between the two P+ regions (4); The second N+ substrate layer (6) is located on the upper surface of the N layer (3); The top ohmic metal layer (5) is located on the upper surface of the P+ region (4) and the second N+ substrate layer (6).

2. A short-circuit protector based on silicon carbide material according to claim 1, characterized in that, The bottom ohmic metal layer (1) is deposited on the lower surface of the first N+ substrate layer (2) by electron beam evaporation or sputtering.

3. A short-circuit protector based on silicon carbide material according to claim 2, characterized in that, The top ohmic metal layer (5) is deposited on the upper surface of the P+ region (4) and the second N+ substrate layer (6) by electron beam evaporation or sputtering.

4. A short-circuit protector based on silicon carbide material according to claim 3, characterized in that, The doping concentration of the first N+ substrate layer (2) is greater than or equal to the doping concentration of the N layer (3), and the doping concentration of the second N+ substrate layer (6) is equal to or different from that of the first N+ substrate layer (2).

5. A short-circuit protector based on silicon carbide material according to claim 4, characterized in that, The top ohmic metal layer (5) is a metal layer located on the upper surface of the device, forming an ohmic contact with the P+ region (4) and the second N+ substrate layer (6) or N layer (3).

6. A short-circuit protector based on silicon carbide material according to claim 5, characterized in that, The bottom ohmic metal layer (1) is a metal layer located on the lower surface of the device, forming an ohmic contact with the first N+ substrate layer (2).

7. A short-circuit protector based on silicon carbide material according to claim 6, characterized in that, The top ohmic metal layer (5) and the bottom ohmic metal layer (1) are made of highly conductive metal materials.

8. A short-circuit protector based on silicon carbide material according to claim 7, characterized in that, The structure of the P+ region (4) is one of rectangle, hexagon, circle and triangle.

9. A short-circuit protector based on silicon carbide material according to claim 8, characterized in that, The depletion region is arranged around the P+ region (4) and is in close contact with the sidewall of the P+ region (4).

10. A short-circuit protector based on silicon carbide material according to claim 9, characterized in that, The P+ region (4) is formed in the N+ substrate layer by ion implantation.

Images