Semiconductor device and memory device

Abstract

A semiconductor device and a memory device, the semiconductor device comprising: a substrate having a logic device formed thereon; the plurality of metal wiring layers are arranged above the substrate, and the metal wiring layers are connected to the logic device through metal wiring; and a plurality of multi-time programmable non-volatile memory cells formed between the metal wiring layers, and each of the multi-time programmable non-volatile memory cells includes a fin field effect transistor having a fin structure, a storage gate disposed around a plurality of channel regions of the fin structure, and a control gate formed around a plurality of sidewalls of the storage gate.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a memory device. Background Technology

[0002] Semiconductor devices are used in a variety of electronic devices, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using lithography to pattern the various material layers to form circuit components and elements on each layer.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size. This allows more components to be integrated into a given area. However, as the minimum feature size shrinks, other problems arise that need to be addressed. Utility Model Content

[0004] The embodiments disclosed herein provide a semiconductor device, including: a substrate having logic devices formed on the substrate; a plurality of metal wiring layers disposed above the substrate and connected to the logic devices via metal wiring; and a plurality of multiple programmable non-volatile memory cells formed between the metal wiring layers, wherein each multiple programmable non-volatile memory cell includes a fin field-effect transistor having a fin structure, a storage gate disposed around a plurality of channel regions of the fin structure, and a control gate formed around a plurality of sidewalls of the storage gate.

[0005] The embodiments disclosed herein provide a semiconductor device including a substrate having logic devices formed on the substrate; a plurality of metal wiring layers disposed above the substrate and the logic devices, the metal wiring layers including an upper metal wiring layer disposed among the plurality of metal wiring layers, the upper metal wiring layer including a plurality of metal lines, a plurality of vias, and an oxide layer; a fin structure disposed on the metal wiring layers, the fin structure including a plurality of channel regions and a first source / drain region and a second source / drain region respectively located on both sides of the channel regions; a dielectric layer disposed on the upper metal wiring layer and the fin structure; a storage gate disposed above the channel regions of the fin structure; a control gate disposed on a first side and a second side of the storage gate; and the control gate and at least one of the first source / drain regions and the second source / drain regions of the fin structure being connected to the logic devices through vias and metal lines.

[0006] The embodiments disclosed herein provide a memory device, including: a logic device; a plurality of metal wiring layers connected to the logic device via metal wiring; and a multiple programmable non-volatile memory cell located between the metal wiring layers, wherein the multiple programmable non-volatile memory cell includes a fin field-effect transistor having a fin, a storage gate disposed around a plurality of channel regions of the fin, and a control gate formed around a plurality of sidewalls of the storage gate. Attached Figure Description

[0007] The embodiments disclosed herein can be better understood by reading in conjunction with the accompanying drawings. It is worth noting that, according to standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0008] FIG. 1A This is a top view of a portion of an exemplary semiconductor device according to various embodiments;

[0009] FIG. 1B Along with various embodiments FIG. 1A A cross-sectional view of an exemplary transistor plotted along the x-axis;

[0010] FIG. 1C Along with various embodiments FIG. 1A A cross-sectional view of an exemplary transistor plotted along the y-axis;

[0011] FIG. 1D These are exemplary embodiments. FIG. 1A A schematic diagram of an MTP 4×4 NOR array;

[0012] FIG. 2A and FIG. 2B This is a cross-sectional view of a portion of an exemplary semiconductor device;

[0013] FIG. 3A This is a top view of a portion of an exemplary semiconductor device according to various embodiments;

[0014] FIG. 3B Along with various embodiments FIG. 3A A cross-sectional view of an exemplary transistor plotted along the x-axis;

[0015] FIG. 3C Along with various embodiments FIG. 3A A cross-sectional view of an exemplary transistor plotted along the y-axis;

[0016] FIG. 3D These are exemplary embodiments. FIG. 3A A schematic diagram of an MTP NAND array;

[0017] FIG. 4A andFIG. 4B This is a cross-sectional view of a portion of an exemplary semiconductor device according to various embodiments; and

[0018] FIG. 5 A flowchart illustrating an exemplary method for manufacturing a semiconductor device according to various embodiments is shown.

[0019] [Symbol Explanation]

[0020] 100, 200, 300, 400: Semiconductor devices

[0021] 102,302: Transistor

[0022] 104: MTP 4×4 NOR array

[0023] 106,208-4,306: Oxide layer

[0024] 108,218,308,418: Fin structure

[0025] 110, 220, 310, 420: Storage gate

[0026] 112,222,312,422: First control gate

[0027] 114, 224, 314, 424: Second control gate

[0028] 115,315: lines

[0029] 116,227,316,427: High-K dielectric layer

[0030] 117,317: Column

[0031] 119: Source Line

[0032] 202,402:Substrate

[0033] 204, 404: Interconnection structure

[0034] 204-1, 204-2, 204-3, 204-4, 204-5, 204-6, 204-7, 208-7: Metallization layer

[0035] 204-4: Wiring Layer

[0036] 206,406: Logic devices

[0037] 208-1, 208-2, 208-3, 208-4, 208-5, 208-6, 208-7: Intermetallic dielectric layer / IMD layer

[0038] 210, 410: Metal wire

[0039] 212,225,226,228,230,232,412,425,426,428,430,432: Through holes

[0040] 216,416: FinFET transistors

[0041] 304: NAND array

[0042] 319: Ground Selection Transistor

[0043] 321: Bit line select transistor

[0044] 404-1, 404-2, 404-3, 404-4, 404-5, 404-6, 404-7, 408-7: Metallization layer

[0045] 408-1, 408-2, 408-3, 408-4, 408-5, 408-6, 408-7: Intermetallic dielectric layer / IMD layer

[0046] BK k BK k+1 BK k+2 BK k+3 :bit line

[0047] SL m ,SL m+1 Source line

[0048] WL0,WL1,WL n WL n+1 WL n+2 WL n+3 :character line

[0049] X, Y: Axes Detailed Implementation

[0050] The following disclosure provides various embodiments or examples of configurations to achieve different features of the provided object. Specific examples of the components and settings are described below to simplify this disclosure. Of course, these are merely exemplary and are not intended to limit this disclosure.

[0051] For the sake of brevity, this disclosure will not describe in detail the conventional techniques associated with the manufacture of conventional semiconductor devices. Furthermore, the various steps and processes described in this disclosure can be incorporated into additional functional and more comprehensive steps or processes not detailed in this disclosure. Specifically, various processes in semiconductor device manufacturing are well-known; therefore, for the sake of brevity, many conventional processes will be only briefly mentioned or completely omitted in this disclosure without providing well-known process details. Those skilled in the art will readily understand upon a full reading of this disclosure that the structures described herein can be used with a variety of technologies and can be incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of components, and a single component shown in the accompanying drawings may represent multiple components.

[0052] It should be understood that while the terms first, second, third, etc., may be configured in this disclosure to describe various elements, components, regions, layers, parts, and / or locations, these elements, components, regions, layers, parts, and / or locations should not be limited by these terms. These terms are configured only to distinguish one element, component, region, layer, part, or location from another. Therefore, the first element, component, region, layer, part, or location discussed below may be referred to as a second element, component, region, layer, part, or location without departing from the teachings of this disclosure.

[0053] Furthermore, spatially related terms, such as "above," "on top of," "located above," "upper," "top," "below," "below," "located below," "lower," and "bottom," are used in this disclosure for ease of description to describe the relationship between one element or feature and another element or feature in the accompanying drawings. In addition to the orientations depicted in the drawings, spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or positioned in other orientations), and therefore the spatially relative descriptive terms used in this disclosure may be interpreted accordingly. When spatially relative terms, such as those listed above, are configured to describe a first element relative to a second element, the first element may be directly on the other element, or may be located in an intermediate element or layer.

[0054] Additionally, the reference numerals and / or letters in the figures may be repeated in various examples of this disclosure. Such repetition is for simplicity and clarity and is not in itself intended to limit the relationship between the various embodiments and / or configurations described.

[0055] It is worth noting that references to "one embodiment," "an embodiment," "an exemplary embodiment," "exemplary," "example," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment does not necessarily include those specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly stated or not, changes to such features, structures, or characteristics in conjunction with other embodiments will be understood by one skilled in the art.

[0056] In some embodiments of this disclosure, a "material layer" refers to a layer comprising at least 50% (wt%) of a specific material, such as at least 60 wt%, at least 75 wt%, at least 90 wt%, at least 95 wt%, or at least 99 wt% of a specific material; and the material of a layer refers to a layer comprising at least 50 wt% of a specific material, such as at least 60 wt%, at least 75 wt%, at least 90 wt%, at least 95 wt%, or at least 99 wt% of a specific material. For example, in some embodiments, each aluminum layer and the aluminum of a layer refers to a layer comprising at least 50 wt%, at least 60 wt%, at least 75 wt%, at least 90 wt%, at least 95 wt%, or at least 99 wt% aluminum.

[0057] It should be understood that the terms or terminology used in this disclosure are for illustrative purposes and not for limiting the disclosure, and that the terms or terminology used in this specification may be interpreted in light of the teachings of someone skilled in the art.

[0058] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0059] Additional steps may be provided before, during, and / or after the stages of the embodiments described. For different embodiments, some stages may be replaced or deleted, and other additional features for manufacturing semiconductor device structures may be added. For different embodiments, some features described below may be replaced or omitted. Although some embodiments are described by steps performed in a specific order, these steps may be performed in another logical order.

[0060] As used in this disclosure, "layer" refers to a region, such as a region with arbitrary boundaries, and not necessarily with uniform thickness. For example, a layer can be a region that includes at least some variation in thickness.

[0061] Multiple-time programmable (MTP) non-volatile memory (NVM) cells can be formed as NAND (Not AND) devices or NOR devices. Embodiments disclosed herein provide for forming MTP NVM cells during back-end of line (BEOL) processes. Embodiments disclosed herein provide for using BEOL processes to increase the device density of NAND and / or NOR devices in integrated circuits. In various embodiments, MTP NVM cells are disposed within an upper metallization layer to increase the density of MTP NVM cells in integrated circuits. In various embodiments, NAND and / or NOR devices are disposed within an upper metallization layer to increase the device density of NAND and / or NOR devices in integrated circuits.

[0062] FIG. 1A This is a top view of a portion of an exemplary semiconductor device according to various embodiments. The exemplary semiconductor device 100 includes a plurality of FinFET transistors 102, and the FinFET transistors 102 are configured as NOR devices in an MTP 4×4 NOR array 104. FIG. 1B It is along FIG. 1A A cross-sectional view of an exemplary transistor 102 plotted along the x-axis. FIG. 1C It is along FIG. 1A A cross-sectional view of an exemplary transistor 102 plotted along the y-axis. FIG. 1D yes FIG. 1A A schematic diagram of an exemplary MTP 4×4 NOR array 104 is provided. It is worth noting that, for clarity, [the diagram is not shown in the original text]. FIG. 1A , FIG. 1B , FIG. 1C and FIG. 1D The diagram illustrates all the features of the semiconductor device 100, and FIG. 1A , FIG. 1B , FIG. 1C and FIG. 1DOnly a portion of the semiconductor structure is illustrated. An exemplary transistor 102 and an exemplary NOR array 104 are disposed in an upper metallization layer, such as between metal layers 5 and 6 or between metal layers 6 and 7. The exemplary transistor 102 includes a source and a drain, as well as other components. Depending on the context, the source / drain region as described in this disclosure may individually or collectively refer to the source or drain.

[0063] like FIG. 1A , FIG. 1B and FIG. 1C As shown, an exemplary FinFET transistor 102 is formed on an oxide layer 106 of a metallization layer, and the FinFET transistor 102 includes a fin structure 108 formed over a portion of the oxide layer 106, a storage gate 110 formed over a channel region of the fin structure 108 and configured to store electrons emitted by the fin structure 108 on a portion of the oxide layer 106, a first control gate 112 formed over the oxide layer 106 and on a first sidewall of the storage gate 110, and a second control gate 114 formed over the oxide layer 106 and on a second sidewall of the storage gate 110. The exemplary FinFET transistor 102 further includes a high-k dielectric layer 116 disposed between the fin structure 108 and the storage gate 110, between the storage gate 110 and the oxide layer 106, between the first control gate 112 and the oxide layer 106, and between the second control gate 114 and the oxide layer 106.

[0064] like FIG. 1A , FIG. 1B , FIG. 1C and FIG. 1D As shown, in the exemplary NOR array 104, the fin structures 108 of four series-connected FinFET transistors 102 in four groups are connected in series to form four rows 115. The control gates 112, 114 of the FinFET transistors 102 are connected to form four word line (WL) columns 117. Each WL column 117 is connected to a different word line WL (e.g., word line WL). n WL n+1 WL n+2 WL n+3 Each row 115 of the fin structure 108 is connected to a different bit line (BL) at the end of the row (e.g., bit line BL). k BL k+1 BL k+2 BL k+3 Furthermore, the source / drain connections between adjacent FinFET transistors 102 in row 115 of fin structure 108 are alternately connected to different source lines 119 (e.g., source line SL) in row 115 of fin structure 108. m SLm+1 (or bit line). In this disclosure, the source and drain are interchangeable, and the source and drain structures are essentially the same.

[0065] FIG. 2A and FIG. 2B This is a cross-sectional view of a portion of an exemplary semiconductor device 200. It is worth noting that, for clarity, details are not shown. FIG. 2A and FIG. 2B The diagram illustrates all the features of the semiconductor device 200, and FIG. 2A and FIG. 2B Only a portion of the semiconductor structure is shown. FIG. 2A It is a cross-sectional view along the y-axis. FIG. 2B This is a cross-sectional view along the x-axis. An exemplary semiconductor device 200 includes a semiconductor substrate 202 and an interconnect structure 204.

[0066] Semiconductor substrate 202 may be a semiconductor substrate, such as the active layer of a doped or undoped silicon (Si) or semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include semiconductor materials such as Si, Ge, Ga, Zn, In, or O. The semiconductor substrate may also include other semiconductor materials, such as compound semiconductors like silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0067] Semiconductor substrate 202 may include any number of conductive components and logic devices 206 formed in and / or on the semiconductor substrate. Conductive components may include, for example, plugs, interconnect structures, wiring, etc. Logic devices 206 may include, for example, transistors, diodes, capacitors, and logic devices formed therefrom. For example, transistors may be metal oxide semiconductor field-effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, planar FETs, such as p-channel field-effect transistors (PFETs) or n-channel field-effect transistors (NFETs), FinFETs, gate-all-around (GAA) FET devices, or other suitable elements. In various embodiments, a transistor includes a source, drain, gate electrode, gate dielectric, and channel. Substrate 202 may further include isolation components (not shown), such as shallow trench isolation (STI) components, deep trench isolation (DTI) components, or local oxidation of silicon (LOCOS) components. Isolation components can define and isolate various device elements.

[0068] Interconnect structure 204 provides wiring and electrical connections between logic devices 206 formed in and / or on substrate 202. Interconnect structure 204 may include multiple metallization layers (also referred to herein as metal wiring layers), such as a first metallization layer 204-1, a second metallization layer 204-2, a third metallization layer 204-3, a fourth metallization layer 204-4, a fifth metallization layer 204-5, a sixth metallization layer 204-6, and a seventh metallization layer 204-7, as follows: FIG. 2A and FIG. 2B As shown.

[0069] The exemplary first, second, third, fourth, fifth, sixth, and seventh metallization layers 204-1, 204-2, 204-3, 204-4, 204-5, 204-6, and 204-7 respectively include a first inter-metal dielectric (IMD) layer 208-1, a second IMD layer 208-2, a third IMD layer 208-3, a fourth IMD layer 208-4, a fifth IMD layer 208-5, a sixth IMD layer 208-6, and an IMD metallization layer 208-7. The first, second, third, fourth, fifth, sixth, and seventh metallization layers 204-1, 204-2, 204-3, 204-4, 204-5, 204-6, and 204-7 may include one or more conductive components. In this example, the conductive components include metal lines 210 and / or vias 212 formed in the metallization layers. The conductive components can be electrically connected to the active and / or passive elements of the substrate 202 via contacts (not shown in the figure).

[0070] In various embodiments, interconnect structure 204 electrically connects the source, drain, gate electrode, gate dielectric and / or channel of transistors and other components on substrate 202 to other components or logic devices 206 on substrate 202 or located in interconnect structure 204.

[0071] In some embodiments, the interconnect structure 204 may be formed using a single damascene process and / or a dual damascene process, a via-first process, or a metal-first process. In one embodiment, acceptable lithography, deposition, and etching techniques may be used to form the IMD layers (e.g., 208-1, 208-2, 208-3, 208-4, 208-5, 208-6, 208-7) and openings (not shown). The first, second, third, fourth, fifth, sixth, and seventh IMD layers (208-1, 208-2, 208-3, 208-4, 208-5, 208-6, 208-7) may be, for example, or comprise oxide films, such as silicon oxide, undoped silicon glass (USG), fluorosilicate glass (FSG), boron doped silicate glass (BSG), phosphosilicate glass (PSG), boronphosphorous-doped silicate glass (BPSG), polyethylene oxide (PEOX), thermal oxides, silicon dioxide (SiO2), or other suitable dielectric materials. One or more layers in the IMD layer (e.g., 208-1, 208-2, 208-3, 208-4, 208-5, 208-6, 208-7) can be formed of a low dielectric constant (low k) material, for example, a dielectric constant less than about 3.0 or less than about 2.5.

[0072] The metal wires 210 and / or vias 212 can be formed in the openings of the IMD layer by conductive materials, such as copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), titanium (Ti), titanium nitride (TiN), gallium (Ga), zinc (Zn), ruthenium (Ru), molybdenum (Mo), indium tin oxide (ITO), combinations thereof, or other suitable materials. The conductive material can be formed in the openings using electrochemical plating, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof. After forming the conductive material, a planarization process, such as chemical mechanical polishing (CMP), can be used to remove excess conductive material, leaving conductive components in the openings of the insulating layer. This process can then be repeated to form additional insulating layers and conductive components.FIG. 2A and FIG. 2B The interconnect structure 204 shown is for illustrative purposes only, and the interconnect structure 204 may include other configurations and include one or more metal lines and IMD layers.

[0073] An exemplary FinFET transistor 216 is formed on the oxide of the IMD layer 208-4 of the metallization layer 204-4, and the FinFET transistor 216 includes a fin structure 218 formed above a portion of the IMD layer 208-4, a storage gate 220 formed above a channel region of the fin structure 218 and a portion of the IMD layer 208-4 above it, a first control gate 222 formed above the IMD layer 208-4 and located on a first sidewall of the storage gate 220, and a second control gate 224 formed above the IMD layer 208-4 and located on a second sidewall of the storage gate 220. An exemplary FinFET transistor 216 further includes a high-k dielectric layer 227 (e.g., having a dielectric constant greater than about 3.0), and the high-k dielectric layer 227 is located between the fin structure 218 and the storage gate 220, between the storage gate 220 and the IMD layer 208-4, between the first control gate 222 and the IMD layer 208-4, and between the second control gate 224 and the IMD layer 208-4.

[0074] An exemplary FinFET transistor 216 is formed in the fifth metallization layer 204-5 and forms part of a NOR device, which forms an MTP NVM memory cell. In this example, the first source / drain region of the fin structure 218 can be connected to the source line or source / drain region of another memory cell transistor via via 225 to a metal line 210 located in the sixth metallization layer 204-6. The second source / drain region of the fin structure 218 can be connected to the bit line or source / drain region of another memory cell transistor via via 226 to another metal line 210 located in the sixth metallization layer 204-6. Thus, the control gate (a combination of the first control gate 222 and the second control gate 224) is connected to the word line via via 228 to another metal line 210 in the seventh metallization layer 204-7, and via vias 230 and 232 to the metal line 210 in the sixth metallization layer 204-6.

[0075] FIG. 3A This is a top view of a portion of an exemplary semiconductor device 300 according to various embodiments. The exemplary semiconductor device 300 includes a plurality of FinFET transistors 302 configured as an MTP NAND array 304. FIG. 3B Along with various embodiments FIG. 3A A cross-sectional view of an exemplary transistor 302 plotted along the x-axis. FIG. 3CAlong with various embodiments FIG. 3A A cross-sectional view of an exemplary transistor 302 plotted along the y-axis. FIG. 3D These are exemplary embodiments. FIG. 3A A schematic diagram of the MTP NAND array 304. It is worth noting that, for clarity, [the diagram is not shown in the original text]. FIG. 3A , FIG. 3B , FIG. 3C and FIG. 3D The diagram illustrates all the features of the semiconductor device 300, and FIG. 3A , FIG. 3B , FIG. 3C and FIG. 3D Only a portion of the semiconductor structure is shown. Exemplary transistor 302 and exemplary NAND array 304 are disposed in the upper metallization layer, such as between metal layer 5 and metal layer 6 or between metal layer 6 and metal layer 7.

[0076] like FIG. 3A , FIG. 3B and FIG. 3C As shown, an exemplary FinFET transistor 302 is formed on an oxide layer 306 of a metallization layer, and includes a fin structure 308 formed over a portion of the oxide layer 306, a channel region formed on the fin structure 308, a storage gate 310 formed over a portion of the oxide layer 306 configured to store electrons emitted by the fin structure 308, a first control gate 312 formed over the oxide layer 306 and located on a first sidewall of the storage gate 310, and a second control gate 314 formed over the oxide layer 306 and located on a second sidewall of the storage gate 310. The exemplary FinFET transistor 302 further includes a high-k dielectric layer 316, which is located between the fin structure 308 and the storage gate 310, between the storage gate 310 and the oxide layer 306, between the first control gate 312 and 306, and between the second control gate 314 and the oxide layer 306.

[0077] like FIG. 3A , FIG. 3B , FIG. 3C and FIG. 3D As shown, in the exemplary NAND array 304, the fin structures 308 of two sets of series-connected FinFET transistors 302 are connected in series to form two rows 315 (e.g., BL). m BL m+1 The control gates 312 and 314 of the FinFET transistor 302 are connected to form WL columns 317. Each WL column 317 is connected to a different word line (e.g., WL0, WL1, WL2). nEach row 315 of the fin structure 308 is connected at one end to a different bit line (e.g., and at the other end to a ground select transistor 319). Furthermore, the source / drain connections between adjacent FinFET transistors 302 in the row 315 of the fin structure 308 are interconnected. Bit line select transistors 321 (e.g., formed between metal wiring layers or on the substrate) are connected between the bit line and the first (FinFET transistor 302) of the plurality of MTP NVM memory cells, and ground select transistors 319 (e.g., formed between metal wiring layers or on the substrate) are connected between a ground source and the second (FinFET transistor 302) of the plurality of MTP NVM memory cells.

[0078] FIG. 4A and FIG. 4B This is a cross-sectional view of a portion of an exemplary semiconductor device 400 according to various embodiments. It is worth noting that, for clarity, details are not shown in the diagram. FIG. 4A and FIG. 4B The diagram illustrates all the features of the semiconductor device 100, and FIG. 4A and FIG. 4B Only a portion of the semiconductor structure is shown. FIG. 4A It is a cross-sectional view along the y-axis. FIG. 4B This is a cross-sectional view along the x-axis. An exemplary semiconductor device 400 includes a semiconductor substrate 402 and an interconnect structure 404.

[0079] Semiconductor substrate 402 may be a semiconductor substrate, such as doped or undoped silicon, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0080] Semiconductor substrate 402 may include any number of conductive components and logic devices 406 formed in and / or on the semiconductor substrate. Conductive components may include, for example, plugs, interconnects, wiring, etc. Logic devices 406 may include, for example, transistors, diodes, capacitors, etc. For example, transistors may be metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, planar FETs, such as p-channel field-effect transistors (PFETs) or n-channel field-effect transistors (NFETs), FinFETs, gate-all-around (GAA) FET devices, or other suitable elements. In various embodiments, a transistor includes a source, drain, gate electrode, gate dielectric, and channel. Substrate 402 may further include isolation components (not shown), such as shallow trench isolation (STI) components, deep trench isolation (DTI) components, or localized silicon oxide (LOCOS) components. Isolation components may define and isolate various device elements.

[0081] Interconnect structure 404 provides wiring and electrical connections between logic devices 406 formed in and / or on substrate 402. Interconnect structure 404 may include multiple metallization layers (also referred to herein as metal wiring layers), such as a first metallization layer 404-1, a second metallization layer 404-2, a third metallization layer 404-3, a fourth metallization layer 404-4, a fifth metallization layer 404-5, a sixth metallization layer 404-6, and a seventh metallization layer 404-7, as follows: FIG. 4A and FIG. 4B As shown.

[0082] The exemplary first, second, third, fourth, fifth, sixth, and seventh metallization layers 404-1, 404-2, 404-3, 404-4, 404-5, 404-6, and 404-7 respectively include a first intermetallic dielectric (IMD) layer 408-1, a second IMD layer 408-2, a third IMD layer 408-3, a fourth IMD layer 408-4, a fifth IMD layer 408-5, a sixth IMD layer 408-6, and an IMD metallization layer 408-7. The first, second, third, fourth, fifth, sixth, and seventh metallization layers 404-1, 404-2, 404-3, 404-4, 404-5, 404-6, and 404-7 may include one or more conductive components. In this example, the conductive components include metal lines 410 and / or vias 412 formed in the metallization layers. The conductive components can be electrically connected to the active and / or passive elements of the substrate 402 through contact points (not shown in the figure).

[0083] In various embodiments, interconnect structure 404 electrically connects the source, drain, gate electrode, gate dielectric and / or channel of transistors and other components on substrate 402 to other components or logic devices 406 on substrate 402 or in interconnect structure 404.

[0084] In some embodiments, the interconnect structure 404 may be formed using a single damascene process and / or a dual damascene process, a via-first process, or a metal-first process. In one embodiment, acceptable lithography, deposition, and etching techniques may be used to form the IMD layers (e.g., 408-1, 408-2, 408-3, 408-4, 408-5, 408-6, 408-7) and openings (not shown). The first, second, third, fourth, fifth, sixth, and seventh IMD layers (408-1, 408-2, 408-3, 408-4, 408-5, 408-6, 408-7) may be, for example, or comprise oxide films, such as silicon oxide, undoped silicon glass (USG), fluorosilicate glass (FSG), boron-doped silicate glass (BSG), phosphosilicate glass (PSG), boron-phosphorus-doped silicate glass (BPSG), polyethylene oxide (PEOX), thermal oxides, silicon dioxide (SiO2), or other suitable dielectric materials. One or more layers in the IMD layer (e.g., 408-1, 408-2, 408-3, 408-4, 408-5, 408-6, 208-7) can be formed of a low dielectric constant (low k) material, for example, a dielectric constant less than about 3.0 or less than about 2.5.

[0085] The metal wires 410 and / or vias 412 can be formed in the openings of the IMD layer by conductive materials, such as copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), titanium (Ti), titanium nitride (TiN), gallium (Ga), zinc (Zn), ruthenium (Ru), molybdenum (Mo), indium tin oxide (ITO), combinations thereof, or other suitable materials. The conductive material can be formed in the openings using electrochemical plating, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or combinations thereof. After forming the conductive material, a planarization process, such as chemical mechanical polishing (CMP), can be used to remove excess conductive material, leaving conductive components in the openings of the insulating layer. This process can then be repeated to form additional insulating layers and conductive components. FIG. 4A and FIG. 4B The interconnect structure 404 shown is for illustrative purposes only, and the interconnect structure 404 may include other configurations and include one or more metal lines and IMD layers.

[0086] An exemplary FinFET transistor 416 is formed on the oxide of the IMD layer 408-4 of the metallization layer 404-4, and the FinFET transistor 416 includes a fin structure 418 formed above a portion of the IMD layer 408-4, a storage gate 420 formed above a channel region of the fin structure 418 and a portion of the IMD layer 408-4 above it, a first control gate 422 formed above the IMD layer 408-4 and located on a first sidewall of the storage gate 420, and a second control gate 424 formed above the IMD layer 408-4 and located on a second sidewall of the storage gate 420. An exemplary FinFET transistor 416 further includes a high-k dielectric layer 427 (e.g., having a dielectric constant greater than about 3.0), and the high-k dielectric layer 427 is located between the fin structure 418 and the storage gate 420, between the storage gate 420 and the IMD layer 408-4, between the first control gate 422 and the IMD layer 408-4, and between the second control gate 424 and the IMD layer 408-4.

[0087] An exemplary FinFET transistor 416 is formed in the fifth metallization layer 404-5 and forms part of a NAND device, which forms an MTP NVM memory cell. In this example, the first source / drain region of the fin structure 418 can be connected to the source / drain region of a BL select transistor or the source / drain region of another memory cell transistor via a via 425 connected to a metal line 410 located in the sixth metallization layer 404-6. The second source / drain region of the fin structure 418 can be connected to the source / drain region of a ground select transistor or the source / drain region of another memory cell transistor via a via 426 connected to another metal line 410 located in the sixth metallization layer 404-6. In this way, the control gate (a combination of the first control gate 422 and the second control gate 424) is connected to the word line through the metal line 210 of the sixth metallization layer 404-6 via the metal line 210 of the sixth metallization layer 404-6 via the metal line 210 of the metal line 210 of the sixth metallization layer 404-6 via the metal line 210 and the metal line 210 via ...

[0088] FIG. 5 A flowchart illustrating an exemplary method 500 for manufacturing a semiconductor device according to various embodiments is provided. (Cross-reference) FIG. 1B to FIG. 1C and FIG. 2A to FIG. 2B This is to provide an exemplary embodiment after the steps of the exemplary method 500 have been completed.

[0089] Exemplary method 500 includes, in step 502, providing a substrate having logic devices formed on a substrate and an interconnect structure formed above the substrate. In various embodiments, the interconnect structure includes a plurality of metal wiring layers disposed above the substrate, wherein the metal wiring layers are connected to the logic devices via metal wiring. In various embodiments, the plurality of metal wiring layers includes an upper metal wiring layer having metal lines, vias, and oxide layers. See also FIG. 1B to FIG. 1C and FIG. 2A to FIG. 2B In an exemplary embodiment of step 502, a substrate 202 is provided. The substrate 202 has a logic device 206 formed on the substrate and an interconnect structure 204 disposed above the substrate. The interconnect structure 204 has a plurality of metal wiring layers (e.g., metallization layers 204-1, 204-2, 204-3, 204-4, 204-5, 204-6, 204-7). The metal wiring layers (e.g., metallization layers 204-1, 204-2, 204-3, 204-4, 204-5, 204-6, 204-7) include metal lines 210 connected to the logic device 206 and vias 212. The metal wiring layers (e.g., metallization layers 204-1, 204-2, 204-3, 204-4, 204-5, 204-6, 204-7) include an upper metal wiring layer 204-4 having metal lines 210, vias 212, and an oxide layer 208-4. In various embodiments, the logic device 206 includes a transistor device, such as a planar FET, FinFET, or GAA FET device. In various embodiments, the logic device 206 includes a gate dielectric (e.g., HfO2, SiO2, HfO, HfO2, La, SiON, SiCON, Zn, Zr, etc.), a gate electrode (e.g., polysilicon, Si, Ti, Ta, Al, W, N, Zn, In, Ga, Ge, C, etc.), a source electrode and a drain electrode (wherein the source / drain electrode includes Si, Ge, C, P, B, etc.), and a nanosheet channel (e.g., Si). In various embodiments, the substrate includes Si, Ge, Ga, Zn, In, or O. In various embodiments, the substrate includes a logic device isolation structure. In various embodiments, the logic device isolation structure in the substrate includes local silicon oxide (LOCOS), shallow trench isolation (STI), and deep trench isolation (DTI).

[0090] In step 504, exemplary method 500 includes planarizing the oxide layer of the upper metal wiring layer of the interconnect structure. In various embodiments, a CMP step is used to perform the oxide layer planarization. See also FIG. 1B to FIG. 1C and FIG. 2A to FIG. 2BIn an exemplary embodiment of step 504, the oxide layer 106 / 208-4 has been planarized. In some embodiments, the oxide layer may be referred to as an interlayer dielectric (ILD) layer. In some embodiments, the material of the oxide layer includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or a low-k material. The dielectric layer can be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), or other suitable methods.

[0091] In step 506, exemplary method 500 includes forming a fin structure over a portion of an oxide layer. In various embodiments, forming the fin structure includes depositing an indium gallium zinc oxide (IGZO) layer. Indium gallium zinc oxide (IGZO) is a semiconductor material composed of indium (In), gallium (Ga), zinc (Zn), and oxygen (O). Using IGZO, fins can be formed at temperatures below 400°C. In various embodiments, IGZO is deposited using ALD or PVD. In various embodiments, after depositing IGZO, the deposited IGZO forms a fin structure. In various embodiments, the fin structure is formed by cutting and etching the IGZO layer into a fin structure using lithography, patterning, and etching techniques. See also... FIG. 1B to FIG. 1C and FIG. 2A to FIG. 2B In an exemplary embodiment of step 506, a fin structure 108 / 218 is formed over a portion of the oxide layer 106 / 208-4.

[0092] In step 508, exemplary method 500 includes forming a high-k dielectric layer over the oxide layer and the fin structure. In various embodiments, the high-k dielectric layer is formed over the oxide layer and the fin structure using a deposition process such as ALD. In various embodiments, the high-k dielectric includes hafnium oxide (HfO2). See also FIG. 1B to FIG. 1C and FIG. 2A to FIG. 2B In an exemplary embodiment of step 508, a high-k dielectric layer 116 / 227 is formed over the oxide layer 106 / 208-4 and the fin structure 108 / 218.

[0093] In step 510, exemplary method 500 includes forming a storage gate over the channel region of the fin structure. In various embodiments, the storage gate is a nitride storage gate formed of silicon nitride (SiN). In various embodiments, the storage gate is a nitride storage gate formed of titanium nitride (TiN). In various embodiments, the storage gate is formed of both TiN and SiN. In various embodiments, the storage gate is formed by a deposition process such as CVD or PVD. See also FIG. 1B to FIG. 1C and FIG. 2A to FIG. 2BIn an exemplary embodiment of step 510, the storage gate 110 / 220 is formed above the channel region of the fin structure 108 / 218.

[0094] In step 512, the exemplary method 500 includes forming a control gate, wherein forming the control gate includes a first control gate on a first side of the storage gate above the oxide layer and a second control gate on a second side of the storage gate above the oxide layer. In various embodiments, forming the control gate includes depositing a control gate material layer over and around the storage gate using a suitable deposition technique and planarizing the control gate material layer (e.g., by CMP) to separate the first control gate from the second control gate. In various embodiments, the control gate is formed of a nitride such as titanium nitride (TiN) or tantalum nitride (TaN). In various embodiments, the control gate is formed of polysilicon, Si, Ti, Ta, Al, W, N, Zn, In, Ga, Ge, or C. See also FIG. 2A and FIG. 2B In an exemplary embodiment of step 512, a control gate is formed, which includes a first control gate 112 / 222 formed on a first side of the storage gate 110 / 220 located above the oxide layer 106 / 208-4 and a second control gate 114 / 224 formed on a second side of the storage gate 110 / 220 located above the oxide layer 106 / 208-4.

[0095] In step 514, exemplary method 500 includes connecting at least one of the control gate and source / drain regions of the fin structure to a logic device using vias and metal lines. In various embodiments, connecting at least one of the control gate and source / drain regions of the fin structure to the logic device vias and metal lines includes: depositing an IMD oxide layer over the fin structure, the control gate, and the storage gate; patterning and etching the IMD oxide layer to cut openings configured to form vias and metal lines connecting to at least one of the control gate and source / drain regions of the fin structure; and depositing a metal layer configured to form the vias and metal lines. In some embodiments, the material of the vias and metal lines may include metals such as copper, titanium, tungsten, aluminum, or combinations thereof. The vias and metal lines may be formed by CVD or electroplating. See also ​ In the exemplary embodiment of step 514, the control gate is connected to the logic device 206 via through-holes 230 and 232, and connected to the metal lines 210 and 212. (See also...) ​ In the exemplary embodiment of step 514, the first source / drain region of the fin structure 218 is connected to the logic device 206 through the through hole 225, the metal line 210, and the through hole 212; and the second source / drain region of the fin structure 218 is connected to the logic device 206 through the through hole 226, the metal line 210, and the through hole 212.

[0096] At step 516, method 500 may include further fabrication steps to complete the integrated circuit. Further processing steps may include forming further interconnects between various elements of the semiconductor device. In various embodiments, method 500 may include forming interconnect structures to form a NOR device. In various embodiments, method 500 may include forming interconnect structures to form a NAND device. In various embodiments, method 500 may include connecting a first source / drain region of the fin structure to a source line, connecting a second source / drain region of the fin structure to a bit line, and connecting a control gate to a word line. In various embodiments, method 500 may include connecting a first source / drain region of the fin structure to the source / drain region of a first series transistor, connecting a second source / drain region of the fin structure to the source / drain region of a second series transistor, and connecting a control gate to a word line.

[0097] In some embodiments, the technology disclosed herein relates to a semiconductor device, comprising: a substrate on which logic devices are formed; a plurality of metal wiring layers disposed above the substrate and connected to the logic devices via metal wiring; and a plurality of multiple programmable (MTP) nonvolatile memory (NVM) cells formed between the metal wiring layers, wherein the multiple programmable NVM cells include a FinFET transistor having a fin structure, a storage gate disposed around a plurality of channel regions of the fin structure, and a control gate formed around a plurality of sidewalls of the storage gate, wherein the channel regions of the fin structure are configured to store electrons emitted by the fin structure.

[0098] In some embodiments, the technology described herein relates to a semiconductor device in which a plurality of memory cells are formed in a back-end process (BEOL).

[0099] In some embodiments, the technology described herein relates to a semiconductor device in which a plurality of multiple-programmable non-volatile memory cells include NOR devices.

[0100] In some embodiments, the technology described herein relates to a semiconductor device in which a first source / drain region of a fin structure is connected to a source line, a second source / drain region of a fin structure is connected to a bit line, and a control gate is connected to a word line.

[0101] In some embodiments, the technology disclosed herein relates to a semiconductor device in which a multiple-programmable non-volatile memory cell includes a NAND device.

[0102] In some embodiments, the technology described herein relates to a semiconductor device in which a first source / drain region of a fin structure is connected to the source / drain region of a first series transistor (e.g., formed between multiple metal wiring layers), a second source / drain region of a fin structure is connected to the source / drain region of a second series transistor (e.g., formed between multiple metal wiring layers), and a control gate is connected to a word line.

[0103] In some embodiments, the technology described herein relates to a semiconductor device, further comprising a bit line selection transistor (e.g., formed between multiple metal wiring layers or formed on a substrate) and a ground selection transistor (e.g., formed between multiple metal wiring layers or formed on a substrate). The bit line selection transistor is connected between a bit line and a first of a plurality of multiple programmable non-volatile memory cells. The ground selection transistor is connected between a ground source and a second of a plurality of multiple programmable non-volatile memory cells.

[0104] In some embodiments, the technology described herein relates to a semiconductor device in which the fin structure is formed of indium gallium zinc oxide (IGZO).

[0105] In some embodiments, the technology described herein relates to a semiconductor device in which the storage gate is formed of silicon nitride (SiN).

[0106] In some embodiments, the technology described herein relates to a semiconductor device in which the control gate is formed of titanium nitride (TiN).

[0107] In some embodiments, the technology described herein relates to a semiconductor device that further includes a high-k dielectric (e.g., hafnium oxide (HfO2)). The high-k dielectric is formed between the storage gate and the fin structure.

[0108] In some embodiments, the technology disclosed herein relates to a semiconductor device, wherein the logic device includes a gate dielectric (e.g., SiO2, HfO, La, SiON, SiCON, Zn, Zr), a gate dielectric (e.g., polysilicon, Si, Ti, Ta, Al, W, N, Zn, In, Ga, Ge, C), a source, a drain (e.g., the source / drain includes Si, Ge, C, P, B), and a nanosheet channel (e.g., Si).

[0109] In some embodiments, the technology disclosed herein relates to a semiconductor device, wherein the substrate comprises Si, Ge, Ga, Zn, In, or O.

[0110] In some embodiments, the technology described herein relates to a semiconductor device in which the logic device isolation structure in the substrate includes local silicon oxide (LOCOS), shallow trench isolation (STI), and deep trench isolation (DTI).

[0111] In some embodiments, the technology disclosed herein relates to a semiconductor device, wherein the logic device includes a planar FET, a FinFET, or a gate-all-around (GAA) FET device.

[0112] In some embodiments, the technology disclosed herein relates to a method of manufacturing a semiconductor device, comprising: providing a substrate having a logic device formed on the substrate and a plurality of metal wiring layers disposed above the logic device, wherein the substrate is connected to the logic device via the metal wiring layers, wherein the plurality of metal wiring layers includes an upper metal wiring layer having a plurality of metal lines, a plurality of vias and a planarized oxide layer; forming a fin structure on the oxide layer in the upper metal wiring layer formed of indium gallium zinc oxide (IGZO); forming a high-k dielectric layer above the oxide layer and the fin structure; forming a storage gate above a plurality of channel regions of the fin structure; forming a control gate on a first side and a second side of the storage gate; and connecting at least one of the control gate and the source / drain regions of the fin structure to the logic device via the vias and metal lines.

[0113] In some embodiments, the technology described herein relates to a method of manufacturing a semiconductor device, wherein forming a fin structure on an oxide layer in an upper metal wiring layer formed of indium gallium zinc oxide (IGZO) includes: depositing an indium gallium zinc oxide layer (IGZO layer) by atomic layer deposition (ALD) or physical vapor deposition (PVD), and forming the deposited IGZO layer into a fin structure by patterning and etching techniques.

[0114] In some embodiments, forming a high-k dielectric layer over the oxide layer and the fin structure includes depositing the high-k dielectric layer by atomic layer deposition (ALD), wherein the high-k dielectric layer includes hafnium oxide (HfO2).

[0115] In some embodiments, the technology disclosed herein relates to a method of manufacturing a semiconductor device, wherein forming a storage gate includes: forming a nitride storage gate from silicon nitride (SiN) by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0116] In some embodiments, the technology disclosed herein relates to a method of manufacturing a semiconductor device, wherein forming a control gate includes: depositing a control gate material layer formed of titanium nitride (TiN) or tantalum nitride (TaN) above and around the storage gate, and using chemical mechanical polishing (CMP) to planarize the control gate material layer to separate a first control gate and a second control gate.

[0117] In some embodiments, the technology described herein relates to a method of manufacturing a semiconductor device, the method further comprising: connecting a first source / drain region of a fin structure to a source line, connecting a second source / drain region of the fin structure to a bit line, and connecting a control gate to a word line.

[0118] In some embodiments, the technology described herein relates to a method of manufacturing a semiconductor device, the method further comprising: connecting a first source / drain region of a fin structure to the source / drain region of a first series transistor (e.g., formed between multiple metal wiring layers), connecting a second source / drain region of the fin structure to the source / drain region of a second series transistor (e.g., formed between multiple metal wiring layers), and connecting a control gate to a word line.

[0119] In some embodiments, the technology described herein relates to a memory device, comprising: a logic device; a plurality of metal wiring layers connected to the logic device via a metal wiring; and a multiple programmable (MTP) nonvolatile memory (NVM) cell located between the plurality of metal wiring layers and formed in a back-end process (BEOL), wherein the multiple programmable NVM cell includes a fin field-effect transistor (FinFET) having an indium gallium zinc oxide fin (IGZO fin), a storage gate disposed around a plurality of channel regions of the indium gallium zinc oxide fin, and a control gate formed around a plurality of sidewalls of the storage gate.

[0120] In some embodiments, the technology described herein relates to a memory device, comprising: a logic device; a plurality of metal wiring layers connected to the logic device via metal wiring; and a multiple programmable non-volatile memory cell located between the metal wiring layers, wherein the multiple programmable non-volatile memory cell includes a fin field-effect transistor having an indium gallium zinc oxide fin, a storage gate disposed around a plurality of channel regions of the indium gallium zinc oxide fin, and a control gate formed around a plurality of sidewalls of the storage gate.

[0121] In some embodiments, the technology disclosed herein relates to a memory device in which multiple programmable nonvolatile memory cells are connected to a plurality of other memory cells to form a NOR device.

[0122] In some embodiments, the technology disclosed herein relates to a memory device in which multiple programmable nonvolatile memory cells are connected to a plurality of other memory cells to form a NAND device.

[0123] In some embodiments, the technology disclosed herein relates to a memory device in which the storage gate is formed of silicon nitride (SiN).

[0124] In some embodiments, the technology described herein relates to a memory device in which the control gate is formed of titanium nitride (TiN).

[0125] In some embodiments, the technology disclosed herein relates to a memory device that further includes a high-k dielectric (e.g., hafnium oxide (HfO2)). The high-k dielectric is formed between the storage gate and the IGZO fin.

[0126] In some embodiments, the technology disclosed herein relates to a memory device, wherein the logic device includes a gate dielectric (e.g., SiO2, HfO, La, SiON, SiCON, Zn, Zr), a gate electrode (e.g., polysilicon, Si, Ti, Ta, Al, W, N, Zn, In, Ga, Ge, C), a source electrode, a drain electrode (e.g., the source / drain includes Si, Ge, C, P, B), and a nanosheet channel (e.g., Si).

[0127] In some embodiments, the technology described herein relates to a memory device, wherein the logic device includes a planar FET, a FinFET, or a gate-all-around (GAA) FET device.

[0128] In some embodiments, the technology disclosed herein relates to a semiconductor device, comprising: a substrate having logic devices formed on the substrate; a plurality of metal wiring layers disposed above the substrate and the logic devices, wherein the metal wiring layers include an upper metal wiring layer disposed among the plurality of metal wiring layers, and the upper metal wiring layer includes a plurality of metal lines, a plurality of vias, and an oxide layer; a fin structure disposed on the metal wiring layers, and the fin structure includes a plurality of channel regions and a first source / drain region and a second source / drain region respectively located on both sides of the channel regions; a dielectric layer disposed on the upper metal wiring layer and the fin structure; a storage gate disposed above the channel regions of the fin structure; a control gate disposed on a first side and a second side of the storage gate; and the control gate and at least one of the first source / drain regions and the second source / drain regions of the fin structure being connected to the logic devices through vias and metal lines.

[0129] In some embodiments, the technology disclosed herein relates to a semiconductor device, and the semiconductor device further includes a control gate layer disposed above and around a storage gate.

[0130] In some embodiments, the technology disclosed herein relates to a semiconductor device, wherein the control gate includes a first control gate disposed on a first side of the storage gate; and a second control gate disposed on a second side of the storage gate, wherein the top surface of the first control gate and the top surface of the second control gate are coplanar.

[0131] In some embodiments, the technology disclosed herein relates to a semiconductor device in which a first source / drain region of a fin structure is connected to a source line, a second source / drain region of a fin structure is connected to a bit line, and a control gate is connected to a word line.

[0132] In some embodiments, the technology disclosed herein relates to a semiconductor device in which a first source / drain region of a fin structure is connected to the source / drain region of a first series transistor, a second source / drain region of the fin structure is connected to the source / drain region of a second series transistor, and a control gate connection is connected to a word line.

[0133] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the various embodiments disclosed herein. Those skilled in the art should understand that they can simply use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A substrate, wherein the substrate has a logic device formed on the substrate; Multiple metal wiring layers are disposed above the substrate, wherein the multiple metal wiring layers are connected to the logic device through metal wiring; as well as Multiple reprogrammable non-volatile memory cells are formed between the multiple metal wiring layers, wherein the multiple reprogrammable non-volatile memory cells include a fin field-effect transistor having a fin structure, a storage gate disposed around multiple channel regions of the fin structure, and a control gate formed around multiple sidewalls of the storage gate.

2. The semiconductor device as claimed in claim 1, characterized in that, A first source / drain region of the fin structure is connected to a source line, a second source / drain region of the fin structure is connected to a bit line, and the control gate is connected to a word line.

3. The semiconductor device as claimed in claim 1, characterized in that, A first source / drain region of the fin structure is connected to the source / drain region of a first series transistor, a second source / drain region of the fin structure is connected to the source / drain region of a second series transistor, and the control gate is connected to a word line.

4. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A high-k dielectric is formed between the storage gate and the fin structure.

5. A semiconductor device, characterized in that, include: A substrate, wherein the substrate has a logic device formed on the substrate; Multiple metal wiring layers are disposed above the substrate and the logic device, wherein the multiple metal wiring layers include: An upper metal wiring layer is disposed among the plurality of metal wiring layers, wherein the upper metal wiring layer includes a plurality of metal lines, a plurality of vias, and an oxide layer; A fin structure is disposed on the plurality of metal wiring layers, wherein the fin structure includes a plurality of channel regions and a first source / drain region and a second source / drain region respectively located on both sides of each channel region; A dielectric layer is disposed on the upper metal wiring layer and the fin structure; A storage gate is disposed above the plurality of channel regions of the fin structure; and A control gate is disposed on a first side and a second side of the storage gate; The control gate and at least one of the first source / drain region and the second source / drain region of the fin structure are connected to the logic device through the plurality of vias and the plurality of metal lines.

6. The semiconductor device as claimed in claim 5, characterized in that, Further includes: A control gate layer is disposed above and around the storage gate.

7. The semiconductor device as claimed in claim 6, characterized in that, The control gate includes: A first control gate is disposed on the first side of the storage gate; and A second control gate is disposed on the second side of the storage gate. The top surface of the first control gate is coplanar with the top surface of the second control gate.

8. The semiconductor device as claimed in claim 5, characterized in that, The first source / drain region of the fin structure is connected to a source line, the second source / drain region of the fin structure is connected to a bit line, and the control gate is connected to a word line.

9. The semiconductor device as claimed in claim 5, characterized in that, The first source / drain region of the fin structure is connected to a source / drain region of a first series transistor, the second source / drain region of the fin structure is connected to a source / drain region of a second series transistor, and the control gate connection is connected to a word line.

10. A memory device, characterized in that, include: A logic device; Multiple metal wiring layers are connected to the logic device via metal wiring; as well as A reprogrammable non-volatile memory cell is located between the plurality of metal wiring layers, wherein the reprogrammable non-volatile memory cell includes a fin field-effect transistor having a fin, a storage gate disposed around a plurality of channel regions of the fin, and a control gate formed around a plurality of sidewalls of the storage gate.

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