2.2 D packaging structure
By combining the RDL layer and interconnect bridges in the 2.2D packaging structure, high-density chip packaging is achieved, solving the problems of low packaging density and high cost, simplifying the process flow and reducing costs, and adapting to different application needs.
Patent Information
- Application Number
- CN202520141154.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2026-02-10
- Estimated Expiration
- 2035-01-21
AI Technical Summary
Existing chip packaging technologies suffer from low packaging density, high cost, and complex processes, especially in multi-chip packaging where interconnect density is limited and cost is difficult to control.
Employing a 2.2D packaging structure, it achieves high-density vertical interconnects and high-density fine-pitch horizontal lines by setting RDL layers and interconnect bridges on the substrate. It combines interconnect bridges made of silicon, glass or organic polymer materials for horizontal interconnection between chips, simplifying the process and reducing costs.
It increases chip packaging density, reduces package size, supports more pins, simplifies the process flow, reduces costs, and provides design flexibility to adapt to different application needs.
Smart Images
Figure CN223899710U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to microelectronic chip packaging technical field, especially 2.2D packaging structure. BACKGROUND
[0002] For chip packaging, the most basic packaging process is wire-bonding packaging, which is very simple as a whole, that is, the chip is fixed to the substrate with the front face upward, then the pins of the chip are connected (bonded) with the substrate by wires, and finally the whole chip is sealed, and the sealing material is plastic, ceramic, etc. The advantages of this packaging technology are relatively simple production process and low cost, and the disadvantages are that the size of the packaged chip is much larger than that of the original chip, and the number of chip pins is limited. With the progress of technology, "flip-chip" technology has emerged, that is, the chip is bonded with the pre-prepared solder point with the front face downward. The application of flip-chip makes the final packaging size close to the original chip, and there are more pins.
[0003] The above packaging is the packaging of a single chip, and when multiple chips need to be packaged together, the packaging method is currently 2D, 2.5D, and 3D packaging. For 2D packaging, the interconnection between chips relies on the wiring in the substrate. The disadvantage of this method is that the wiring density on the substrate is low, so the interconnection between chips is limited. Therefore, the improved 2.5D packaging adds a layer of silicon interposer between the chip and the substrate, and the chips are not directly connected to each other, but are connected to the silicon interposer, which acts as a chip-chip interconnection and a chip-substrate interconnection. Since the wiring of the silicon interposer can be directly manufactured using semiconductor technology, the wiring density can be greatly improved. The disadvantage of this packaging technology is that since the silicon interposer is also manufactured using semiconductor technology, its cost is difficult to reduce, and its area is severely limited by semiconductor technology. In order to reduce the cost of the silicon interposer, Intel uses EMIB technology to realize the interconnection between chips using a silicon bridge, and the silicon bridge is embedded in the substrate, and the chip-substrate connection is realized by a traditional method. This method can significantly reduce the area of the silicon interposer, reduce the cost, and reduce the limitations of multi-chip packaging, but the cost is still relatively high, and further optimization is needed. UTILITY MODEL CONTENTS
[0004] The utility model aims at the deficiencies in the above background technology, and provides a scheme with high chip packaging density, simple process, and controllable cost.
[0005] In order to achieve the above object, the utility model provides a 2.2D packaging structure, including substrate, RDL layer, first chip, second chip and interconnection bridge, the interconnection circuit is integrated in the substrate, the RDL layer is partially packaged on the upper surface of the substrate, so as to realize the vertical high density interconnection of the substrate and the first chip or the second chip, the interconnection bridge is arranged on the non RDL layer area of the substrate upper surface, and is fixed with the substrate through the adhesive, a plurality of bonding points are arranged on the interconnection bridge and are bonded with the first chip and the second chip, and the high density fine pitch circuit of horizontal interconnection is integrated in the interconnection bridge.
[0006] Further, the size and spacing of the bonding points of the interconnection bridge are consistent with the RDL layer.
[0007] Further, the front surface of the interconnection bridge is provided with the bonding points, and the first chip and the second chip are bonded through the bonding points, and the back surface of the interconnection bridge is fixed with the substrate through the adhesive.
[0008] Further, the material of the interconnection bridge is silicon, glass or organic polymer.
[0009] Further, the bonding positions of the RDL layer, the substrate, the first chip and the second chip, and the bonding positions of the interconnection bridge and the first chip and the second chip are all encapsulated with filling glue.
[0010] Further, the thickness of the RDL layer, the adhesive and the interconnection bridge is set to a preset value, so that the first chip and the second chip are packaged horizontally.
[0011] The above scheme of the utility model has the following beneficial effects:
[0012] The 2.2D packaging structure provided by the utility model realizes the horizontal interconnection of multiple chips through the interconnection bridge made of silicon, glass or organic polymer, so that multiple chips can be integrated into a single package, effectively reducing the overall size of the device; the RDL layer helps to redistribute the I / O connection from the chip to the package, forms vertical high-density interconnection between the bonding points on the chip and the RDL layer, supports more pin numbers, and the I / O contact spacing is more flexible, thereby simplifying assembly and improving the performance of IC; in summary, this RDL layer and interconnection bridge combination scheme provides higher design flexibility, allows selection of appropriate chip combination according to specific application requirements, and can be weighed and optimized according to performance, power consumption and cost, etc. Compared with 2.5D packaging, the process is simpler, and the cost is more controllable.
[0013] Other beneficial effects of the utility model will be described in detail in the subsequent specific embodiment part. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of the overall structure of this utility model;
[0015] Figure 2 This is a schematic diagram of the process route of this utility model.
[0016] [Explanation of Labels in the Attached Image]
[0017] 1-Substrate; 2-RDL layer; 3-First chip; 4-Second chip; 5-Interconnect bridge; 6-Adhesive; 7-Filling adhesive. Detailed Implementation
[0018] To make the technical problems, solutions, and advantages of this utility model clearer, a detailed description will be provided below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model. Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.
[0019] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0020] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a locking connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0021] like Figure 1As shown, an embodiment of this utility model provides a 2.2D package structure, including a substrate 1, an RDL layer 2, a first chip 3, a second chip 4, and interconnect bridges 5. The substrate 1 integrates interconnect lines. The RDL layer 2 is one or more layers of metal lines, which are typically packaged on the substrate 1 in the prior art, enabling communication between external package pins and internal chip pins. In this embodiment, the RDL layer 2 is partially packaged on the upper surface of the substrate 1 to achieve high-density vertical interconnection between the substrate 1 and the chip. Simultaneously, interconnect bridges 5 are provided in areas outside the RDL layer 2 (i.e., areas exposed on the substrate 1), and these interconnect bridges are used for lateral interconnection between the first chip 3 and the second chip 4. Multiple bonding points are densely arranged on the interconnect bridges 5, with the size and spacing of the bonding points consistent with those of the RDL layer 2. Furthermore, the interconnect bridges 5 integrate high-density fine-pitch lines for lateral interconnection, with line width / spacing typically smaller than that of the substrate 1.
[0022] Therefore, based on the high-density vertical interconnection between the first chip 3 and substrate 1, and between the second chip 4 and substrate 1 via RDL layer 2, the interconnect bridge 5 enables high-density horizontal interconnection between the first chip 3 and the second chip 4, achieving higher integration of the entire package, reducing overall size, and providing a relatively stable and efficient transmission path for signal transmission. This approach, known as the 2.2D packaging structure, further reduces design complexity compared to 2.5D packaging, solves the limitation of package interconnection density, and better addresses the issue of process cost.
[0023] It should be noted that in this embodiment, the interconnect bridge 5 is bonded and fixed to the substrate 1 by adhesive 6. Since there are no vertical interconnect lines within the interconnect bridge 5, it is not directly interconnected with the substrate 1. Its main function is to achieve lateral interconnection between the first chip 3 and the second chip 4. The adhesive 6 serves two purposes: firstly, it fixes the interconnect bridge 5, ensuring it is securely packaged on the substrate 1; secondly, based on the properties of the adhesive 6, it can effectively buffer internal stress caused by packaging deformation, further improving packaging quality.
[0024] Therefore, for the interconnect bridge 5, it only needs to set bonding points on the front side to bond with the first chip 3 and the second chip 4, and the back side is fixed to the substrate 1 by adhesive 6, without the need to set bonding points, thus the structure can be further simplified.
[0025] In this embodiment, the interconnect bridge 5 can be made of silicon, glass, or organic polymers. It is worth noting that organic polymers, due to their flexibility, can further buffer internal stress caused by encapsulation deformation, thus offering advantages over materials such as silicon and glass.
[0026] It should be noted that this embodiment uses the first chip 3 and the second chip 4 as examples, and the two chips are horizontally interconnected through the interconnect bridge 5. In practical applications, more chips can be horizontally interconnected simultaneously through one interconnect bridge 5, such as four or six, to further improve the efficient communication between chips and further increase the chip packaging density.
[0027] The process route for the 2.2D packaging structure provided in this embodiment is as follows: Figure 2 As shown, the specific steps include the following:
[0028] S1, Prepare substrate 1 and RDL layer 2, and partially encapsulate RDL layer 2 in a predetermined area of substrate 1.
[0029] S2, apply adhesive 6 to the non-RDL layer 2 region on substrate 1;
[0030] S3, with the front of the interconnect bridge 5 facing up and the back of it attached to the area of the adhesive 6, and fixed by the adhesive 6;
[0031] S4, the first chip 3 and the second chip 4 that need to be interconnected are placed face down and bonded to the corresponding bonding points on the RDL layer 2 and the interconnection bridge 5 for packaging.
[0032] S5, the bonding area is filled and protected with filler glue 7 to complete the 2.2D encapsulation.
[0033] It should be noted that during packaging, it is usually necessary to ensure that the chip is horizontal (relative to the device's own coordinate system) to make the overall thickness of the device thinner and more uniform, and also to allow the heat dissipation structure above the chip to better fit the chip and avoid weakening the heat dissipation effect. Based on this, when considering the above process route, it is necessary to ensure that the thickness of RDL layer 2, adhesive 6, and interconnect bridge 5 is appropriate so that the chip can complete all bonding and be firmly secured in a horizontal position.
[0034] In summary, the 2.2D packaging structure and corresponding process provided in this embodiment achieve lateral interconnection of multiple chips through interconnect bridges 5 made of silicon, glass, or organic polymer materials, enabling multiple chips to be integrated into a single package and effectively reducing the overall size of the device. Combined with RDL layer 2, it helps to redistribute I / O connections from the chip to the package, forming a high-density vertical interconnect between the bonding points on the chip and RDL layer 2, supporting a larger number of pins and more flexible I / O contact spacing, thereby simplifying assembly and improving IC performance. Overall, this combination of RDL layer 2 and interconnect bridge 5 provides greater design flexibility, allowing for the selection of appropriate chip combinations based on specific application requirements. It allows for trade-offs and optimization based on factors such as performance, power consumption, and cost, and compared to 2.5D packaging, the process is simpler and the cost is more controllable.
[0035] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0036] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A 2.2D packaging structure, characterized in that, The device includes a substrate, an RDL layer, a first chip, a second chip, and interconnect bridges. The substrate integrates interconnect lines, and the RDL layer is partially encapsulated on the upper surface of the substrate to achieve high-density vertical interconnection between the substrate and the first chip or the second chip. The interconnect bridges are disposed in the non-RDL layer area on the upper surface of the substrate and are fixed to the substrate by adhesive. The interconnect bridges are provided with multiple bonding points and are bonded to the first chip and the second chip. The interconnect bridges integrate high-density fine-pitch lines for lateral interconnection.
2. The 2.2D packaging structure according to claim 1, characterized in that, The size and spacing of the bonding points of the interconnect bridge are consistent with those of the RDL layer.
3. The 2.2D packaging structure according to claim 1, characterized in that, The interconnect bridge has bonding points on its front side, which are used to bond to the first chip and the second chip. The back side of the interconnect bridge is fixed to the substrate by the adhesive.
4. The 2.2D packaging structure according to claim 1, characterized in that, The interconnect bridge is made of silicon, glass, or organic polymer.
5. A 2.2D packaging structure according to claim 1, characterized in that, The bonding locations of the RDL layer with the substrate, the first chip, and the second chip, as well as the bonding locations of the interconnect bridge with the first chip and the second chip, are all encapsulated with filler adhesive.
6. A 2.2D packaging structure according to any one of claims 1-5, characterized in that, The thicknesses of the RDL layer, the adhesive, and the interconnect bridge are set to preset values so that the first chip and the second chip are horizontal after packaging.