Fan-out wafer level novel 2.2 D packaging structure
By using the novel Fan-out wafer-level 2.2D packaging structure, problems such as low signal transmission efficiency, difficult thermal management, integration and space limitations in existing wafer-level chip packaging are solved, achieving high-density interconnection, enhanced heat dissipation performance and reduced cost.
Patent Information
- Application Number
- CN202520147876.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2026-02-10
- Estimated Expiration
- 2035-01-22
AI Technical Summary
Existing wafer-level chip packaging suffers from problems such as low signal transmission efficiency, difficulty in thermal management, integration and space limitations, insufficient interconnect density, high process complexity, and high cost.
It adopts a novel 2.2D packaging structure at the Fan-out wafer level, including interconnect bridges, solder balls, RDL adapter boards, substrates, and molding layers. Through the design of horizontal and vertical interconnects and underfill layers, it achieves high-density interconnects and improved heat dissipation performance.
It achieves high integration, low parasitic effects, greater design flexibility, thinner package thickness, simplified process and reduced cost, while improving package reliability and heat dissipation performance.
Smart Images
Figure CN223899714U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of microelectronics technology, specifically to a novel 2.2D fan-out wafer-level packaging structure. Background Technology
[0002] Wafer-level chip packaging differs from traditional chip packaging. This latest technology involves packaging and testing on the entire wafer before cutting it into individual IC chips. Therefore, the packaged volume is equivalent to the original size of the bare IC die.
[0003] The existing packaging structure has the following problems:
[0004] 1. Signal transmission efficiency issues;
[0005] 2. As the integration level of integrated circuits increases, the heat generated inside the chip also increases, and traditional packaging methods may not be able to effectively dissipate heat.
[0006] 3. Limitations in integration and space.
[0007] 4. Limitations on package interconnect density.
[0008] 5. The complexity of the process and the cost issues.
[0009] 6. Risks of stress concentration and chip failure. Utility Model Content
[0010] The technical problem to be solved by this utility model is to provide a novel Fan-out wafer-level 2.2D packaging structure to address the shortcomings mentioned in the background art.
[0011] To solve the above-mentioned technical problems, the technical solution provided by this utility model is: a novel Fan-out wafer-level 2.2D packaging structure, including an interconnect bridge and a chip, wherein a first solder ball is soldered around the interconnect bridge, and two chips are provided, symmetrically bonded to the top two ends of the interconnect bridge;
[0012] The interconnect bridge and the bottom of the first solder ball are bonded together to form an RDL adapter board, the bottom of the RDL adapter board is bonded to a second solder ball, and the bottom of the second solder ball is connected to a substrate.
[0013] Furthermore, the interconnect bridge, the first solder ball, and the outer surface of the chip are all provided with an underfill layer, and a molding compound layer is provided on the outer side of the underfill layer.
[0014] Furthermore, the underfill layer is one of epoxy resin, styrene-based materials, silicone-based filler materials, and lead-free underfill materials.
[0015] Furthermore, the molding compound is one of epoxy resin, styrene resin, polyester resin, polytetrafluoroethylene, and polyimide.
[0016] The advantages of this utility model compared with the prior art are: 1. High integration and high-density interconnection;
[0017] 2. Enhanced heat dissipation performance;
[0018] 3. Lower parasitic effects;
[0019] 4. Greater design flexibility;
[0020] 5. Thinner package thickness;
[0021] 6. Simplified process and reduced cost;
[0022] 7. Improve the reliability of the packaging. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of a novel 2.2D fan-out wafer-level packaging structure.
[0024] Figure 2 This is a first structural schematic diagram of a novel fan-out wafer-level 2.2D packaging structure;
[0025] Figure 3 This is a schematic diagram of the second structure of a novel 2.2D fan-out wafer-level packaging structure;
[0026] Figure 4 This is a schematic diagram of the third structure of a novel Fan-out wafer-level 2.2D packaging structure;
[0027] Figure 5 This is a schematic diagram of the fourth structure of a novel Fan-out wafer-level 2.2D packaging structure;
[0028] Figure 6 This is a fifth structural schematic diagram of a novel Fan-out wafer-level 2.2D packaging structure;
[0029] Figure 7 This is a schematic diagram of a novel 2.2D fan-out wafer-level packaging structure and its combination with a temporary carrier board.
[0030] As shown in the figure: 1. Interconnect bridge; 2. First solder ball; 3. Chip; 4. Underfill layer; 5. Molding layer; 6. RDL adapter board; 7. Second solder ball; 8. Substrate; 9. Temporary carrier board. Detailed Implementation
[0031] The present invention will now be described in further detail with reference to the accompanying drawings.
[0032] Combined with appendix Figure 1-7 A novel 2.2D fan-out wafer-level packaging structure includes an interconnect bridge 1 and a chip 3. The interconnect bridge 1 is surrounded by a first solder ball 2. Two chips 3 are symmetrically bonded to the top ends of the interconnect bridge 1. An RDL adapter board 6 is bonded to the bottom of the interconnect bridge 1 and the first solder ball 2. A second solder ball 7 is bonded to the bottom of the RDL adapter board 6. A substrate 8 is connected to the bottom of the second solder ball 7.
[0033] The interconnect bridge 1, the first solder ball 2 and the chip 3 are all provided with an underfill layer 4. The outer side of the underfill layer 4 is provided with a molding compound 5. The underfill layer 4 is one of epoxy resin, styrene, silicon substrate filler material and lead-free underfill material. The molding compound 5 is one of epoxy resin, styrene resin, polyester resin, polytetrafluoroethylene and polyimide.
[0034] The specific production process is as follows:
[0035] like Figure 2 As shown: On the temporary carrier board 9, multiple RDL adapter boards 6 are bonded to each other via second solder balls 7. The material is Si or glass, and lateral interconnection is achieved through the RDL adapter boards 6.
[0036] like Figure 3 As shown: TSV / TGV is used for vertical interconnection within multiple RDL adapter boards 6. This effectively improves signal transmission speed and packaging density, thus the interconnect bridge 1 is a high-density interconnect bridge with bidirectional horizontal and vertical interconnection capabilities.
[0037] like Figure 4 As shown: The first solder ball 2 is soldered around the interconnect bridge 1, and then two chips 3 are bonded on the interconnect bridge 1.
[0038] like Figure 5 As shown: an underfill layer is set around each encapsulation structure using an underfill process, and a molding process is used to set a molding layer 5 for the entire temporary carrier board 9, thereby achieving stress buffering and protection.
[0039] like Figure 6 As shown: Remove the entire temporary carrier board 9, bond the entire structure to the RDL adapter board 6, and finally connect the overall package structure to the substrate 8 through the second solder ball.
[0040] Ultimately, the overall packaging structure is divided into independent packaging structures.
[0041] N independent chip packaging structures are packaged simultaneously on the same substrate 8. The substrate 8 and the interconnect bridge 1 are bonded to the substrate 8 through a welding process. The bottom is filled with underfill material using an underfill process to achieve stress buffering and protection. The temporary carrier board 9 is a wafer, and wafer-level packaging is performed on the entire wafer.
[0042] With the above structure, this utility model has the following advantages:
[0043] 1. High integration and high-density interconnection:
[0044] 2D packaging increases packaging density by adding a redistribution layer (RDL) between the chip and the substrate, enabling more electrical connections within a smaller package area. Compared to traditional 2D packaging, fan-out technology allows multiple chips to be integrated together, reducing the interconnect distance between chips and improving the overall system integration.
[0045] 2. Enhanced heat dissipation performance
[0046] Fan-out packaging improves chip heat dissipation efficiency by reducing the thermal resistance of the packaging material. Compared to traditional packaging, the multi-layer RDL in 2.2D packaging can help conduct and dissipate heat more effectively, solving thermal management problems in high-power applications and thus improving chip reliability.
[0047] 3. Lower parasitic effect
[0048] Because the chip is directly connected to the redistribution layer (RDL) in a fan-out package, the number of solder layers between the chip and the package substrate and the complexity of the interconnect structure are reduced, thereby reducing parasitic inductance and resistance, and minimizing signal delay and signal integrity issues. This is especially important for high-frequency and high-speed signal transmission.
[0049] 4. Greater design flexibility
[0050] Fan-out 2.2D packaging allows for the integration of different types of chips (such as logic chips and memory chips) within a single package, providing flexibility for heterogeneous integration. This design flexibility enables developers to design packages flexibly to meet the needs of different applications, thereby improving product functionality and market competitiveness.
[0051] 5. Thinner package thickness
[0052] Compared to traditional BGA (Ball Grid Array) or CSP (Chip Scale Package) packaging, Fan-out packaging eliminates the need for a packaging substrate, reducing the overall thickness and weight of the package, making it suitable for portable electronic devices and smart devices with strict size and weight requirements.
[0053] 6. Simplified process and reduced cost
[0054] Although 2.2D packaging has a slightly lower packaging density than 3D packaging, its manufacturing process is simpler and its cost is more controllable. Fan-out packaging does not require through-silicon via (TSV) technology like 3D packaging, thus it has advantages in manufacturing complexity and yield, and can reduce the overall packaging cost.
[0055] 7. Improve packaging reliability
[0056] In traditional packaging, the solder joints between the chip and the substrate may fail due to stress concentration. Fan-out packaging reduces the possibility of stress concentration and thermal failure through optimization of the redistribution layer (RDL) and packaging materials, thereby enhancing the reliability and mechanical strength of the package.
[0057] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the inventive spirit of the present invention, such designs should fall within the protection scope of the present invention.
Claims
1. A novel 2.2D fan-out wafer-level packaging structure, comprising an interconnect bridge (1) and a chip (3), characterized in that: The interconnect bridge (1) is surrounded by a first solder ball (2), and two chips (3) are provided, which are symmetrically bonded to the top two ends of the interconnect bridge (1); The interconnect bridge (1) and the first solder ball (2) are bonded together at the bottom of an RDL adapter board (6), the RDL adapter board (6) is bonded to the bottom of a second solder ball (7), and the bottom of the second solder ball (7) is connected to a substrate (8).
2. The novel Fan-out wafer-level 2.2D packaging structure according to claim 1, characterized in that: The interconnect bridge (1), the first solder ball (2) and the chip (3) are all provided with an underfill layer (4), and the outer side of the underfill layer (4) is provided with a molding compound (5).
3. The novel Fan-out wafer-level 2.2D packaging structure according to claim 2, characterized in that: The underfill layer (4) is one of epoxy resin, styrene, silicone substrate filler material, or lead-free underfill material.
4. The novel Fan-out wafer-level 2.2D packaging structure according to claim 2, characterized in that: The molding layer (5) is one of epoxy resin, styrene resin, polyester resin, polytetrafluoroethylene, and polyimide.