Radio frequency amplifier capable of adjusting overshoot waveform

Abstract

The utility model discloses a radio frequency amplifier capable of adjusting an overshoot waveform. The radio frequency amplifier comprises a driving-stage amplifier, a final-stage amplifier, a first biasing circuit and a second biasing circuit which are sequentially arranged from front to back, and the driving-stage amplifier and the final-stage amplifier are respectively connected with the first biasing circuit and the second biasing circuit. When the bias voltage Vbias is controlled to be opened by the enable voltage Ven, an overshoot waveform is formed on a time domain waveform in a connection structure of the first bias circuit and the driving stage circuit; and after the bias voltage Vbias is controlled by Ven to be opened, a us-level slow climbing time is formed on a time domain waveform in a connection structure of the second bias circuit and the final-stage circuit. According to the utility model, through the first biasing circuit and the second biasing circuit, the time domain waveform is fast and stable in an extremely short time at the moment when the switch is turned on, the communication quality is effectively improved, and the high practicability is achieved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the technical field of gallium arsenide amplifier, and particularly relates to a radio frequency amplifier of adjustable overshoot waveform. BACKGROUND

[0002] In the modern wireless communication field, the gallium arsenide amplifier is very widely applied in the communication field, in the prior art, the gallium arsenide chip can be observed to slowly climb up in the first us level when being turned on, and the radio frequency time domain waveform slowly climbs up, and the time domain waveform cannot reach good communication quality before being stable. However, in the prior art of radio frequency communication, the opening time of radio frequency is an important and key system index, and in the traditional gallium arsenide switch circuit, the radio frequency time domain waveform is difficult to be stable in the ns level. In the prior art, with the increasing design demand of switch speed and communication quality, the above-mentioned defects of the traditional amplifier scheme need to be solved urgently. UTILITY MODEL CONTENT

[0003] The utility model aims at providing a radio frequency amplifier of adjustable overshoot waveform, which aims at solving the above-mentioned problems.

[0004] The utility model mainly realizes the following technical scheme:

[0005] A radio frequency amplifier of adjustable overshoot waveform comprises a driving stage amplifier, a final stage amplifier and first and second bias circuits arranged in sequence from front to back; the driving stage amplifier and the final stage amplifier are connected with the first and second bias circuits respectively;

[0006] The first bias circuit comprises inductors L1 and L2, transistors Q1-Q4 and resistors R1-R4; one end of the inductor L1 is connected with a working voltage VDD, and the other end is connected with the inductor L2 and the resistor R1 respectively; the inductor L2 is connected with the collector of the driving stage amplifier; the resistor R1 is connected with the base and collector of the transistor Q1 and the base of the transistor Q4 respectively; the emitter of the transistor Q1 is connected with the base and collector of the transistor Q2 and the transistor Q3 respectively; the emitters of the transistor Q2, the transistor Q3 and the transistor Q4 are connected with the resistor R3, the resistor R4 and the resistor R2 respectively; the resistor R3 and the resistor R4 are grounded respectively; the collector of the transistor Q4 is connected with a bias voltage Vbias; the resistor R2 and the inductor L2 correspond to the output current IB_driver and ICC_driver to the base and collector of the driving stage amplifier respectively;

[0007] The second bias circuit comprises an inductor L3, transistors Q5-Q7 and resistors R5 and R6; one end of the resistor R5 is connected with a bias voltage Vbias, and the other end is connected with the base and the collector of the transistor Q5 and the base of the transistor Q7 respectively; the emitter of the transistor Q5 is connected with the base and the collector of the transistor Q6 respectively, and the emitter of the transistor Q6 is grounded; the collector of the transistor Q7 is connected with the bias voltage Vbias, and the emitter is connected with the base of the final stage amplifier through the resistor R6 for outputting a current IB_final; one end of the inductor L3 is connected with a working voltage, and the other end outputs a current ICC_driver to the collector of the final stage amplifier.

[0008] In order to better realize the utility model, further, the first bias circuit further comprises capacitors C1-C5, the capacitor C1 is arranged between the inductor L1 and the working voltage VDD, the capacitor C2 is arranged between the inductor L1 and the resistor R1, the capacitor C3 is arranged between the bias voltage Vbias and the collector of the transistor Q4, the capacitor C4 is arranged between the base of the transistor Q4 and the collector of the transistor Q1, the capacitor C5 is arranged between the inductor L1 and the inductor L2, and the capacitors C1-C5 are grounded respectively.

[0009] In order to better realize the utility model, further, the second bias circuit further comprises capacitors C6-C8, the capacitor C6 is arranged between the bias voltage Vbias and the resistor R5, the capacitor C7 is arranged between the bias voltage Vbias and the transistor Q7, and the capacitor C8 is arranged between the base of the transistor Q7 and the collector of the transistor Q5, and the capacitors C6-C8 are grounded respectively.

[0010] In order to better realize the utility model, further, an inter-stage matching network is arranged between the driving stage amplifier and the final stage amplifier, an input matching network is arranged at the input end of the driving stage amplifier, and the first bias circuit is arranged between the input matching network and the driving stage amplifier.

[0011] In order to better realize the utility model, further, the driving stage amplifier and the final stage amplifier are an amplifier driving stage die array and an amplifier final stage die array respectively.

[0012] In order to better realize the utility model, further, a switch module is further included, and the switch module is connected with an enable voltage Ven, a working voltage VDD and a bias voltage Vbias respectively.

[0013] The utility model has the advantages of the following:

[0014] The utility model discloses a first bias circuit and second bias circuit have realized in the moment of switch opening, two different time domain waveform combinations are together after, in an extremely short time time domain waveform fast stabilization, effectively improved communication quality. The utility model discloses can be realized in switch opening, time domain waveform fast stabilization, or the over shoot waveform of opening. The utility model discloses can adjust the time domain waveform of amplifier opening, and the time domain waveform amplitude reaches the balance in the opening ns time of amplifier, thereby improved communication quality. For example, can be applied to the improvement amplifier dynamic EVM index in WiFi system communication, increase communication quality, in the field of road testing radar, increase ranging accuracy, have better practicality. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is the circuit schematic diagram of the utility model adjustable over shoot wave radio frequency amplifier;

[0016] Figure 2 It is the connection structure schematic diagram of switch module and enable voltage Ven, working voltage VDD and bias voltage Vbias;

[0017] Figure 3 It is the time domain waveform diagram of drive stage amplifier opening;

[0018] Figure 4 It is the time domain waveform diagram of final stage amplifier opening;

[0019] Figure 5 It is the time domain waveform diagram of the utility model adjustable over shoot wave radio frequency amplifier whole opening;

[0020] Figure 6 It is the structure schematic diagram of amplifier drive stage die array;

[0021] Figure 7 It is the structure schematic diagram of amplifier final stage die array. DETAILED DESCRIPTION

[0022] Embodiment 1:

[0023] A kind of adjustable over shoot wave radio frequency amplifier, as Figure 1 And Figure 2 As shown, including input matching network, drive stage amplifier, interstage matching network and final stage amplifier that are sequentially arranged from front to back, and first bias circuit and second bias circuit;The drive stage amplifier and final stage amplifier are connected with first bias circuit and second bias circuit respectively. Specifically, as Figure 6 And Figure 7 As shown, the drive stage amplifier and final stage amplifier are amplifier drive stage die array and amplifier final stage die array respectively.

[0024] The first bias circuit comprises inductors L1 and L2, transistors Q1-Q4, capacitors C1-C5 and resistors R1-R4; one end of the inductor L1 is connected with a working voltage VDD, and the other end is connected with the inductor L2 and the resistor R1 respectively; the inductor L2 is connected with a collector of a driving stage amplifier; the resistor R1 is connected with a base and a collector of the transistor Q1 and a base of the transistor Q4 respectively; the emitter of the transistor Q1 is connected with the base and the collector of the transistor Q2 and the transistor Q3 respectively; the emitters of the transistors Q2, Q3 and Q4 are connected with the resistors R3, R4 and R2 respectively; the resistors R3 and R4 are grounded respectively; the collector of the transistor Q4 is connected with a bias voltage Vbias; the resistors R2 and L2 correspond to output currents IB_driver and ICC_driver to the base and the collector of the driving stage amplifier respectively; the capacitors C1, C2, C3, C4 and C5 are arranged between the inductor L1 and the working voltage VDD, between the inductor L1 and the resistor R1, between the bias voltage Vbias and the collector of the transistor Q4, between the base of the transistor Q4 and the collector of the transistor Q1 and between the inductors L1 and L2 respectively, and the capacitors C1-C5 are grounded respectively.

[0025] The second bias circuit comprises an inductor L3, transistors Q5-Q7, capacitors C6-C8 and resistors R5 and R6; one end of the resistor R5 is connected with the bias voltage Vbias, and the other end is connected with the base and the collector of the transistor Q5 and the base of the transistor Q7 respectively; the emitter of the transistor Q5 is connected with the base and the collector of the transistor Q6 respectively, and the emitter of the transistor Q6 is grounded; the collector of the transistor Q7 is connected with the bias voltage Vbias, and the emitter is connected with the base of a final stage amplifier through the resistor R6 for outputting a current IB_final; one end of the inductor L3 is connected with a working voltage, and the other end outputs a current ICC_driver to the collector of the final stage amplifier; the capacitors C6, C7 and C8 are arranged between the bias voltage Vbias and the resistor R5, between the bias voltage Vbias and the transistor Q7 and between the base of the transistor Q7 and the collector of the transistor Q5 respectively, and the capacitors C6-C8 are grounded respectively.

[0026] Preferably, a switch module is further included, and the switch module is connected with an enable voltage Ven, a working voltage VDD and a bias voltage Vbias respectively. The switch module is a prior art, and thus is not described herein.

[0027] As Figure 2As shown, when the bias voltage Vbias is turned on by the enable voltage Ven, in the connection structure of the first bias circuit and the driver stage circuit, after the switch is turned on, the base current IB_driver of the driver stage amplifier chip increases sharply, and the collector current ICC_driver also increases sharply. At this time, the load at the output terminal of inductor L1 decreases. Under this state, the voltage across the inductor cannot be compensated for the sudden change, and the voltage at the output terminal of L1 decreases. In the current source bias structure composed of transistors Q1, Q2, Q3, and Q4, the supply voltage decreases, the bias point of the driver amplifier decreases, and the gain of the driver amplifier decreases. Figure 3 As shown, an overshoot waveform is formed on the time-domain waveform.

[0028] like Figure 2 As shown, when the bias voltage Vbias is turned on by Ven, in the connection structure of the second bias circuit and the final stage circuit, after the switch is turned on, the base current IB_final of the driver stage amplifier chip increases, and the collector current ICC_final increases. When the amplifier is turned on, as shown... Figure 4 As shown, there is a slow ramp-up time at the microsecond level.

[0029] like Figure 5 As shown, from the overall perspective of this utility model, at the instant the switch is turned on, after the two different time-domain waveforms are combined, the amplifier chip module can quickly stabilize the time-domain waveform in a very short time (within 200ns), which is an order of magnitude higher than the traditional design scheme (the traditional scheme is at the microsecond level), and has good practicality.

[0030] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present utility model shall fall within the protection scope of the present utility model.

Claims

1. A radio frequency amplifier with adjustable overshoot waveform, characterized by, The bias circuit comprises a driving stage amplifier, a final stage amplifier and a first bias circuit and a second bias circuit arranged in sequence from front to back; the driving stage amplifier and the final stage amplifier are connected with the first bias circuit and the second bias circuit respectively; The first bias circuit comprises inductors L1 and L2, transistors Q1-Q4 and resistors R1-R4; one end of the inductor L1 is connected with a working voltage VDD, and the other end is connected with the inductor L2 and the resistor R1 respectively; the inductor L2 is connected with a collector of the driving stage amplifier; the resistor R1 is connected with a base, a collector of the transistor Q1 and a base of the transistor Q4 respectively; the emitter of the transistor Q1 is connected with the base and the collector of the transistor Q2 and the transistor Q3 respectively; the emitters of the transistor Q2, the transistor Q3 and the transistor Q4 are connected with the resistor R3, the resistor R4 and the resistor R2 respectively; the resistor R3 and the resistor R4 are grounded respectively; the collector of the transistor Q4 is connected with a bias voltage Vbias; the resistor R2 and the inductor L2 correspond to an output current IB_driver and ICC_driver to the base and the collector of the driving stage amplifier respectively; The second bias circuit comprises an inductor L3, transistors Q5-Q7 and resistors R5 and R6; one end of the resistor R5 is connected with the bias voltage Vbias, and the other end is connected with the base and the collector of the transistor Q5 and the base of the transistor Q7 respectively; the emitter of the transistor Q5 is connected with the base and the collector of the transistor Q6 respectively; the emitter of the transistor Q6 is grounded; the collector of the transistor Q7 is connected with the bias voltage Vbias, and the emitter is connected with the base of the final stage amplifier through the resistor R6 for outputting a current IB_final; one end of the inductor L3 is connected with a working voltage, and the other end outputs a current ICC_driver to the collector of the final stage amplifier.

2. The RF amplifier of claim 1, wherein, The first bias circuit further comprises capacitors C1-C5, and the capacitors C1, C2, C3, C4 and C5 are respectively arranged between the inductor L1 and the working voltage VDD, between the inductor L1 and the resistor R1, between the bias voltage Vbias and the collector of the transistor Q4, between the base of the transistor Q4 and the collector of the transistor Q1 and between the inductor L1 and the inductor L2, and the capacitors C1-C5 are grounded respectively.

3. The RF amplifier of claim 1, wherein, The second bias circuit further comprises capacitors C6-C8, and the capacitors C6, C7 and C8 are respectively arranged between the bias voltage Vbias and the resistor R5, between the bias voltage Vbias and the transistor Q7 and between the base of the transistor Q7 and the collector of the transistor Q5, and the capacitors C6-C8 are grounded respectively.

4. A radio frequency amplifier of adjustable overshoot waveform according to any one of claims 1 to 3, characterised in that, An inter-stage matching network is arranged between the driving stage amplifier and the final stage amplifier, an input matching network is arranged at an input end of the driving stage amplifier, and the first bias circuit is arranged between the input matching network and the driving stage amplifier.

5. The RF amplifier of claim 4, wherein, The driving stage amplifier and the final stage amplifier are an amplifier driving stage die array and an amplifier final stage die array respectively.

6. The RF amplifier of claim 1, wherein, The switch module is connected with the enable voltage Ven, the working voltage VDD and the bias voltage Vbias respectively. The switch module is connected with the enable voltage Ven, the working voltage VDD and the bias voltage Vbias respectively.

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