Chip packaging structure
By using a three-dimensional stacked structure and through-silicon via (TSV) technology, the problems of insufficient integration and data interaction capabilities in the packaging structure have been solved, enabling high-bandwidth data transmission and logic operation, thereby improving packaging performance and production efficiency.
Patent Information
- Application Number
- CN202520305600.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2035-02-25
AI Technical Summary
Existing packaging structures are limited in terms of integration and system performance, have insufficient data interaction capabilities, and suffer from high processing costs, high power consumption, fixed thickness, and poor heat dissipation.
It adopts a three-dimensional stacked structure design, including memory chips and logic chips stacked on top of each other. It utilizes through silicon vias, redistribution layers and metal bumps to increase communication channels and optimize circuit structure. The logic chips are protected by an intermediary chip, enabling high-bandwidth data transmission and logic operation.
It improves packaging integration and system performance, enhances data interaction capabilities, reduces the impact of production errors, and improves product yield and overall work efficiency.
Smart Images
Figure CN223912796U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a memory chip technical field, concretely relates to a chip packaging structure. BACKGROUND
[0002] HBM is the abbreviation of High Bandwidth Memory, it is a kind of high-performance DRAM based on 3D stacking process, it is through vertical stacking multilayer DRAM chip, and through the technology of silicon through hole (TSV) and micro bump (uBump) connection technology, forms high-density storage stack, to greatly improve the overall storage capacity and bandwidth.
[0003] In recent years, with the growth of demand for smaller electronic devices, more innovative packaging technologies are needed for semiconductor wafers, among which three-dimensional semiconductor wafer packaging technology has become an effective choice for further reducing the physical size of semiconductor wafer packaging.
[0004] The packaging structure formed under the current technical conditions is either limited by the packaging stacking technology and cannot further improve the integration and system performance, or is limited by the advanced wafer processing technology, which has high cost and high integration difficulty.
[0005] At the same time, the data interaction capability of the prior art is low, and there are problems of high power consumption, fixed thickness and poor heat dissipation. UTILITY MODEL CONTENT
[0006] The utility model aims at the above-mentioned problems and deficiencies, provides a kind of chip packaging structure, improves the overall work efficiency.
[0007] The technical problem solved by the utility model is:
[0008] (1) how to further improve the integration and system performance of packaging stacking technology;
[0009] (2) how to reduce processing cost and improve the data interaction capability between different chips.
[0010] The purpose of the utility model can be realized by the following technical scheme: a kind of chip packaging structure, including mutually stacked storage wafer and logic wafer, logic wafer is at least provided with two, and logic wafer is arranged in the upper and lower sides of storage wafer, each storage wafer and each logic wafer are kept electrical connection between each other, and the top of the logic wafer located in top layer is equipped with intermediate wafer.
[0011] Preferably, the intermediate wafer includes a sacrificial layer, and a conductor post is provided in the sacrificial layer.
[0012] Preferably, the through silicon vias are regularly distributed in a fixed array in the memory wafer and the logic wafer, and the through silicon vias of the memory wafer and the logic wafer correspond one by one and are in communication.
[0013] Preferably, integrated circuits are arranged on one side surface of the memory wafer and the logic wafer, and the active surfaces are formed, and redistribution layers are formed on the other side surface of the memory wafer and the logic wafer.
[0014] Preferably, the memory wafer is provided with a plurality of memory wafers, and at least three memory wafers are provided.
[0015] Preferably, the plurality of conductor columns are provided, the conductor columns are metal, and the conductor columns are used for data communication or power supply.
[0016] Preferably, the plurality of conductor columns are regularly distributed in a fixed array, and the distribution of the conductor columns is consistent with the distribution of the interfaces on the surface of the redistribution layer.
[0017] Preferably, the connection bumps are arranged on the interfaces of the outer surface of the redistribution layer and the two side end surfaces of the conductor columns, the mutual communication of the plurality of memory wafers, the mutual communication of the plurality of logic wafers, the mutual communication of the memory wafer and the logic wafer, and the mutual communication of the logic wafer and the external environment through the intermediate wafer are connected through the connection bumps of the corresponding interfaces.
[0018] Preferably, the memory wafer, the logic wafer and the intermediate wafer are collectively molded with a plastic shell.
[0019] The beneficial effects of the utility model are as follows:
[0020] (1) During operation, the two-dimensional single-layer distribution and structure of the existing chip are expanded to a three-dimensional stacked distribution and structure, thereby expanding the existing single chip into a storage part and a logic control part according to the functional division, so that different parts can be provided with corresponding processes and circuit structures according to the functional division and actual needs, in the stacked structure, the technology of through silicon vias, RDL, UBM and metal bumps is used, thereby increasing the number of communication channels and the capacity of the communication process, and the vertical connection greatly eliminates the communication distance, so that the chip density can be very high, the delay is very small, high-bandwidth data transmission is realized, the storage density is improved through the multi-layer storage wafer, the overall size is compressed, the communication connection distance is eliminated, and different interfaces are adapted by the redistribution layer to ensure the stability and efficiency of the connection.
[0021] (2) Working, through the division of the two sides of the logic chip, both can make the chip has the ability of double-sided communication, interaction, conductive transmission, and make the chip can communicate and connect each other after the scale setting, produce a distributed structure, can carry out more complex logic operation, and the logic chip on both sides of the chip itself after accessing the circuit can also interact and communicate with each other, thereby further improving the logic operation ability and data transmission efficiency, through the mutual communication of silicon channel, the storage chip and the logic chip can further expand the data communication ability, thereby further improving the ability of data interaction and logic operation;
[0022] (3) Working, through the mediation chip to protect the logic chip, so that it can participate in the combination packaging of other chips, replace the logic chip to participate in the overall size adjustment process of the chip, such as through grinding to realize the process of multi-chip coplanar, and can adjust the channel distribution when the chip communicates with the outside world, ensure the connection effect and high bandwidth of the channel, adjust the communication connection points of the storage chip and the logic chip through the re-wiring layer, avoid the phenomenon that the silicon channel of the storage chip and the logic chip cannot be aligned, ensure that the production process error will not cause the obstacle of unable to connect, improve the product yield of the storage chip and the logic chip, at the same time, through the secondary adjustment of the re-wiring layer, the chip can further adapt to different interface distribution, standardize the distribution of communication channel, keep the stability and efficiency of the connection process, facilitate the alignment effect in the production and assembly process, and reduce the adverse effects of production errors. BRIEF DESCRIPTION OF DRAWINGS
[0023] In order to facilitate the understanding of those skilled in the art, the present application will be further described below with reference to the drawings.
[0024] Figure 1 It is the overall structure schematic view of the present application.
[0025] Figure 2 It is Figure 1 It is the front view of A-A section.
[0026] Figure 3 It is Figure 2 It is the enlarged schematic view of B area.
[0027] Figure 4 It is the front view of the storage chip and the logic chip of the present application.
[0028] In the figure: 101, storage chip; 102, logic chip; 103, mediation chip; 104, connection bump; 105, plastic package shell; 201, sacrifice layer; 202, conductor column; 301, silicon channel; 302, re-wiring layer. DETAILED DESCRIPTION
[0029] In order to further illustrate the technical means and effects adopted by the utility model to achieve the predetermined utility model purposes, the specific implementation, structure, features and effects according to the utility model are described in detail as follows in combination with the drawings and preferred embodiments.
[0030] Please refer to Figures 1-4 As shown in FIG. 1, a chip packaging structure includes mutually stacked storage wafers 101 and logic wafers 102, the logic wafers 102 are at least two, and the logic wafers 102 are arranged on the upper and lower sides of the storage wafers 101, each storage wafer 101 and each logic wafer 102 are electrically connected to each other, and the top of the logic wafer 102 on the top layer is provided with an intermediate wafer 103.
[0031] In the working process of the embodiment, the two-dimensional single-layer distribution and structure of the existing chip are expanded to a three-dimensional stacked distribution and structure, thereby expanding the existing single chip into a storage part and a logic control part according to the functional division, so that different parts can be provided with corresponding processes and circuit structures according to the functional division and actual needs, in the stacked structure, the technology of through silicon via, RDL, UBM and metal bump is used, which not only increases the number of communication channels, but also increases the capacity of the communication process, and the vertical connection greatly eliminates the communication distance, so that the chip density can be very high, the delay is very small, and high-bandwidth data transmission is realized.
[0032] In the working process, the division and cooperation of the logic wafers 102 on both sides not only enable the chip to have the ability of bidirectional communication, interaction and conductive transmission, but also enable the chip to communicate and connect with each other after being set in scale, thereby generating a distributed structure, being capable of performing more complex logic operation, and the logic wafers 102 on both sides of the chip itself can also interact and communicate with each other after being connected to the circuit, thereby further improving the logic operation ability and data transmission efficiency of the chip itself.
[0033] The intermediate wafer 103 includes a sacrifice layer 201, and a conductor column 202 is arranged in the sacrifice layer 201.
[0034] In the working process of the embodiment, the intermediate wafer 103 can protect the logic wafers 102, so that the chip of the embodiment can participate in the combined packaging of other chips, replace the logic wafers 102 to participate in the overall size adjustment process of the chip, for example, realize the process of multiple chips being coplanar through grinding, and can secondarily adjust the channel distribution when the chip is connected to the outside, thereby ensuring the communication effect and high bandwidth of the channel, and improving the overall work efficiency and yield.
[0035] In addition, the intermediate wafer 103 can also not be arranged, and the logic wafers 102 can be directly electrically connected to other circuit structures.
[0036] The intermediate wafer 103 can be arranged, and the corresponding redistribution layer 302 is arranged on the surface of the intermediate wafer 103, so as to meet the design requirements of the interface position arrangement when the chip is assembled into a new chip set.
[0037] The one side surface of the storage wafer 101 and the logic wafer 102 is respectively provided with an integrated circuit and forms an active surface, and the other side surface of the storage wafer 101 and the logic wafer 102 is respectively provided with a redistribution layer 302;
[0038] The storage wafer 101 and the logic wafer 102 are respectively provided with a through silicon via 301 arranged in a fixed array in a through silicon via process, and the through silicon via 301 of the storage wafer 101 and the logic wafer 102 is one-to-one corresponding and interconnected;
[0039] The embodiment is shown in the accompanying drawings Figure 2 and Figure 4 As shown in the drawings, the active surface of the storage wafer 101 and the logic wafer 102 is arranged on the lower surface, and the redistribution layer 302 is arranged on the upper surface, and the information exchange is facilitated through the redistribution layer 302, and the data communication capability of the storage wafer 101 and the logic wafer 102 is further expanded through the interconnected through silicon via 301, so as to further improve the data interaction and logic operation capability.
[0040] The communication connection points of the storage wafer 101 and the logic wafer 102 are secondarily adjusted through the redistribution layer 302, so as to avoid the phenomenon that the through silicon via 301 of the storage wafer 101 and the logic wafer 102 cannot be aligned, to ensure that the error in the production process will not cause the obstacle of the corresponding connection, to improve the product yield of the storage wafer 101 and the logic wafer 102, and to further adapt the chip to different interface distributions through the secondary adjustment of the redistribution layer 302, to improve the overall application range.
[0041] The storage wafer 101 is provided with a plurality of conductor columns 202, and at least three conductor columns 202, the conductor column 202 is metal and has the functions of data communication or potential power supply, the conductor column 202 is arranged in a fixed array, and the distribution of the conductor column 202 is consistent with the interface distribution on the surface of the redistribution layer 302 and one-to-one corresponding;
[0042] The conductor column 202 of the embodiment is a copper column;
[0043] Through the multi-layer arrangement of the storage wafer 101, the storage density is improved, the overall size is compressed, the communication connection distance is eliminated, and the redistribution layer 302 is matched with different interfaces to ensure the stability and efficiency of the connection.
[0044] The connecting bump 104 is welded through the corresponding interface to realize the communication among the storage chips 101, the communication among the logic chips 102, the communication between the storage chip 101 and the logic chip 102 and the communication between the logic chip 102 and the outside through the intermediate chip 103.
[0045] The welding of the connecting bump 104 is not limited to micro-bump and copper-copper solid-state welding.
[0046] The welding of the connecting bump 104 is not limited to micro-bump and copper-copper solid-state welding.
[0047] The storage chip 101, the logic chip 102 and the intermediate chip 103 are collectively molded with the molded shell 105.
[0048] The chip periphery is supported and protected by the molded shell 105.
[0049] The two-dimensional single-layer distribution and structure of the existing chip are expanded to three-dimensional stacking distribution and structure, so that the existing single chip is expanded to a storage part and a logic control part according to the function division, so that different parts can set corresponding processes and circuit structures according to the function division and actual demand, in the stacking structure, the through silicon via, RDL, UBM and metal bump technology are used, not only the number of communication channels is increased, but also the capacity of the communication process is increased, and the vertical connection greatly eliminates the communication distance, so that the chip density can be very high, and the delay is very small, realizing high-bandwidth data transmission, the storage density is improved by the multi-layer storage chip 101, the overall size is compressed, the communication connection distance is eliminated, and the different interfaces are adapted by the redistribution layer 302, so that the stability and efficiency of the connection are ensured.
[0050] Through the division and cooperation of the two logic chips 102, the chip can have the ability of double-sided communication, interaction and conductive transmission, and the chip can communicate and connect with each other after being set in scale, a distributed structure is generated, more complex logic operation can be performed, and the two logic chips 102 on both sides of the chip can also interact and communicate after being connected to the circuit, so as to further improve the logic operation ability and data transmission efficiency of the chip, the data communication ability of the storage chip 101 and the logic chip 102 is further expanded through the mutual communication of the through silicon channel 301, so as to further improve the data interaction and logic operation ability of the chip.
[0051] The logic wafer 102 is protected by the intermediary wafer 103, so that the logic wafer 102 can participate in the combined packaging of other chips, replace the logic wafer 102 to participate in the overall size adjustment process of the chip, for example, through grinding to realize the process of multi-chip coplanarization, and can secondarily adjust the channel distribution when the chip is connected with the outside world, ensure the communication effect and high bandwidth of the channel, through the re-wiring layer 302, the communication connection points of the storage wafer 101 and the logic wafer 102 are secondarily adjusted, so that the phenomenon that the silicon channel 301 of the storage wafer 101 and the logic wafer 102 cannot be aligned is avoided, the error in the production process is ensured to not cause the obstacle of non-corresponding connection, the product yield of the storage wafer 101 and the logic wafer 102 is improved, meanwhile, through the secondary adjustment of the re-wiring layer 302, the chip can be further adapted to different interface distribution, the distribution of the communication channel is standardized, the stability and efficiency of the communication process are maintained, the alignment effect in the production and assembly process is facilitated, and the adverse effects caused by the production error are reduced.
[0052] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as the above preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes, as long as the changes do not deviate from the technical scheme of the present application. Any indirect modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still belong to the scope of the technical scheme of the present application.
Claims
1. A chip package structure, characterized by, It comprises mutually stacked memory wafers (101) and logic wafers (102), the logic wafers (102) are provided with at least two, and the logic wafers (102) are arranged on the upper and lower sides of the memory wafers (101), each memory wafer (101) and each logic wafer (102) are electrically connected to each other, and the top of the top logic wafer (102) is provided with an intermediate wafer (103).
2. The chip package structure of claim 1, wherein The intermediate wafer (103) comprises a sacrificial layer (201), and a conductor column (202) is arranged in the sacrificial layer (201).
3. The chip package structure of claim 1, wherein The memory wafers (101) and the logic wafers (102) are provided with through-silicon vias (301) arranged in a fixed array by a through-silicon via process, and the through-silicon vias (301) of the memory wafers (101) and the logic wafers (102) correspond one by one and are in communication.
4. The chip package structure of claim 2, wherein, The memory wafers (101) and the logic wafers (102) are respectively provided with integrated circuits and active surfaces on one side surface.
5. The chip package structure of claim 1, wherein, The memory wafers (101) are provided with several, and at least three.
6. The chip package structure of claim 2, wherein The conductor column (202) is provided with several, the conductor column (202) is metal and has the functions of data communication or potential power supply.
7. The chip package structure of claim 4, wherein The conductor column (202) is arranged in a fixed array.
8. The chip package structure of claim 4, wherein, The distribution of the conductor column (202) is consistent with the interface distribution of the surface of the redistribution layer (302) and corresponds one by one.
9. The chip package structure of claim 7, wherein, The outer surface of the redistribution layer (302), the active surface and the two side surfaces of the conductor column (202) are respectively provided with connecting bumps (104) for connection, the mutual connection of the memory wafers (101), the mutual connection of the logic wafers (102), the mutual connection of the memory wafers (101) and the logic wafers (102), and the mutual connection of the logic wafers (102) and the outside through the intermediate wafer (103) are all connected and welded through the connecting bumps (104) of the corresponding interfaces.
10. The chip package structure of claim 1, wherein The memory wafers (101), the logic wafers (102) and the intermediate wafer (103) are collectively plastic encapsulated by a plastic encapsulation shell (105).