Pixel matrix and integrated device

Abstract

Various embodiments of the utility model relate to a pixel matrix. The pixel matrix comprises a substrate comprising a first side and a second side opposite to the first side; a plurality of light detectors in the substrate, the plurality of light detectors being symmetrically arranged around a central axis between the plurality of light detectors, the central axis being perpendicular to the first side and the second side; a first doped region located at a central axis between the plurality of light detectors and located at a first side of the substrate; a front-side deep trench isolation (DTI) structure located on the first side of the substrate and directly extending between the plurality of light detectors; and a backside DTI structure located on the second side of the substrate and separating the front side DTI structure from the center axis.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a pixel matrix and an integrated device. BACKGROUND

[0002] Many modern electronic devices include image sensors. An image sensor has photodetectors, transfer gates, and floating diffusion nodes. The transfer gates are configured to form a conductive path between the photodetectors and the floating diffusion nodes during operation, such that charges in the photodetectors are transferred to image processing circuitry through the floating nodes. The photodetectors are typically separated from each other by deep trench isolation (DTI) structures. SUMMARY

[0003] An embodiment of the present application provides a pixel matrix. The pixel matrix includes a substrate, the substrate including a first side and a second side opposite the first side. The pixel matrix also includes a plurality of photodetectors in the substrate, the plurality of photodetectors being symmetrically disposed about a central axis between the plurality of photodetectors, wherein the central axis is perpendicular to the first side and the second side. The pixel matrix also includes a first doped region at the central axis between the plurality of photodetectors and at the first side of the substrate. The pixel matrix also includes a front-side deep trench isolation (DTI) structure at the first side of the substrate and directly extending between the photodetectors of the plurality of photodetectors. The pixel matrix also includes a back-side DTI structure at the second side of the substrate and separating the front-side DTI structure from the central axis.

[0004] Another aspect of the present application provides an integrated device. The integrated device includes a substrate, the substrate including a first side and a second side. The integrated device also includes a pixel region in the substrate, the pixel region including a first corner, a second corner, a third corner, and a fourth corner when viewed from a top view. The integrated device also includes a first photodetector in the pixel region of the substrate. The integrated device also includes a transistor on the first side of the substrate. The integrated device also includes a first doped region having a first conductivity type, the first doped region on the first side of the substrate, on a first side of the first photodetector, and overlapping the first corner of the pixel region. The integrated device also includes a second doped region having a second conductivity type, the second doped region on the first side of the substrate, on a second side of the first photodetector opposite the first side of the first photodetector, and overlapping a second corner of the pixel region opposite the first corner. The integrated device also includes a backside deep trench isolation (DTI) structure on the second side of the substrate and directly below the first doped region and the second doped region, the backside DTI structure including a first segment and a second segment intersecting at the first corner of the pixel region and a third segment and a fourth segment intersecting at the second corner of the pixel region. The integrated device also includes a frontside DTI structure on the first side of the substrate, the frontside DTI structure including a fifth segment extending from the first segment of the backside DTI structure, a sixth segment extending from the second segment of the backside DTI structure, a seventh segment extending from the third segment of the backside DTI structure, and an eighth segment extending from the fourth segment of the backside DTI structure, wherein the fifth segment and the seventh segment intersect at the third corner of the pixel region and the sixth segment and the eighth segment intersect at the fourth corner of the pixel region.

[0005] A method of forming an integrated device is provided. The method includes receiving a substrate, the substrate including a first side, a second side, and a pixel region, the pixel region having a first corner, a second corner, a third corner, and a fourth corner when viewed from a top view. The method also includes etching a first opening in the first side of the substrate, the first opening including a first cross-shaped opening and a second cross-shaped opening, the first cross-shaped opening outlining a profile of the third corner of the pixel region, and the second cross-shaped opening outlining a profile of the fourth corner of the pixel region. The method also includes forming a front side deep trench isolation (DTI) structure within the first opening. The method also includes forming a first doped region having a first conductivity type at the first corner of the pixel region. The method also includes forming a second doped region having a second conductivity type at the second corner of the pixel region. The method also includes forming a pass transistor in the pixel region in the first side of the substrate. The method also includes etching a second opening in the second side of the substrate, the second opening including a third cross-shaped opening and a fourth cross-shaped opening, the third cross-shaped opening being located below the first corner of the pixel region, and the fourth cross-shaped opening being located below the second corner of the pixel region. The method also includes forming a back side DTI structure within the second opening, wherein the back side DTI structure and the front side DTI structure form a continuous ring around the pixel region, and the back side DTI structure separates the front side DTI structure from the first corner and the second corner of the pixel region.

[0006] In order to make the above features and advantages of the present application more obvious and easy to understand, the following embodiments are described in detail below, and the detailed description is made below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1A , FIG. 1B , FIG. 1C and FIG. 1D show top views, cross-sectional views, and circuit diagrams of some embodiments of front side DTI structures and back side DTI structures of a photodetector isolating a pixel matrix.

[0008] FIG. 2A , FIG. 2B , FIG. 2C and FIG. 2D show top views and cross-sectional views of alternative embodiments of front side DTI structures and back side DTI structures of a photodetector isolating a pixel matrix, wherein the back side DTI structure is separated from the first doped region.

[0009] FIG. 3A , FIG. 3B , FIG. 3C and FIG. 3D show top views and cross-sectional views of alternative embodiments of front side DTI structures and back side DTI structures of a photodetector isolating a pixel matrix.

[0010] FIG. 4A through FIG. 17BA series of top and cross-sectional views showing some embodiments of a method of forming front-side and back-side DTI structures that isolate the photodetectors of a pixel matrix.

[0011] FIG. 18 A flowchart showing some embodiments of a method of forming front-side and back-side DTI structures that isolate the photodetectors of a pixel matrix. DETAILED DESCRIPTION

[0012] The present disclosure provides many different embodiments or examples of different features that can be implemented in various combinations to form different embodiments of the present disclosure. The following description is presented in terms of specific embodiments, which should not be construed as limiting. For example, the description below can refer to a first component being formed on or over a second component. This can include embodiments where the first component is formed directly on or over the second component, and also embodiments where additional components are formed between the first component and the second component, such that the first component is not formed directly on or over the second component. Additionally, the present disclosure can refer to a number of instances of reference numerals and / or letters in various examples. Such repetition of reference numerals and / or letters is for the purpose of simplicity and clarity and does not itself dictate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] The DTI structures include insulating films and fill layers. The DTI structures extend between and isolate different semiconductor devices or components in a substrate from one another, thereby reducing the amount of interference that can occur between the semiconductor devices. In a pixel matrix, some embodiments use the DTI structures to surround and isolate the pixels of the pixel matrix, such that separate photodetectors, floating diffusion nodes, and body contacts exist within the pixels of the pixel matrix. Forming the DTI structures includes high-temperature processes, thereby repairing defects caused by etching the substrate.

[0015] As digital technology advances, more complex integrated devices are needed, and there is a growing demand for higher resolution pixel matrices that occupy less space. To reduce the footprint of each pixel (e.g., the space used by components on a semiconductor device), some embodiments share a floating diffusion node and a body contact among multiple pixels in a pixel matrix. To extend to multiple pixels in the pixel matrix, the floating diffusion node and the body contact are formed at the junctions between the multiple pixels, thereby occupying the space of the DTI structures at these intersections. While this reduces the footprint of the pixel matrix, this change removes a portion of the DTI structures that isolate the pixels. Reducing the degree of isolation between the pixels can again cause the possibility of interference between the pixels in the pixel matrix.

[0016] Furthermore, the thermal budget available for forming the DTI structure variants is limited by the active components and doped regions of the integrated device. If the DTI structure is formed after the doped regions, the high temperature processes performed during formation to repair defects in the substrate will not be within the thermal budget. Introducing defects in the substrate can increase the likelihood of dark current and leakage current in the integrated device, thereby reducing the performance of the pixel matrix. Therefore, there is a need for a device that maintains the reduced footprint provided by sharing a floating diffusion node, isolates the pixels sharing the floating diffusion node, and also reduces defects in the substrate resulting from forming the DTI structure.

[0017] The present disclosure provides a pixel matrix including a front-side DTI structure and a back-side DTI structure (or "dual" DTI structure), and the front-side and back-side DTI structures surround the pixels of the pixel matrix. The front-side DTI structure extends completely through the substrate, extending around most of the periphery of the pixels. The back-side DTI structure extends partially through the substrate just below the floating diffusion region and the body contact region, thereby further isolating the pixels without interfering with the functionality of the pixel components. Additionally, the front-side DTI structure is formed before the body contact region, the floating diffusion node, and the photodetector, and a high temperature process is used to repair substrate defects around the front-side DTI structure. The back-side DTI structure is formed after the body contact region, the floating diffusion node, and the photodetector, and has a lower thermal budget. Limiting the back-side DTI structure to the area below the floating diffusion region and the body contact region mitigates the damage to the substrate caused by forming the back-side DTI structure.

[0018] FIG. 1A 、 FIG. 1B 、 FIG. 1C and FIG. 1DTop view 100a, sectional view 100b, 100c and circuit diagram of some embodiments of the front DTI structure and rear DTI structure of the isolated pixel matrix photodetector are shown. FIG. 1B The sectional view 100b is along FIG. 1A The view of line A-A'. FIG. 1C The sectional view 100c is along FIG. 1A The view of line B-B'.

[0019] like FIG. 1A As shown in top view 100a, a front DTI structure 104 and a rear DTI structure 106 are disposed within a substrate 102. The front DTI structure 104 and the rear DTI structure 106 form a continuous loop within the substrate 102 surrounding a pixel region 108. The pixel region 108 includes one photodetector from a plurality of photodetectors 114 and one gate stack from a plurality of gate stacks 116. The pixel region 108 is arranged as a plurality of rows 109 extending along a first direction 101 and a plurality of columns 107 extending along a second direction 103 perpendicular to the first direction 101. The front DTI structure 104 and the rear DTI structure 106 together form a grid extending between the plurality of rows 109 and the plurality of columns 107. The rear DTI structure 106 is positioned at alternating intersections of the grid, forming a checkered pattern spanning the grid intersections.

[0020] Photodetector 114 includes a doped region of a first conductivity type (e.g., negative doping type) and a surrounding substrate 102. A plurality of gate stacks 116, together with the first doped region 110 and photodetector 114, are configured to act as transfer transistors 115. Transfer transistors 115 control the formation of channels between the plurality of photodetectors 114 and the first doped region 110. The first doped region 110 extends into a plurality of pixel regions 108 and is used by the pixel regions 108 to transfer charge from the plurality of photodetectors 114 within the pixel regions 108 to an interconnect structure (see [link to interconnect structure]). FIG. 1B (119). The first doped region 110 has a first conductivity type (e.g., negative conductivity type). The second doped region 112 extends into the plurality of pixel regions 108, thereby biasing the substrate 102 within the plurality of pixel regions 108. The second doped region 112 has a second conductivity type (e.g., positive conductivity type) and is also referred to as a bulk contact region.

[0021] To extend into the plurality of pixel regions 108, the first doped region 110 and the second doped region 112 are located between the plurality of pixel regions 108. The first doped region 110 and the second doped region 112 cannot be formed in the front DTI structure 104 surrounding most of the periphery of the pixel regions 108 because the front DTI structure 104 has a capping layer 123 that is an insulating material or includes an insulating material. The insulating material would impede the function of the first doped region 110 and the second doped region 112. Therefore, the front DTI structure 104 does not continuously surround the pixel regions 108. Gaps exist in the front DTI structure 104, where the first doped region 110 and the second doped region 112 are formed. These gaps are located at opposite corners of the front DTI structure, such that the first doped region 110 and the second doped region 112 have maximum distance between each other while still being coupled to the pixel regions 108. The rear DTI structure 106 extends directly below the first doped region 110 and the second doped region 112. The rear DTI structure 106 and the front DTI structure 104 form a continuous loop around the pixel region 108 without interfering with the intended function of the first doped region 110 and the second doped region 112.

[0022] In some embodiments, pixel region 108 surrounds the central axis of the first doped region extending through the first doped region 110 (see [link]). FIG. 1B The second doped region 113 is symmetrically arranged. Additionally, the second doped region 112 is symmetrically arranged around the central axis (see [reference]). FIG. 1B 113). Central axis (see 113). FIG. 1B 113) extends on a third direction 105 perpendicular to the first direction 101 and the second direction 103, and extends through the midpoint between pixel areas 108. The rear DTI structure 106 connects the front DTI structure 104 and the central axis (see...). FIG. 1B (113) are separated.

[0023] like FIG. 1B As shown in cross-sectional view 100b, the front-side DTI structure 104 is located on the first side 102a of the substrate and includes a first filler layer 120, a first insulating liner 122, and a capping layer 123. The capping layer 123 and the first insulating liner 122 are or include one or more insulating materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4), etc. The insulating material reduces the amount of possible interference between multiple pixels.

[0024] The rear-side DTI structure 106 is located on the second side 102b of the substrate 102 and includes a second fill layer 124 and a second insulating substrate 126. The second insulating substrate 126 contacts the first insulating substrate 122 of the front-side DTI structure 104. In some embodiments, the rear-side DTI structure 106 extends into the first doped region 110. In other embodiments, the rear-side DTI structure 106 and the first doped region 110 are spaced apart by the substrate 102. A floating diffusion region 111 is located within the first doped region 110. The conductivity of the first conductivity type of the floating diffusion region 111 is higher than that of the first doped region 110. The first doped region 110 may also be referred to as a lightly doped region. In some embodiments, the floating diffusion region 111 has a conductivity greater than 10. 18 cm -3 The doping concentration is less than 10, while the first doped region 110 has a doping concentration of less than 10. 18 cm -3 The doping concentration is specified. The floating diffusion region 111 is configured to transfer the charge generated by the plurality of photodetectors 114 to the interconnect structure 119. The central axis 113 extends through the first doped region 110 and the rear DTI structure 106.

[0025] Multiple contacts 118 connect the first doped region 110 and the second doped region (see...) FIG. 1A 112) is coupled to interconnect structure 119. The interconnect structure includes one or more metal line levels 130 and one or more via levels 131, which are configured to transfer received charge to image processing circuitry (see details). FIG. 1D Interlayer dielectric 128 surrounds interconnect structure 119. In some embodiments, etch stop layer 129 spaces one or more metal line layers 130 from one or more active components (e.g., transfer transistor 115).

[0026] like FIG. 1C As shown in cross-sectional view 100c, a plurality of gate stacks 116 cover the substrate 102. The plurality of gate stacks 116 include a plurality of gate dielectrics 134 and a plurality of gates 132. In some embodiments, the plurality of gate dielectrics 134 are situated in a single layer extending between the plurality of gate stacks of the plurality of gate stacks 116. In other embodiments, the plurality of gate dielectrics 134 are a plurality of individual dielectric segments spaced apart by sidewall separators 135 and interlayer dielectrics 128.

[0027] like FIG. 1DAs shown in circuit diagram 100d, interconnect structure 119 couples a floating diffusion region 111 to an image processing circuit 136. The image processing circuit 136 includes pixel circuitry 144, an application-specific integrated circuit (ASIC) 146, a first pixel transistor 138, a second pixel transistor 140, and a third pixel transistor 142. In some embodiments, the photodetector 114, the transfer transistor 115, and the floating diffusion region 111 are on a first chip 137, and the image processing circuit 136 is on one or more additional chips. The transfer transistor 115 shares the floating diffusion region 111. Multiple photodetectors 114 are selectively coupled to the floating diffusion region 111 via the transfer transistor 115 (e.g., the coupling of the first photodetector to the floating diffusion region is controlled by the first transfer transistor, etc.). The floating diffusion region 111 is coupled to the source / drain region of the first pixel transistor 138 and the gate of the second pixel transistor 140. The second pixel transistor 140 is coupled in series with the third pixel transistor 142. Pixel circuit 144 is coupled to the source / drain region of the third pixel transistor 142. Pixel circuit 144 may include, for example, additional transistors, diodes, resistors, capacitors, inductors, or other suitable circuitry. In some embodiments, pixel circuit 144 is coupled to ASIC circuit 146. ASIC circuit 146 may include, for example, transistors, diodes, resistors, capacitors, inductors, or other suitable circuitry.

[0028] FIG. 2A , FIG. 2B , FIG. 2C and FIG. 2D Top view 200a and cross-sectional views 200b, 200c, and 200d show alternative embodiments of the front and rear DTI structures of a photodetector with an isolated pixel matrix, wherein the rear DTI structure is separated from the first doped region. FIG. 2B The sectional view 200b is along FIG. 2A The line C-C' is intercepted. FIG. 2C The sectional view 200c is along FIG. 2A The line D-D' is intercepted. Simultaneously describe... FIG. 2A , FIG. 2B and FIG. 2C . FIG. 2D The sectional view 200d is along FIG. 2A The line E-E' is intercepted.

[0029] In some embodiments, the rear-side DTI structure 106 is spaced apart from the first doped region 110 by the substrate 102. In some embodiments, a plurality of gate stacks 116 extend into the substrate 102 into regions of a plurality of photodetectors 114 having a first conductivity type. In some embodiments, the plurality of gate stacks 116 may also be surrounded by additional layers, such as a high-temperature oxide layer 202, a resistive protection layer 204, or a contact etch stop layer 206.

[0030] In some embodiments, the rear DTI structure 106 overlaps with the front DTI structure 104, and the rear DTI structure extension 106e replaces a portion of the front DTI structure 104 (see [link]). FIG. 2A and 2C The rear DTI structure extension 106e extends into the front DTI structure 104 for approximately 20 nm to 30 nm, 10 nm to 25 nm, 15 nm to 30 nm, or another similar range.

[0031] like FIG. 2D As shown in cross-sectional view 200d, in some embodiments, the front-side DTI structure 104 has a first thickness t1, while the rear-side DTI structure 106 has a second thickness t2, and the second thickness t2 is less than the first thickness t1. In some embodiments, the first thickness t1 is 160 to 180 nm, 170 to 190 nm, 170 to 180 nm, or within another similar range. In some embodiments, the second thickness t2 is 110 to 130 nm, 120 to 140 nm, 120 to 130 nm, or within another similar range. In some embodiments, the difference between the first thickness t1 and the second thickness t2 may cause the rear-side DTI structure extension 106e to be separated from the substrate 102 by a first insulating liner 122 and a second insulating liner 126.

[0032] FIG. 3A , FIG. 3B , FIG. 3C and FIG. 3D Top views 300a, 300d and sectional views 300b, 300c show alternative embodiments of the front and rear DTI structures of the photodetector with isolated pixel matrix. FIG. 3B The sectional view 300b is along FIG. 3A The view of line A-A'. FIG. 3C The sectional view 300c is along FIG. 3A The view of line B-B'. Top view 300d shows additional details not shown in top view 300a for clarity.

[0033] like FIG. 3AAs shown in top view 300a, in some embodiments, the first doped region 110 may extend along the sidewall of the rear DTI structure 106 past the outermost sidewall of the front DTI structure 104. In some embodiments, the first doped region 110 directly covers the photodetector 114 (shown in dashed lines). FIG. 3B As shown in cross-sectional view 300b, in some embodiments, the first doped region 110 contacts the outer wall of the front DTI structure 104. In other embodiments, the rear DTI structure 106 also contacts the first doped region 110. FIG. 3C As shown in cross-sectional view 300c, in some embodiments, the first doped region 110 covers the photodetector 114 and extends to a first side 102a of the substrate 102. In some embodiments, the portion of the first side 102a of the substrate 102 where the first doped region 110 extends is larger than the portion where the second doped region 112 extends.

[0034] like FIG. 3D As shown in the top view 300d, in some embodiments, the pixel region 108 includes a first corner 302a, a second corner 302b, a third corner 302c, and a fourth corner 302d. A first doped region 110 extends above and overlaps with the first corner 302a. A second doped region 112 extends above and overlaps with the second corner 302b. The rear-side DTI structure 106 includes a first segment 304a and a second segment 304b intersecting at the first corner 302a. The rear-side DTI structure 106 also includes a third segment 304c and a fourth segment 304d intersecting at the second corner 302b. The front DTI structure 104 includes a fifth segment 304e extending from the first segment 304a of the rear DTI structure 106, a sixth segment 304f extending from the second segment 304b of the rear DTI structure 106, a seventh segment 304g extending from the third segment 304c of the rear DTI structure 106, and an eighth segment 304h extending from the fourth segment 304d of the rear DTI structure 106. The fifth segment 304e and the seventh segment 304g intersect at the third corner 302c of the pixel area 108. The sixth segment 304f and the eighth segment 304h intersect at the fourth corner 302d of the pixel area 108.

[0035] FIG. 4A , FIG. 4B , FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B , FIG. 10A ,FIG. 10B , FIG. 11A , FIG. 11B , FIG. 12A , FIG. 12B , FIG. 13A , FIG. 13B , FIG. 14A , FIG. 14B , FIG. 14C , FIG. 15A , FIG. 15B , FIG. 16A , FIG. 16B , FIG. 17A and FIG. 17B A series of top and cross-sectional views illustrate some embodiments of a method for forming a front-side DTI structure and a rear-side DTI structure that isolates the photodetectors of the pixel matrix. In the above figures, figures ending with "A" (e.g., FIG. 4A , FIG. 5A , FIG. 6A (etc.) is a top view, while a drawing ending in "B" (e.g., FIG. 4B , FIG. 5B , FIG. 6B (etc.) is a sectional view taken from the corresponding top view along line C-C'. FIG. 14C It is along FIG. 14A The line A-A' intercepts FIG. 14A The sectional view. The top view and the corresponding sectional view are described simultaneously (e.g., simultaneously describing...). FIG. 4A and FIG. 4B (etc.). Although FIG. 4A through FIG. 17B The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted, in whole or in part.

[0036] like FIG. 4A Top view 400a and FIG. 4B As shown in cross-sectional view 400b, a sacrificial oxide layer 408 and a first mask layer 402 are formed over the substrate 102. The first mask layer 402 can be formed, for example, using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, etc. The first mask layer 402 is then patterned to expose the front-side DTI structure of the substrate 102 corresponding to the structure to be formed subsequently (see...). FIG. 1A(104) portion. In some embodiments, the first mask layer 402 is a photoresist or includes a photoresist and / or the first mask layer 402 is patterned using photolithography. In other embodiments, the first mask layer 402 is a hard mask including silicon nitride (Si3N4), silicon dioxide (SiO2), etc. The hard mask is patterned using another photoresist, which is patterned using photolithography and an etching process through the photoresist.

[0037] After patterning the first mask layer 402, a first etching process 404 is performed on the substrate 102 with the first mask layer 402 in place. The first etching process 404 removes the portion of the substrate 102 exposed by the first mask layer 402, thereby forming a first opening 406 within the substrate 102. In some embodiments, the first opening 406 is a series of segments depicting an array within the substrate 102. In some embodiments, the first etching process 404 is a dry etching process. In some embodiments, the first opening 406 has a depth d1 ranging from 2.8 micrometers to 3.2 micrometers, from 2.5 micrometers to 3.1 micrometers, from 2.9 micrometers to 3.5 micrometers, or another similar range. The first opening 406 includes a first cross-shaped opening 407a and a second cross-shaped opening 407b. The first cross-shaped opening 407a outlines the contour of a third corner 302c of the pixel region 108, and the second cross-shaped opening 407b outlines the contour of a fourth corner 302d of the pixel region 108.

[0038] like FIG. 5A Top view 500a and FIG. 5B As shown in cross-sectional view 500b, a first conformal liner 502 is formed above the first shielding layer 402 and within the first opening 406. In some embodiments, the first conformal liner 502 is formed using CVD, PVD, ALD, etc. The first conformal liner 502 covers the upper surface of the first mask layer 402. Additionally, the first conformal liner 502 covers the inner sidewall and bottom surface of the first opening 406. In some embodiments, the first conformal liner 502 is an insulating material or includes insulating materials, such as silicon dioxide (SiO2). The first conformal liner covers the inner sidewall and bottom surface of the first opening 406.

[0039] like FIG. 6A Top view 600a and FIG. 6BAs shown in the cross-sectional view 600b, a first conformal fill layer 602 is formed above a first conformal substrate 502. In some embodiments, the first conformal fill layer 602 is formed using CVD, PVD, ALD, etc. The first conformal fill layer 602 covers the upper surface of the first mask layer 402. Furthermore, the first conformal fill layer 602 covers the inner sidewalls and lower surface of the first conformal substrate 502. The first conformal fill layer 602 fills the first opening 406 (shown in dashed lines). In some embodiments, the first conformal fill layer 602 is a semiconductor material or includes a semiconductor material, such as polysilicon.

[0040] like FIG. 7A Top view 700a and FIG. 7B As shown in the sectional view 700b, the first conformal liner is removed (see...). FIG. 6B 502) and the first conformal fill layer (see 502) and the first conformal fill layer (see FIG. 6B The portion of the first conformal liner 122 (602) extending beyond the substrate 102 leaves the first insulating liner 122 and the first filler layer 120 within the first opening 406. Furthermore, the upper portion 702 of the first opening 406 is also exposed, such that the first insulating liner 122 and the first filler layer 120 are recessed from the first side 102a of the substrate 102. In some embodiments, removal is performed using an etching process 704 to remove the first conformal liner (see [reference]). FIG. 6B 502) and the first conformal fill layer (see 502) and the first conformal fill layer (see FIG. 6B The portion of 602 above the first mask layer 402 and the first conformal liner (see 602) FIG. 6B 502) and the first conformal fill layer (see 502) and the first conformal fill layer (see FIG. 6B The portion of 602 exposed by the first mask layer 402.

[0041] like FIG. 8A Top view 800a and FIG. 8B As shown in cross-sectional view 800b, a conformal capping layer 802 is formed within the upper portion 702 (shown in dashed lines) of the first opening 406 (shown in dashed lines). In some embodiments, the conformal capping layer 802 is formed using CVD, PVD, ALD, etc. The conformal capping layer 802 covers the upper surface of the first mask layer 402. Furthermore, the conformal capping layer 802 covers the inner sidewall of the first opening 406. In some embodiments, the conformal capping layer 802 is an insulating material or includes an insulating material, such as silicon dioxide (SiO2).

[0042] like FIG. 9A Top view 900a and FIG. 9B As shown in the sectional view 900b, the conformal top cover layer is removed (see...). FIG. 8BThe portion 802) is left with a top cap layer 123 filling the upper portion 702 (shown in dashed lines) of the first opening 406 (shown in dashed lines). In some embodiments, removal is performed using an etching process 902 to remove the conformal top cap layer (see [reference]). FIG. 8B The portion of the capping layer 123 above the substrate 102 (802). In some embodiments, the upper surface of the capping layer 123 is flush with the sacrificial oxide layer 408. In some embodiments, etching process 902 completes the front-side DTI structure 104 within the substrate 102. In some embodiments, the formation of the first insulating liner 122, the first filler layer 120, and the capping layer 123 is performed in a temperature range of 900 to 1200 degrees Celsius. In other embodiments, a separate high-temperature (e.g., at 900 to 1200 degrees Celsius) annealing process is performed. During the formation of the first doped region (see...) FIG. 1A 110) and the second doped region (see ... FIG. 1A The formation of the first insulating liner 122 and the first filler layer 120 prior to 112) allows for a higher thermal budget. Due to the higher thermal budget, a high-temperature process can be used to repair [the affected area]. FIG. 4A Damage to substrate 102 caused during the etching process described herein. Repairing the damage to substrate 102 increases the passivation of the front-side DTI structure 104, thereby improving the performance of the integrated device.

[0043] like FIG. 10A Top view 1000a and FIG. 10B As shown in the cross-sectional view 1000b, a removal process 1002 is performed to remove the first photomask layer 402 from the substrate 102. In some embodiments, the removal process 1002 is or includes a planarization process (e.g., chemical mechanical planarization (CMP) process), an etching process (e.g., dry etching process), etc. The removal process 1002 removes the first mask layer 402. In some embodiments, the removal process 1002 further removes the sacrificial oxide layer, exposing the substrate 102.

[0044] like FIG. 11A Top view 1100a and FIG. 11B As shown in cross-sectional view 1100b, a first doped region 110, a second doped region 112, and a floating diffusion region 111 are formed in the substrate 102. The first doped region 110, the second doped region 112, and the floating diffusion region 111 are formed using a doping process. The floating diffusion region 111 has a higher dopant concentration than the first doped region 110.

[0045] In some embodiments, the first doped region 110 and the second doped region 112 are formed in a pattern such that the first doped region 110 is formed in rows and columns of a first group, the second doped region is formed in rows and columns of a second group, and the rows and columns of the second group are offset from and interleaved with the rows and columns of the first group. That is, the first doped region in each row is separated from the first doped region in other rows by the rows of the second doped region. In addition, the first doped region in each column is separated from the first doped region in other columns by the columns of the second doped region. This pattern separates the individual first doped region 110 from the individual second doped region 112 by the pixel area 108, wherein the photodetector (see FIG. 1A 114) will be formed in pixel region 108 in the following steps. In some embodiments, the first doped region 110 includes a first doped region 110 at a first corner 302a of pixel region 108. The second doped region 112 includes a second doped region 112 at a second corner 302b of pixel region 108.

[0046] like FIG. 12A Top view 1200a and FIG. 12B As shown in cross-sectional view 1200b, a photodetector 114 and a gate stack 116 are formed on a substrate 102. In some embodiments, the photodetector 114 is formed using a doping process. In some embodiments, the gate stack 116 is formed using multiple deposition processes, etching processes, etc., to form a gate 132 above the pixel region 108 and a gate dielectric 134 separating the gate 132 from the pixel region 108. In some embodiments, multiple gates 132 extend into the substrate 102. In some embodiments, a high-temperature oxide layer 202, a resistive protection layer 204, and a contact etch stop layer 206 may be formed above the gate stack 116 and the substrate 102.

[0047] After forming the gate stack 116, a plurality of contacts 118 are formed. The plurality of contacts 118 couple the first doped region 110, the second doped region 112, and the gate 132 to the interconnect structure (see 119 in Figure 1). For easier viewing of the top views 1200a, 1300a, 1400a, 1500a, and 1600a alongside the corresponding cross-sectional views 1200b, 1300b, 1400b, 1500b, and 1600b, [the following text is missing from the original] FIG. 12B , FIG. 13B , FIG. 14B , FIG. 15B and FIG. 16B The interconnection structure is omitted.

[0048] like FIG. 13A Top view 1300a and FIG. 13BAs shown in the cross-sectional view 1300b, the lower portion of the substrate 102 is removed to expose the lower surface of the front-side DTI structure 104. In some embodiments, a planarization process 1302 (e.g., CMP process) is used to remove the lower portion of the substrate 102.

[0049] like FIG. 14A Top view 1400a and FIG. 14B As shown in the cross-sectional view 1400b, a second mask layer 1404 is formed above the second side 102b of the substrate 102. The second mask layer 1404 can be formed, for example, using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, etc. The second mask layer 1404 is then patterned to expose the backside DTI structure of the substrate 102 corresponding to the structure to be subsequently formed (see [reference]). FIG. 1A (106) portion. In some embodiments, the second mask layer 1404 is a photoresist or includes a photoresist and / or is patterned using photolithography. In other embodiments, the second mask layer 1404 is a hard mask including silicon nitride (Si3N4), silicon dioxide (SiO2), etc. The hard mask is patterned using an additional photoresist, which is patterned using photolithography and an etching process through the photoresist.

[0050] After the second mask layer 1404 is patterned, a second etching process 1402 is performed on the substrate 102 with the second mask layer 1404 in place. The second etching process 1402 removes the portion of the substrate 102 exposed by the second mask layer 1404, thereby forming a second opening 1406 within the substrate 102. In some embodiments, the second opening 1406 exposes the outer sidewall of the front-side DTI structure 104. The second opening 1406 extends between and is spaced apart from each other among the four portions of the front-side DTI structure 104. The second opening 1406 is vertically aligned with the first doped region 110 and the second doped region 112. That is, when the first side 102a of the substrate 102 is above the second side 102b of the substrate 102, the second opening 1406 is directly below the first doped region 110 and the second doped region 112 (e.g., a portion of the second opening 1406 is directly below the first doped region 110, and another portion of the second opening 1406 is directly below the second doped region 112). In some embodiments, the second opening 1406 extends into the first doped region 110 and the second doped region 112. In other embodiments, the second opening 1406 is separated from the first doped region 110 and the second doped region 112. In some embodiments, the second etching process 1402 is a dry etching process. After the second etching process 1402, the second mask layer 1404 is removed. In some embodiments, the second opening 1406 has a depth d2 within a range of 1.8 micrometers to 2.2 micrometers, 1.5 micrometers to 2.1 micrometers, 1.9 micrometers to 2.5 micrometers, or another similar range. In some embodiments, such as FIG. 14C As shown in the cross-sectional view 1400c, the second opening 1406 may have a depth that varies along the cross-section of the integrated device. The second opening 1406 includes a third cross-shaped opening 1407a and a fourth cross-shaped opening 1407b. The third cross-shaped opening 1407a outlines the contour of the first corner 302a of the pixel area 108, and the fourth cross-shaped opening 1407b outlines the contour of the second corner 302b of the pixel area 108.

[0051] like FIG. 15A Top view 1500a and FIG. 15B As shown in the cross-sectional view 1500b, a second conformal liner 1502 is formed above the second side 102b of the substrate 102 and within the second opening 1406. In some embodiments, the second conformal liner 1502 is formed using CVD, PVD, ALD, etc. The second conformal liner 1502 covers the inner sidewall and bottom surface of the second opening 1406. In some embodiments, the second conformal liner 1502 is an insulating material or includes an insulating material, such as silicon dioxide (SiO2).

[0052] like FIG. 16A Top view 1600a and FIG. 16BAs shown in cross-sectional view 1600b, a second conformal fill layer 1602 is formed over the second conformal liner 1502. In some embodiments, the second conformal fill layer 1602 is formed using CVD, PVD, ALD, etc. The second conformal fill layer 1602 covers the inner sidewalls and lower surface of the first conformal liner 502. The second conformal fill layer 1602 fills the first openings 406 (shown in dashed lines). In some embodiments, the second conformal fill layer 1602 is or includes a semiconductor material, such as polysilicon, etc. In some embodiments, the formation of the second conformal liner 1502 and the second conformal fill layer 1602 is performed in a temperature range of 300 to 450 degrees Celsius. In other embodiments, a separate low temperature (e.g., in the range of 300 to 450 degrees Celsius) anneal process is performed. The low temperature range for forming the second conformal liner and the second conformal fill layer is selected to remain within a lower available thermal budget after the formation of the first and second doped regions 110 and 112. The low temperature process reduces the amount of dopant diffusing from the first and second doped regions 110 and 112 into the substrate 102.

[0053] As shown in top view 1700a and cross-sectional view 1700b, after the formation of the second conformal fill layer (see 1602 of FIG. 16), portions of the second conformal fill layer (see 1602 of FIG. 16) and the second conformal liner (see 1502 of FIG. 15) that extend beyond the second side 102b of the substrate 102 are removed. In some embodiments, the removal is performed using a planarization process 1702 (e.g., a CMP process). The removal process leaves the second fill layer 124 and the second insulating liner 126 within the substrate, while forming the backside DTI structure 106. FIG. 17A FIG. 17B As shown in top view 1700a and cross-sectional view 1700b, after the formation of the second conformal fill layer (see 1602 of FIG. 16), portions of the second conformal fill layer (see 1602 of FIG. 16) and the second conformal liner (see 1502 of FIG. 15) that extend beyond the second side 102b of the substrate 102 are removed. In some embodiments, the removal is performed using a planarization process 1702 (e.g., a CMP process). The removal process leaves the second fill layer 124 and the second insulating liner 126 within the substrate, while forming the backside DTI structure 106. FIG. 16B FIG. 16B As shown in top view 1700a and cross-sectional view 1700b, after the formation of the second conformal fill layer (see 1602 of FIG. 16), portions of the second conformal fill layer (see 1602 of FIG. 16) and the second conformal liner (see 1502 of FIG. 15) that extend beyond the second side 102b of the substrate 102 are removed. In some embodiments, the removal is performed using a planarization process 1702 (e.g., a CMP process). The removal process leaves the second fill layer 124 and the second insulating liner 126 within the substrate, while forming the backside DTI structure 106. FIG. 16B After the planarization process 1702, the combined frontside and backside DTI structures 104 and 106 isolate the photodetectors 114 in the pixel regions 108 and form a continuous ring around the photodetectors 114 in the pixel regions 108. The frontside and backside DTI structures 104 and 106 isolate the pixel regions 108 from each other. The formation of the frontside DTI structure 104 before the formation of the photodetectors, doped regions, and active components makes a higher thermal budget available, and enables the use of higher temperature processes to repair substrate damage caused by the etching performed for the frontside DTI structure 104. Since the frontside DTI structure 104 provides most of the isolation, the higher temperature processes repair most of the damage to the substrate 102 of the combined structure, and increase the overall passivation of the combined structure.

[0054]

[0055] FIG. 18 ​​​A flowchart 1800 showing some embodiments of a method of forming a DTI structure having a first film, a second film, and a third film surrounding a DTI core, where the second film is a trapping film. Although this and other methods are shown and / or described herein as a series of acts or events, it is understood that the disclosure is not limited to the order of acts or events as shown. Thus, in some embodiments, the acts can be performed in an order other than that shown, and / or concurrently. Further, in some embodiments, acts or events shown can be subdivided into multiple acts or events, which can be performed at different times or concurrently with other acts or sub-acts. In some embodiments, some of the acts or events shown can be omitted, and other acts or events not shown can be included.

[0056] At 1802, a substrate including a first side, a second side, and a pixel region is received. See, e.g., FIG. 4.

[0057] At 1804, a first opening is etched into the first side of the substrate. See, e.g., FIG. 4.

[0058] At 1806, a front-side deep trench isolation (DTI) structure is formed within the first opening. See, e.g., FIGS. 5-10.

[0059] At 1808, the substrate is heated to repair damage to the substrate and increase passivation of the front-side DTI structure. See, e.g., the description of FIG. 7.

[0060] At 1810, a transfer transistor is formed in the pixel region of the first side of the substrate. See, e.g., FIGS. 11-12.

[0061] At 1812, a second opening is etched into the second side of the substrate. See, e.g., FIG. 14.

[0062] At 1814, a back-side DTI structure is formed within the second opening, where the back-side DTI structure and the front-side DTI structure form a continuous ring around the pixel region. See, e.g., FIGS. 15-17.

[0063] Some embodiments are directed to a pixel matrix, comprising: a substrate including a first side and a second side opposite the first side; a plurality of photodetectors located in the substrate, the plurality of photodetectors disposed symmetrically about a mid-axis between the plurality of photodetectors, where the mid-axis is perpendicular to the first side and the second side; a first doped region located at the mid-axis between the plurality of photodetectors and located at the first side of the substrate; a front-side deep trench isolation (DTI) structure located at the first side of the substrate and extending directly between photodetectors of the plurality of photodetectors; and a back-side DTI structure located at the second side of the substrate and separating the front-side DTI structure from the mid-axis.

[0064] In some embodiments, the front-side DTI structure extends from the first side of the substrate to the second side of the substrate; and the back-side DTI structure extends from the back-side portion of the substrate into the substrate such that the first doped region extends directly between the back-side DTI structure and the first side of the substrate. In some embodiments, the back-side DTI structure has a first surface that extends between the plurality of photodetectors and the first side of the substrate. In some embodiments, an outer sidewall of the front-side DTI structure directly contacts an outer sidewall of the back-side DTI structure. In some embodiments, the front-side DTI structure has a first thickness; and the back-side DTI structure has a second thickness that is less than the first thickness. In some embodiments, the back-side DTI structure extends into the front-side DTI structure. In some embodiments, the pixel matrix further comprises a plurality of second doped regions disposed symmetrically about the central axis, wherein the plurality of second doped regions have a positive electrical conductivity, and wherein the first doped region has a negative electrical conductivity. In some embodiments, the front-side DTI structure extends into the plurality of second doped regions.

[0065] Other embodiments are directed to an integrated device comprising: a substrate comprising a first side and a second side; a pixel region in the substrate, the pixel region comprising, when viewed from a top view, a first corner, a second corner, a third corner, and a fourth corner; a first photodetector in the pixel region of the substrate; a transistor on the first side of the substrate; a first doped region having a first conductivity type on the first side of the substrate, on a first side of the first photodetector, and overlapping the first corner of the pixel region; a second doped region having a second conductivity type on the first side of the substrate, on a second side of the first photodetector opposite the first side of the first photodetector, and overlapping the second corner of the pixel region opposite the first corner; a back-side deep trench isolation (DTI) structure on the second side of the substrate directly below the first doped region and the second doped region, the back-side DTI structure comprising a first segment and a second segment intersecting at the first corner of the pixel region and a third segment and a fourth segment intersecting at the second corner of the pixel region; and a front-side DTI structure on the first side of the substrate, the front-side DTI structure having a fifth segment extending from the first segment of the back-side DTI structure, a sixth segment extending from the second segment of the back-side DTI structure, a seventh segment extending from the third segment of the back-side DTI structure, and an eighth segment extending from the fourth segment of the back-side DTI structure, wherein the fifth segment and the seventh segment intersect at the third corner of the pixel region and the sixth segment and the eighth segment intersect at the fourth corner of the pixel region.

[0066] In some embodiments, the backside DTI structure extends from the second side of the substrate to the first doped region. In some embodiments, a first segment of the backside DTI structure intersects a second segment directly below the first doped region; a third segment of the backside DTI structure intersects a fourth segment directly below the second doped region; and the first photodetector is located directly between the first corner and the second corner of the pixel region. In some embodiments, a fifth segment of the frontside DTI structure, along with a seventh segment, extends from the first segment to the third segment of the backside DTI structure, and further extends around the third corner of the pixel region; and a sixth segment of the frontside DTI structure, along with an eighth segment, extends from the second segment to the fourth segment of the backside DTI structure, and further extends around the fourth corner of the pixel region. In some embodiments, the frontside DTI structure further comprises a first fill layer, a cap layer covering the first fill layer, and a first insulating liner surrounding the first fill layer and separating the first fill layer from the substrate, and the backside DTI structure further comprises a second fill layer and a second insulating liner surrounding the second fill layer and separating the second fill layer from the substrate, wherein the first insulating liner has a first sidewall and the second insulating liner has a second sidewall contacting the first sidewall.

[0067] Yet other embodiments are directed to a method of forming an integrated device, comprising: receiving a substrate, the substrate comprising a first side, a second side, and a pixel region, the pixel region having a first corner, a second corner, a third corner, and a fourth corner when viewed from a top perspective; etching a first opening on the first side of the substrate, the first opening comprising a first cross-shaped opening and a second cross-shaped opening, the first cross-shaped opening outlining a profile of the third corner of the pixel region, the second cross-shaped opening outlining a profile of the fourth corner of the pixel region; forming a frontside deep trench isolation (DTI) structure within the first opening; forming a first doped region having a first conductivity type at the first corner of the pixel region; forming a second doped region having a second conductivity type at the second corner of the pixel region; forming a pass transistor in the pixel region on the first side of the substrate; etching a second opening on the second side of the substrate, the second opening comprising a third cross-shaped opening and a fourth cross-shaped opening, the third cross-shaped opening being located below the first corner of the pixel region, the fourth cross-shaped opening being located below the second corner of the pixel region; and forming a backside DTI structure within the second opening, wherein the backside DTI structure and the frontside DTI structure form a continuous ring around the pixel region, and the backside DTI structure separates the frontside DTI structure from the first corner and the second corner of the pixel region.

[0068] In some embodiments, the first doped region extends into a pixel region of the substrate, the second doped region extends into the pixel region of the substrate; and the backside DTI structure is formed directly below the first doped region and the second doped region. In some embodiments, the frontside DTI structure is formed in a first temperature range, the backside DTI structure is formed in a second temperature range, and a lowest temperature in the first temperature range is higher than a highest temperature in the second temperature range. In some embodiments, the method further comprises, after forming the pass transistor and before etching the second opening, performing a planarization process on the second side of the substrate to remove portions of the substrate below a bottom surface of the frontside DTI structure. In some embodiments, forming the frontside DTI structure further comprises: forming a first insulating liner over inner sidewalls and a bottom surface of the first opening; forming a first fill layer within the first opening to fill the first opening; removing portions of the first insulating liner and the first fill layer that cover the substrate and extend into the substrate to expose an upper portion of the first opening; and filling the upper portion of the first opening with a cap layer. In some embodiments, forming the backside DTI structure further comprises: forming a second insulating liner over inner sidewalls and a bottom surface of the second opening; forming a second fill layer within the second opening to fill the second opening; and removing portions of the second insulating liner and the second fill layer that cover the substrate. In some embodiments, etching the second opening exposes outer sidewalls of the frontside DTI structure.

[0069] It should be understood that the use of the terms "first", "second", "third", etc. in this written description and in the claims are merely used as general identifiers to distinguish between different components of a figure or series of figures. These terms do not imply any temporal or structural proximity as a matter of their own, and are not intended to describe corresponding components in different illustrated embodiments and / or unillustrated embodiments. For example, a "first dielectric layer" described in connection with a first figure can not necessarily correspond to a "first dielectric layer" described in connection with another figure, and can not necessarily correspond to a "first dielectric layer" in unillustrated embodiments.

[0070] Finally, it should be noted that the above-described embodiments are merely intended for describing the technical solutions of the present application, but are not intended to limit the present application; even though the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or equivalently replace some or all of the technical features thereof; and such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel matrix, characterized by comprising: a substrate comprising a first side and a second side opposite the first side; a plurality of photodetectors located in the substrate, the plurality of photodetectors disposed symmetrically about a central axis between the plurality of photodetectors, wherein the central axis is perpendicular to the first side and the second side; a first doped region located at the central axis between the plurality of photodetectors and located at the first side of the substrate; a front side deep trench isolation structure located at the first side of the substrate and directly extending between photodetectors of the plurality of photodetectors; and a back side deep trench isolation structure located at the second side of the substrate and separating the front side deep trench isolation structure from the central axis.

2. The pixel matrix of claim 1, wherein: the front side deep trench isolation structure extends from the first side of the substrate to the second side of the substrate; and wherein the back side deep trench isolation structure extends from a back side portion of the substrate into the substrate such that the first doped region directly extends between the back side deep trench isolation structure and the first side of the substrate. the back side deep trench isolation structure has a first surface extending between the plurality of photodetectors and the first side of the substrate.

3. The pixel matrix of claim 1, wherein 4. The pixel matrix of claim 1, wherein: an outer sidewall of the front side deep trench isolation structure directly contacts an outer sidewall of the back side deep trench isolation structure.

5. The pixel matrix of claim 1, wherein: the front side deep trench isolation structure has a first thickness; and the back side deep trench isolation structure has a second thickness, the second thickness being less than the first thickness. the back side deep trench isolation structure extends into the front side deep trench isolation structure.

6. The pixel matrix of claim 1, wherein comprising:

7. An integrated device, characterized by a substrate comprising a first side and a second side; a pixel region located in the substrate, the pixel region comprising, when viewed from a top-down perspective, a first corner, a second corner, a third corner, and a fourth corner; a first photodetector located in the pixel region of the substrate; a transistor located at the first side of the substrate; a first doped region having a first conductivity type located at the first side of the substrate, located at a first side of the first photodetector, and overlapping the first corner of the pixel region; a second doped region having a second conductivity type located at the first side of the substrate, located at a second side of the first photodetector opposite the first side of the first photodetector, and overlapping the second corner of the pixel region opposite the first corner; a back side deep trench isolation structure located at the second side of the substrate directly below the first doped region and the second doped region, the back side deep trench isolation structure comprising a first segment and a second segment intersecting at the first corner of the pixel region and a third segment and a fourth segment intersecting at the second corner of the pixel region; and a second photodetector located in the pixel region of the substrate. ​ A front side deep trench isolation structure is located at the first side of the substrate, the front side deep trench isolation structure includes a fifth segment extending from the first segment of the back side deep trench isolation structure, a sixth segment extending from the second segment of the back side deep trench isolation structure, a seventh segment extending from the third segment of the back side deep trench isolation structure, and an eighth segment extending from the fourth segment of the back side deep trench isolation structure, wherein the fifth segment intersects with the seventh segment at the third corner of the pixel region, and the sixth segment intersects with the eighth segment at the fourth corner of the pixel region.

8. The integrated device of claim 7, wherein, The back side deep trench isolation structure extends from the second side of the substrate to the first doped region.

9. The integrated device of claim 7, wherein, The first segment of the back side deep trench isolation structure intersects with the second segment directly below the first doped region. The third segment of the back side deep trench isolation structure intersects with the fourth segment directly below the second doped region. The first photodetector is directly located between the first corner and the second corner of the pixel region.

10. The integrated device of claim 9, wherein, The fifth segment of the front side deep trench isolation structure, together with the seventh segment, extends from the first segment to the third segment of the back side deep trench isolation structure, and further extends around the third corner of the pixel region. The sixth segment of the front side deep trench isolation structure, together with the eighth segment, extends from the second segment to the fourth segment of the back side deep trench isolation structure, and further extends around the fourth corner of the pixel region. ​

Images