Display device

Abstract

A display device includes: a substrate on which a display element is arranged; a first transistor disposed on the substrate and including a first semiconductor pattern including a silicon semiconductor and a first gate electrode insulated from and disposed over the first semiconductor pattern; a second transistor disposed on the substrate and including a second semiconductor pattern including an oxide semiconductor and a 2-1-th gate electrode insulated from the second semiconductor pattern and disposed over the second semiconductor pattern; and a first connection electrode connecting the first semiconductor pattern and the second semiconductor pattern to each other, in which the first connection electrode and the 2-1-th gate electrode are arranged in the same layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0001671, filed on January 4, 2024, and all benefits accruing therefrom, the contents of which are incorporated herein in their entirety. TECHNICAL FIELD

[0002] One or more embodiments relate to a display device, for example, a display device including an organic light emitting diode. BACKGROUND

[0003] A display device visually displays data. The display device can provide an image by using a light emitting diode. Applications of the display device have diversified, and various designs for improving the quality of the display device have been attempted. SUMMARY

[0004] One or more embodiments include a display device that can be driven to reduce power consumption of the display device and achieve high integration by using a transistor including a silicon semiconductor and a transistor including an oxide semiconductor. However, such technical problems are examples, and one or more embodiments are not limited thereto.

[0005] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description and drawings or can be learned by practice of the presented embodiments of the disclosure.

[0006] According to one or more embodiments, a display device includes a substrate on which a display element is arranged, a first transistor arranged on the substrate and including a first semiconductor pattern including a silicon semiconductor and a first gate electrode insulated from the first semiconductor pattern and arranged above the first semiconductor pattern, a second transistor arranged on the substrate and including a second semiconductor pattern including an oxide semiconductor and a 2-1 gate electrode insulated from the second semiconductor pattern and arranged below the second semiconductor pattern, and a first connection electrode connecting the first semiconductor pattern and the second semiconductor pattern to each other, wherein the first connection electrode and the 2-1 gate electrode are arranged in the same layer.

[0007] According to one or more embodiments, the display device can further include a second connection electrode connecting the first gate electrode and the second semiconductor pattern to each other.

[0008] According to one or more embodiments, the second connection electrode can be arranged in the same layer as the first connection electrode.

[0009] According to one or more embodiments, the display device can further include a 2-2 gate electrode insulated from the second semiconductor pattern and arranged below the second semiconductor pattern.

[0010] According to one or more embodiments, the display device can further include a capacitor electrode insulated from and disposed over the first gate electrode, wherein the first connection electrode and the capacitor electrode can be disposed in the same layer.

[0011] According to one or more embodiments, the first gate electrode and the 2-2 gate electrode can be disposed in the same layer.

[0012] According to one or more embodiments, the first semiconductor pattern and the second semiconductor pattern can be disposed in the same layer.

[0013] According to one or more embodiments, the first connection electrode can be connected to the second semiconductor pattern through a contact hole defined in an insulating layer disposed between the first connection electrode and the second semiconductor pattern, wherein the contact hole can include, in a plan view, a first region overlapping the first connection electrode and a second region not overlapping the first connection electrode.

[0014] According to one or more embodiments, a side surface of the first connection electrode and the insulating layer facing the first region can be in direct contact with each other.

[0015] According to one or more embodiments, another insulating layer covering the first connection electrode can be provided in the display device, and the second semiconductor pattern can be in direct contact with the other insulating layer in the second region.

[0016] According to one or more embodiments, a display device includes a substrate; a first transistor disposed on the substrate and including a first semiconductor pattern including a silicon semiconductor and a first gate electrode insulated from and disposed over the first semiconductor pattern, wherein the first semiconductor pattern includes a first channel region overlapping the first gate electrode and first source and drain regions disposed on both sides of the first channel region opposite to each other; a second transistor disposed on the substrate, including a second semiconductor pattern including an oxide semiconductor and a 2-1 gate electrode insulated from and disposed over the second semiconductor pattern, and electrically connected to the first transistor, wherein the second semiconductor pattern includes a second channel region overlapping the 2-1 gate electrode and second source and drain regions disposed on both sides of the second channel region opposite to each other; a first connection electrode connected to one of the first source and drain regions of the first semiconductor pattern; a second connection electrode connected to one of the second source and drain regions of the second semiconductor pattern; and an insulating layer disposed between the first connection electrode and the second connection electrode, wherein the second connection electrode is disposed under the insulating layer, and the first connection electrode is disposed on the insulating layer.

[0017] According to one or more embodiments, the first portion of the second connection electrode can be connected to one of the second source region and the second drain region of the second semiconductor pattern, and the second portion of the second connection electrode can be connected to the other of the first source region and the first drain region of the first semiconductor pattern.

[0018] According to one or more embodiments, the first portion of the second connection electrode can be connected to one of the second source region and the second drain region of the second semiconductor pattern, and the second portion of the second connection electrode can be connected to the first gate electrode.

[0019] According to one or more embodiments, the second connection electrode and the 2-1 gate electrode can be disposed in the same layer.

[0020] According to one or more embodiments, the display device can further include a capacitor electrode disposed above the first gate electrode and insulated from the first gate electrode, wherein the second connection electrode and the capacitor electrode can be disposed in the same layer.

[0021] According to one or more embodiments, the display device can further include a capacitor electrode disposed above the first gate electrode and insulated from the first gate electrode, and the second semiconductor pattern and the capacitor electrode can be disposed in the same layer.

[0022] According to one or more embodiments, the display device can further include a 2-2 gate electrode insulated from and disposed below the second semiconductor pattern.

[0023] According to one or more embodiments, the second connection electrode and the first gate electrode can be disposed in the same layer.

[0024] According to one or more embodiments, the first semiconductor pattern and the second semiconductor pattern can be disposed in the same layer.

[0025] According to one or more embodiments, the second connection electrode can be connected to one of the second source region and the second drain region of the second semiconductor pattern through a contact hole defined in another insulating layer disposed between the second connection electrode and the second semiconductor pattern, wherein, in a plan view, the contact hole can include a first region overlapping the second connection electrode and a second region not overlapping the second connection electrode, and the second semiconductor pattern can include a buffer region overlapping the second region. BRIEF DESCRIPTION OF DRAWINGS

[0026] The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a schematic perspective view of a display device according to an embodiment;

[0028] Figure 2 is a schematic cross-sectional view of a portion of a display device according to an embodiment;

[0029] Figure 3 is an equivalent circuit diagram showing a sub-pixel circuit configured to drive a sub-pixel and an organic light emitting diode as a display element connected to the sub-pixel circuit according to an embodiment;

[0030] Figure 4 is an equivalent circuit diagram showing a sub-pixel circuit configured to drive a sub-pixel and an organic light emitting diode as a display element connected to the sub-pixel circuit according to another embodiment;

[0031] Figure 5A is an enlarged plan view of a portion of a display device according to an embodiment;

[0032] Figure 5B is a cross-sectional view of the display device of Figure 5A taken along the line Vb-Vb’ of Figure 5A ;

[0033] Figure 6A is an enlarged plan view of a portion of a display device according to another embodiment;

[0034] Figure 6B is a cross-sectional view of the display device of Figure 6A taken along the line VIb-VIb’ of Figure 6A ;

[0035] Figure 7A is an enlarged plan view of a portion of a display device according to yet another embodiment;

[0036] Figure 7B is a cross-sectional view of the display device of Figure 7A taken along the line VIIb-VIIb’ of Figure 7A ;

[0037] Figure 8A is an enlarged plan view of a portion of a display device according to still another embodiment;

[0038] Figure 8B is a cross-sectional view of the display device of Figure 8A taken along the line VIIIb-VIIIb’ of Figure 8A ;

[0039] Figure 9A is an enlarged plan view of a portion of a display device according to yet another embodiment;

[0040] Figure 9B is a cross-sectional view of the display device of Figure 9A taken along the line IXb-IXb’ of Figure 9A ;

[0041] Figure 10A is a magnified plan view of a portion of a display device according to yet another embodiment;

[0042] Figure 10B is a cross-sectional view of the display device of Figure 10A taken along line Xb-Xb' of Figure 10A

[0043] Figure 11A is a magnified plan view of a portion of a display device according to yet another embodiment;

[0044] Figure 11B is a cross-sectional view of the display device of Figure 11A taken along line XIb-XIb' of Figure 11A

[0045] Figure 12A is a magnified plan view schematically illustrating a portion of a display device according to an embodiment;

[0046] Figure 12B is a cross-sectional view of the display device of Figure 12A taken along line XIIb-XIIb' of Figure 12A

[0047] Figure 12C is a cross-sectional view of the display device of Figure 12A taken along line XIIc-XIIc' of Figure 12A

[0048] Figure 13 is a magnified plan view schematically illustrating a portion of a display device according to another embodiment; and

[0049] Figure 14 is a magnified plan view schematically illustrating a portion of a display device according to yet another embodiment. DETAILED DESCRIPTION

[0050] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the drawings, to explain aspects of this description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0051] ​​​​Since the present description allows various changes and numerous embodiments, specific embodiments will be illustrated in the drawings and described in the written description in detail. The effects and features of one or more embodiments and the method of achieving them will become apparent by referring to the following detailed description of one or more embodiments in conjunction with the accompanying drawings. However, the present embodiments can have different forms and should not be construed as being limited to the description set forth herein.

[0052] One or more embodiments will be described in greater detail below with reference to the accompanying drawings. Like or corresponding elements are denoted by like reference numerals, regardless of whether they are illustrated in different drawings, and redundant descriptions thereof will be omitted.

[0053] Although terms such as "first" and "second" can be used to describe various elements, the elements should not be limited by the above terms. The above terms are used only to distinguish one element from another.

[0054] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0055] It will be understood that the terms "includes," "comprises," and "has," as used herein, indicate the presence of stated features or elements but do not preclude the presence or addition of one or more other features or elements.

[0056] It will be further understood that when a layer, region, or element is referred to as being "on" another layer, region, or element, it can be directly on the other layer, region, or element, or intervening layers, regions, or elements can also be present. That is, for example, one or more intervening layers, regions, or elements, can be present in between the layer, region, or element and the other layer, region, or element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0057] The size of the elements in the drawings can be exaggerated or reduced for the sake of explanation. For example, since the size and thickness of the elements in the drawings are arbitrarily shown for the sake of explanation, the following embodiments are not limited thereto.

[0058] When the embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described sequence.

[0059] As used herein, the expression "A and / or B" means A, B, or A and B. In addition, the expression "at least one of A and B" means A, B, or A and B.

[0060] It will be further understood that when a layer, region or element is referred to as being "connected" to another layer, region or element, it can be directly connected to the other layer, region or element or intervening layers, regions or elements can be present. For example, when a layer, region or element is referred to as being electrically connected to another layer, region or element, it can be electrically connected directly to the other layer, region or element, or intervening layers, regions or elements can be present.

[0061] The x-axis, y-axis and z-axis are not limited to three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0062] Figure 1 is a schematic perspective view of a display device 1 according to an embodiment.

[0063] Referring to Figure 1 , the display device 1 can include a display area DA and a non-display area NDA outside the display area DA. The display area DA can display an image by the sub-pixels P arranged in the display area DA. The non-display area NDA is arranged outside the display area DA, is an area in which an image is not displayed, and can surround the entirety of the display area DA. A driver for providing an electrical signal or power to the display area DA can be arranged in the non-display area NDA. A land, which is an area to which an electronic element or a printed circuit board can be electrically connected, can be arranged in the non-display area NDA.

[0064] In an embodiment, Figure 1 A display area DA having a polygonal shape (e.g., a quadrilateral shape) in which a length of the display area DA in the x-axis direction is less than a length of the display area DA in the y-axis direction is illustrated. However, in another embodiment, the display area DA can have a polygonal shape (e.g., a quadrilateral shape) in which a length of the display area DA in the y-axis direction is less than a length of the display area DA in the x-axis direction. Although Figure 1 A display area DA having a substantially quadrilateral shape is illustrated, but one or more embodiments are not limited thereto. In another embodiment, the display area DA can have various shapes such as an N-gon shape (where N is a natural number equal to or greater than 3), a circular shape, or an elliptical shape. Figure 1 A corner portion of the display area DA including a vertex at which a straight line and another straight line intersect is illustrated. However, in another embodiment, the display area DA can have a polygonal shape in which the corner portion is curved.

[0065] Although it is described below that the display device 1 is an electronic device such as a smartphone for convenience, the display device 1 described herein is not limited thereto. The display device 1 can be applied not only to portable electronic devices such as mobile phones, smartphones, tablet personal computers ("PCs"), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players ("PMPs"), navigation systems, and ultra-mobile PCs ("UMPCs"), but also to various products such as televisions, notebook computers, monitors, billboards, and Internet of Things ("IoT") devices. Furthermore, the display device 1 according to an embodiment can be applied to wearable devices such as smartwatches, watch phones, glasses-type displays, and head-mounted displays ("HMDs"). Furthermore, the display device 1 according to an embodiment can be applied to an instrument panel of a car, a central information display ("CID") placed on a center console or an instrument panel of a car, an in-vehicle rear mirror display that replaces a rear mirror of a car, or a display screen placed on the back of a front seat as an entertainment facility for rear seats of a car.

[0066] Figure 2 is a schematic cross-sectional view of a portion of the display device 1 according to an embodiment. Figure 2 is a cross-sectional view of the display device 1 of Figure 1 taken along line II-II' of Figure 1 .

[0067] Referring to Figure 2 , a sub-pixel P including an organic light emitting diode OLED and a thin film transistor TFT can be disposed in a display area DA, on a substrate 100.

[0068] The substrate 100 can include glass or a polymer resin. The substrate 100 including the polymer resin can be flexible, rollable, or bendable. The substrate 100 can have a multi-layer structure including layers and inorganic layers, the layers including a polymer resin.

[0069] A thin film transistor TFT, an organic light emitting diode OLED electrically connected to the thin film transistor TFT, and an insulating layer IL disposed therebetween can be disposed on the substrate 100. The thin film transistor TFT can be configured to provide a voltage to drive the organic light emitting diode OLED. The insulating layer IL can include a plurality of layers.

[0070] The organic light emitting diode OLED can include a sub-pixel electrode 210, an intermediate layer 220, and a counter electrode 230.

[0071] The sub-pixel electrode 210 can be disposed on the insulating layer IL. The sub-pixel electrode 210 can be a transparent or semi-transparent electrode, or can be a reflective electrode. When the sub-pixel electrode 210 is a transparent or semi-transparent electrode, the sub-pixel electrode 210 can include, for example, indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide ("IGO"), or aluminum zinc oxide ("AlZO"). When the sub-pixel electrode 210 is a reflective electrode, the sub-pixel electrode 210 can include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a layer including ITO, IZO, ZnO, or In2O3 on the reflective layer. In an embodiment, the sub-pixel electrode 210 can have a structure in which an ITO layer, an Ag layer, and an ITO layer are sequentially stacked with each other. However, one or more embodiments are not limited thereto, and the sub-pixel electrode 210 can include various materials, and the structure of the sub-pixel electrode 210 can also have various variations such as a single layer structure or a multi-layer structure.

[0072] The sub-pixel definition layer PDL can cover an edge region (or an edge) of the sub-pixel electrode 210. The sub-pixel definition layer PDL can define an opening in the sub-pixel definition layer PDL that exposes a portion of the sub-pixel electrode 210. The opening in the sub-pixel definition layer PDL can correspond to a region in which light of the organic light emitting diode OLED is emitted, and can define a sub-pixel P (refer to FIG. 2B) or an emission region of the organic light emitting diode OLED. Figure 1 ) or an emission region of the organic light emitting diode OLED.

[0073] The intermediate layer 220 can be disposed on the sub-pixel electrode 210. The intermediate layer 220 can include an organic emission layer including a low molecular weight material or a polymer material. The intermediate layer 220 can have a structure in which a hole injection layer, a hole transport layer, an organic emission layer, an electron transport layer, and / or an electron injection layer are stacked in a single structure or a complex structure.

[0074] The counter electrode 230 can be disposed on the intermediate layer 220. The counter electrode 230 can be a transparent or semi-transparent electrode. When the counter electrode 230 is a transparent or semi-transparent electrode, the counter electrode 230 can include one or more materials selected from Ag, Al, Mg, Li, Ca, Cu, LiF, MgAg, and CaAg, or a material having a multi-layer structure such as LiF / Ca or LiF / Al, and can be in a form of a thin film having a thickness of several nanometers to several tens of nanometers. The structure and material of the counter electrode 230 are not limited thereto, and can have various variations.

[0075] A encapsulation layer 300 can be disposed on the counter electrode 230. The encapsulation layer 300 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the encapsulation layer 300 can include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), and / or silicon oxynitride (SiON), and the organic encapsulation layer 320 can include at least one organic insulating material selected from polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyformaldehyde, polyarylate, and hexamethyldisiloxane.

[0076] Figure 3 is an equivalent circuit diagram showing a sub-pixel circuit PC configured to drive a sub-pixel P and an organic light emitting diode OLED as a display element connected to the sub-pixel circuit PC according to an embodiment.

[0077] Referring to Figure 3 , the sub-pixel circuit PC includes first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, a first capacitor Cst1, and a second capacitor Cst2. Further, the sub-pixel circuit PC is connected to a plurality of signal lines, a first initialization voltage line VL1 and a second initialization voltage line VL2, and a power voltage line PL. The signal lines can include a data line DL, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, and an emission control line EL. In another embodiment, at least one of the signal lines, the first initialization voltage line VL1 and the second initialization voltage line VL2, and / or the power voltage line PL can be shared by adjacent sub-pixel circuits.

[0078] The power voltage line PL can be configured to deliver a first power voltage ELVDD to the first transistor T1. The first initialization voltage line VL1 can be configured to deliver a first initialization voltage Vint1 for initializing the first transistor T1 to the sub-pixel circuit PC. The second initialization voltage line VL2 can be configured to deliver a second initialization voltage Vint2 for initializing the organic light emitting diode OLED to the sub-pixel circuit PC.

[0079] In Figure 3 , the third transistor T3 and the fourth transistor T4 among the first to seventh transistors T1 to T7 are shown as implemented as N-channel MOSFETs ("NMOS"), while the other transistors are shown as implemented as P-channel MOSFETs ("PMOS").

[0080] The first transistor T1 is connected to the power voltage line PL via the fifth transistor T5 and is electrically connected to the organic light emitting diode OLED via the sixth transistor T6. The first transistor T1 serves as a driving transistor and is configured to receive a data signal Dm according to a switching operation of the second transistor T2 and to supply a driving current to the organic light emitting diode OLED.

[0081] The second transistor T2 is a switching transistor, connected to the first scan line SL1 and the data line DL, and connected to the power voltage line PL via the fifth transistor T5. The second transistor T2 is turned on according to a first scan signal Sn received through the first scan line SL1 to perform a switching operation for transmitting a data signal Dm transmitted through the data line DL to the first node N1.

[0082] The third transistor T3 is a compensation transistor, connected to the second scan line SL2, and connected to the organic light emitting diode OLED via the sixth transistor T6. The third transistor T3 is turned on according to a second scan signal Sn’ received through the second scan line SL2 to diode-connect the first transistor T1.

[0083] The fourth transistor T4 is a first initialization transistor, connected to the third scan line SL3 which is a preceding scan line and the first initialization voltage line VL1, and turned on according to a third scan signal Sn-1 which is a preceding scan signal received through the third scan line SL3 to transmit a first initialization voltage Vint1 from the first initialization voltage line VL1 to a gate electrode of the first transistor T1 and initialize a voltage of the gate electrode of the first transistor T1.

[0084] The fifth transistor T5 can be an operation control transistor, and the sixth transistor T6 can be an emission control transistor. The fifth transistor T5 and the sixth transistor T6 are connected to the emission control line EL and are simultaneously turned on according to an emission control signal En received through the emission control line EL to form a current path allowing a driving current to flow in a direction from the power voltage line PL to the organic light emitting diode OLED.

[0085] The seventh transistor T7 is a second initialization transistor, connected to the fourth scan line SL4 which is a subsequent scan line and the second initialization voltage line VL2, and can be turned on according to a fourth scan signal Sn+1 which is a subsequent scan signal received through the fourth scan line SL4 to transmit a second initialization voltage Vint2 from the second initialization voltage line VL2 to the organic light emitting diode OLED and initialize the organic light emitting diode OLED. In another embodiment, the seventh transistor T7 can be omitted.

[0086] The first capacitor Cst1 may include a first capacitor electrode CE1-1 and a first capacitor electrode CE1-2. The first capacitor electrode CE1-1 is connected to the gate electrode of the first transistor T1, and the first capacitor electrode CE1-2 is connected to the power voltage line PL. The first capacitor Cst1 can maintain the voltage applied to the gate electrode of the first transistor T1 by storing and maintaining a voltage corresponding to the voltage difference between the power voltage line PL and the gate electrode of the first transistor T1.

[0087] The second capacitor Cst2 may include a second-first capacitor electrode CE2-1 and a second-second capacitor electrode CE2-2. The second-first capacitor electrode CE2-1 is connected to the gate electrode of the first scan line SL1 and the second transistor T2. The second-second capacitor electrode CE2-2 is connected to the gate electrode of the first transistor T1 and the first-first capacitor electrode CE1-1 of the first capacitor Cst1. The second capacitor Cst2 is a boost capacitor, and when the first scan signal Sn of the first scan line SL1 is the voltage used to turn off the second transistor T2, the voltage at the node can be increased to decrease the voltage used to display black. In another embodiment, the second capacitor Cst2 may be omitted.

[0088] Organic light-emitting diodes (OLEDs) may include sub-pixel electrodes 210 (reference) Figure 2 ) and counter electrode 230 (reference) Figure 2 Sub-pixel electrode 210 ( Figure 2 The sub-pixel electrode 210 can receive the first electrical voltage ELVDD via the fifth transistor T5, the first transistor T1, and the sixth transistor T6. The counter electrode 230 ( Figure 2 The counter electrode 230 can receive a second electrical voltage ELVSS. The organic light-emitting diode (OLED) receives the current (i.e., drive current) caused by the potential difference between the first electrical voltage ELVDD and the second electrical voltage ELVSS, and therefore emits light to display an image.

[0089] In this embodiment, at least one of the plurality of transistors T1 to T7 includes a semiconductor layer comprising an oxide, and the other transistors include a semiconductor layer comprising silicon. For example, the first transistor T1, which directly affects the brightness of the display device, can be configured to include a semiconductor layer composed of polycrystalline silicon (e.g., low-temperature polycrystalline silicon (“LTPS”)) with high reliability, and thus a high-resolution display device can be achieved.

[0090] Meanwhile, the oxide semiconductor has a high carrier mobility and a low leakage current, and thus, even if the driving time is long, the voltage drop is not significant. That is, even during low-frequency driving, the change in color of an image due to the voltage drop is not significant, which makes low-frequency driving possible. As described above, because the oxide semiconductor has a low leakage current, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can include the oxide semiconductor, and thus, the leakage current that can flow to the gate electrode of the first transistor T1 can be prevented and power consumption can also be reduced.

[0091] Figure 4 is an equivalent circuit diagram showing a sub-pixel circuit PC configured to drive a sub-pixel P and an organic light emitting diode OLED as a display element connected to the sub-pixel circuit PC according to another embodiment. Features repeated with the features of the embodiment shown in Figure 3 are omitted below, and differences are mainly described.

[0092] Reference Figure 4 The sub-pixel circuit PC includes first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8 and a first capacitor Cst1.

[0093] In Figure 4 , the third transistor T3 and the fourth transistor T4 among the first to eighth transistors T1 to T8 are shown as being implemented as N-channel MOSFETs (NMOS), while the other transistors are shown as being implemented as P-channel MOSFETs (PMOS).

[0094] The seventh transistor T7 is a second initialization transistor connected to an emission control line EL and a second initialization voltage line VL2, and can be turned on according to an emission control signal En received through the emission control line EL to transfer a second initialization voltage Vint2 from the second initialization voltage line VL2 to the organic light emitting diode OLED and initialize the organic light emitting diode OLED.

[0095] The eighth transistor T8 is a stress transistor connected to a fourth scan line SL4 which is a post scan line and a stress voltage line VOBSL, and can be turned on according to a fourth scan signal Sn+1 which is a post scan signal received through the fourth scan line SL4 to supply a stress voltage VOBS from the stress voltage line VOBSL to the first transistor T1. The stress voltage VOBS can be equal to or less than the first power voltage ELVDD. The stress voltage VOBS can be supplied to the first transistor T1 through the eighth transistor T8, and thus, a hysteresis phenomenon (e.g., a stress bias effect) that can occur in the first transistor T1 can be reduced.

[0096] WithFigure 3 The differences shown are in Figure 4 In the embodiment shown, the second capacitor Cst2 can be omitted. Figure 3 The second capacitor (Cst2).

[0097] In this embodiment, at least one of the plurality of transistors T1 to T8 includes a semiconductor layer comprising an oxide, while the other transistors include a semiconductor layer comprising silicon. For example, the first transistor T1 may be configured to include a semiconductor layer composed of polycrystalline silicon (e.g., low-temperature polycrystalline silicon (“LTPS”)). At least one of the third transistor T3 and the fourth transistor T4 may include a semiconductor layer composed of an oxide semiconductor.

[0098] The following will be referenced Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A It is shown Figure 3 Zone III or Figure 4 Various examples of the plan view of area IV. Therefore, it will be understood that Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A Each of the structures shown in the diagram is applicable not only to Figure 3 The embodiments shown can also be applied to Figure 4 The structure of the embodiment shown.

[0099] Figure 5A This is an enlarged plan view of a portion of the display device according to an embodiment. Figure 5B It is along Figure 5A The line Vb-Vb' intercepts Figure 5A A cross-sectional view of the display device. As used herein, "plan view" means a view on substrate 100 (reference 100). Figure 2 A view along the thickness direction (z-axis) of a plane.

[0100] Let's refer to each other. Figure 5A and Figure 5B The first transistor T1 may include a first semiconductor pattern AP1 and a first gate electrode G1, and the third transistor T3 may include a third semiconductor pattern AP3, a third-first gate electrode G3a and a third-second gate electrode G3b.

[0101] The first semiconductor pattern AP1 can include a first channel region C1 overlapping the first gate electrode G1 in a plan view, and a first drain region D1 and a first source region S1 disposed on both sides of the first channel region C1 opposite to each other. The first drain region D1 and the first source region S1 can be regions doped with impurities. In some embodiments, the positions of the first drain region D1 and the first source region S1 can be reversed in a different manner from that shown in FIG. 1B. That is, the first drain region D1 and the first source region S1 are interchangeable. In some embodiments, the first semiconductor pattern AP1 can include a low-temperature polysilicon semiconductor, and can be implemented as a PMOS. Figure 5A The first gate electrode G1 can be disposed on the first semiconductor pattern AP1 to overlap the first channel region C1 in a plan view. The first gate electrode G1 can be formed at the same time as a 1-1 capacitor electrode CE1-1 of the first capacitor Cst1 to function as both the first gate electrode G1 and the 1-1 capacitor electrode CE1-1. A 1-2 capacitor electrode CE1-2 of the first capacitor Cst1 can be disposed on the first gate electrode G1 to overlap the first channel region C1 and the first gate electrode G1 in a plan view. In another embodiment, the first gate electrode G1 and the 1-1 capacitor electrode CE1-1 can be formed separately.

[0102] The first gate electrode G1 can be disposed on the first semiconductor pattern AP1 to overlap the first channel region C1 in a plan view. The first gate electrode G1 can be formed at the same time as a 1-1 capacitor electrode CE1-1 of the first capacitor Cst1 to function as both the first gate electrode G1 and the 1-1 capacitor electrode CE1-1. A 1-2 capacitor electrode CE1-2 of the first capacitor Cst1 can be disposed on the first gate electrode G1 to overlap the first channel region C1 and the first gate electrode G1 in a plan view. In another embodiment, the first gate electrode G1 and the 1-1 capacitor electrode CE1-1 can be formed separately.

[0103] The third semiconductor pattern AP3 can include a third channel region C3 overlapping the 3-1 gate electrode G3a and the 3-2 gate electrode G3b in a plan view, and a third drain region D3 and a third source region S3 disposed on both sides of the third channel region C3 opposite to each other. The third drain region D3 and the third source region S3 can be regions doped with impurities. In some embodiments, the positions of the third drain region D3 and the third source region S3 can be reversed in a different manner from that shown in FIG. 1B. That is, the third drain region D3 and the third source region S3 are interchangeable. In some embodiments, the third semiconductor pattern AP3 can include an oxide semiconductor, and can be implemented as an NMOS. Figure 5A The third gate electrode G3a can be disposed on the third semiconductor pattern AP3 to overlap the third channel region C3 in a plan view. The 3-2 gate electrode G3b can be disposed under the third semiconductor pattern AP3 to overlap the third channel region C3.

[0104] The third gate electrode G3a can be disposed on the third semiconductor pattern AP3 to overlap the third channel region C3 in a plan view. The 3-2 gate electrode G3b can be disposed under the third semiconductor pattern AP3 to overlap the third channel region C3.

[0105] The first connection electrode 11 can overlap and be connected to the first source region S1 and the third drain region D3 in a plan view to connect the first source region S1 and the third drain region D3 to each other, thereby connecting the first semiconductor pattern AP1 and the third semiconductor pattern AP3 to each other. The second connection electrode 12 can overlap and be connected to the first gate electrode G1 and the third source region S3 in a plan view to connect the first gate electrode G1 and the third source region S3 to each other, thereby connecting the first gate electrode G1 and the third semiconductor pattern AP3 to each other. In some embodiments, the second connection electrode 12 can be connected to the first gate electrode G1 through an opening defined in the 1-2 capacitor electrode CE1-2. The third connection electrode 13 can be connected to the first drain region D1. Referring to Figure 3 and Figure 4 , the third node N3 can be located on the first connection electrode 11, the second node N2 can be located on the second connection electrode 12, and the third connection electrode 13 can extend toward the first node N1.

[0106] The barrier layer BAR and the first to sixth insulating layers IL1, IL2, IL3, IL4, IL5, and IL6 can be sequentially provided on the substrate 100. The barrier layer BAR and the first to sixth insulating layers IL1, IL2, IL3, IL4, IL5, and IL6 can each include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), and / or silicon oxynitride (SiON).

[0107] The first semiconductor pattern AP1 can be provided on the first insulating layer IL1. A layer on which the first semiconductor pattern AP1 is located can be defined as a first semiconductor layer 101.

[0108] The second insulating layer IL2 can be provided above the first semiconductor layer 101. The first gate electrode G1 can be provided on the second insulating layer IL2 to overlap the first channel region C1 of the first semiconductor pattern AP1 in a plan view. The first semiconductor pattern AP1 and the first gate electrode G1 can be insulated from each other by the second insulating layer IL2. A layer on which the first gate electrode G1 is located can be defined as a first electrode layer 103.

[0109] A third insulating layer IL3 can be disposed on the first electrode layer 103. A first-2 capacitor electrode CE1-2 can be disposed on the third insulating layer IL3. As described above, in some embodiments, the first gate electrode G1 can also serve as a first-1 capacitor electrode CE1-1. The first-1 capacitor electrode CE1-1 and the first-2 capacitor electrode CE1-2 can be included in the first capacitor Cst1. The first-2 capacitor electrode CE1-2 can define an opening in the first-2 capacitor electrode CE1-2 that overlaps the first gate electrode G1 in a plan view.

[0110] A third-2 gate electrode G3b can be disposed on the third insulating layer IL3 to overlap the third channel region C3 of the third semiconductor pattern AP3 in a plan view. The third semiconductor pattern AP3 and the third-2 gate electrode G3b can be insulated from each other by a fourth insulating layer IL4 disposed between the third semiconductor pattern AP3 and the third-2 gate electrode G3b. Layers in which the first-2 capacitor electrode CE1-2 and the third-2 gate electrode G3b are disposed can be defined as a second electrode layer 105. In some embodiments, the first-2 capacitor electrode CE1-2 and the third-2 gate electrode G3b can be formed during the same process.

[0111] A fourth insulating layer IL4 can be disposed on the second electrode layer 105. A third semiconductor pattern AP3 can be separate from the first semiconductor pattern AP1 and disposed on the fourth insulating layer IL4. Layers in which the third semiconductor pattern AP3 is disposed can be defined as a second semiconductor layer 107.

[0112] A fifth insulating layer IL5 can be disposed on the second semiconductor layer 107. A third-1 gate electrode G3a can be disposed on the fifth insulating layer IL5 to overlap the third channel region C3 of the third semiconductor pattern AP3 in a plan view. The third semiconductor pattern AP3 and the third-1 gate electrode G3a can be insulated from each other by the fifth insulating layer IL5. Layers in which the third-1 gate electrode G3a is disposed can be defined as a third electrode layer 109.

[0113] The first connection electrode 11 can be disposed on the fifth insulating layer IL5 and can be connected to the first source region S1 of the first semiconductor pattern API and the third drain region D3 of the third semiconductor pattern AP3. The first connection electrode 11 can overlap the first source region S1 in a plan view and be connected to the first source region S1 through a first opening defined in the second through fifth insulating layers IL2, IL3, IL4, and IL5. The first connection electrode 11 can overlap the third drain region D3 in a plan view and be connected to the third drain region D3 through a second opening defined in the fifth insulating layer IL5. The first and second openings can be formed during the same process, or can be formed during different processes. In some embodiments, when the first and second openings are formed during the same process, a buffer oxide etch (“BOE”) process can be used to remove inorganic material remaining in the first opening after the first and second openings are formed through an etching process. In this regard, the second opening can be covered with a photoresist to protect an upper surface of the third semiconductor pattern AP3 exposed by the second opening (e.g., an upper surface of the third drain region D3). The second opening can be opened again by removing the photoresist after the BOE process is performed. In some embodiments, the first connection electrode 11 can be disposed in the same layer as the 3-1st gate electrode G3a. That is, the first connection electrode 11 can be located in the third electrode layer 109. In some embodiments, the first connection electrode 11 and the 3-1st gate electrode G3a can be formed during the same process.

[0114] A sixth insulating layer IL6 can be provided over the third electrode layer 109. The second connection electrode 12 and the third connection electrode 13 can be provided on the sixth insulating layer IL6. The second connection electrode 12 can be connected to the first gate electrode G1 and the third source region S3. The second connection electrode 12 can overlap the first gate electrode G1 in a plan view and be connected to the first gate electrode G1 through an opening defined in the third to sixth insulating layers IL3, IL4, IL5, and IL6. The second connection electrode 12 can overlap the third source region S3 in a plan view and be connected to the third source region S3 through an opening defined in the fifth insulating layer IL5 and the sixth insulating layer IL6. The third connection electrode 13 can overlap the first drain region D1 in a plan view and be connected to the first drain region D1 through an opening defined in the second to sixth insulating layers IL2, IL3, IL4, IL5, and IL6. The layer on which the second connection electrode 12 and the third connection electrode 13 are provided can be defined as a fourth electrode layer 111. In some embodiments, the second connection electrode 12 and the third connection electrode 13 can be formed during the same process. As used herein, when the position of the first connection electrode 11, the second connection electrode 12, or the third connection electrode 13 in a multilayer structure is described, it is considered that the position of the “main plate portion” of the connection electrode is described. For example, although the first connection electrode 11 includes a main plate portion parallel to a plane defined by an x-axis and a y-axis, a first vertical portion extending in a z-axis direction from the main plate portion to the first semiconductor pattern AP1, and a second vertical portion extending in the z-axis direction from the main plate portion to the third semiconductor pattern AP3, when it is said that the first connection electrode 11 is arranged in the third electrode layer 109, it means that the main plate portion of the first connection electrode 11 is arranged in the third electrode layer 109.

[0115] Figure 6A is a plan view of a part of a display device according to another embodiment. Figure 6B is a cross-sectional view of the display device of Figure 6A taken along the line VIb-VIb’ of Figure 6A

[0116] Referring to Figure 6A and Figure 6B together, the second connection electrode 12 can be provided on a layer different from the layer in the embodiment shown in Figure 5A and Figure 5B

[0117] ​​The second connection electrode 12 can be provided on the fifth insulating layer IL5. For example, the second connection electrode 12 can be provided between the fifth insulating layer IL5 and the sixth insulating layer IL6. The second connection electrode 12 can be arranged in the same layer as the first connection electrode 11 and the 3-1 gate electrode G3a. In other words, the first connection electrode 11, the second connection electrode 12, and the 3-1 gate electrode G3a can be located in the third electrode layer 109. In some embodiments, the first connection electrode 11, the second connection electrode 12, and the 3-1 gate electrode G3a can be formed during the same process.

[0118] The second connection electrode 12 can overlap the first gate electrode G1 in a plan view and be connected to the first gate electrode G1 through an opening defined in the third to fifth insulating layers IL3, IL4, and IL5. The second connection electrode 12 can overlap the third source region S3 in a plan view and be connected to the third source region S3 through an opening defined in the fifth insulating layer IL5.

[0119] Figure 7A is a plan view of a part of a display device according to yet another embodiment. Figure 7B is a cross-sectional view of the display device of Figure 7A taken along the line VIIb-VIIb’ of Figure 7A

[0120] Reference is made together with Figure 7A and Figure 7B , with Figure 5A and Figure 5B , the second electrode layer 105 (cf. Fig. 1) can be omitted, which is different from the embodiments shown in Figure 5B .

[0121] The 3-2 gate electrode G3b can be provided on the second insulating layer IL2. For example, the 3-2 gate electrode G3b can be provided between the second insulating layer IL2 and the third insulating layer IL3. The 3-2 gate electrode G3b can be arranged in the same layer as the first gate electrode G1. In other words, the 3-2 gate electrode G3b and the first gate electrode G1 can be located in the first electrode layer 103. In some embodiments, the 3-2 gate electrode G3b and the first gate electrode G1 can be formed during the same process.

[0122] ​The first-second capacitor electrode CE1-2 can be disposed on the fifth insulating layer IL5. For example, the first-second capacitor electrode CE1-2 can be disposed between the fifth insulating layer IL5 and the sixth insulating layer IL6. The first-second capacitor electrode CE1-2 can be disposed in the same layer as the first connecting electrode 11 and the third-first gate electrode G3a. In other words, the first-second capacitor electrode CE1-2, the first connecting electrode 11, and the third-first gate electrode G3a can be located in the third electrode layer 109. In some embodiments, the first-second capacitor electrode CE1-2, the first connecting electrode 11, and the third-first gate electrode G3a can be formed during the same process.

[0123] In some embodiments, a separate electrode layer may not be provided between the third insulating layer IL3 and the fourth insulating layer IL4. In other words, Figure 5B The second electrode layer 105 shown (reference) Figure 5B The first electrode layer 109, where the first-2 capacitor electrodes CE1-2, the first connection electrode 11, and the third-1 gate electrode G3a are located, can be understood as a "basically second" electrode layer. In another embodiment, the fourth insulating layer IL4 can be omitted, and the third semiconductor pattern AP3 can be disposed on the third insulating layer IL3.

[0124] Figure 8A This is an enlarged plan view of a portion of a display device according to another embodiment. Figure 8B It is along Figure 8A The line VIIIb-VIIIb' intercepted Figure 8A A cross-sectional view of the display device.

[0125] Let's refer to each other. Figure 8A and Figure 8B Other characteristics and Figure 7A and Figure 7B The embodiments shown have the same features, but the layers in which the first and second capacitor electrodes CE1-2 are disposed may be different.

[0126] The first and second capacitor electrodes CE1-2 can be disposed on the fourth insulating layer IL4. For example, the first and second capacitor electrodes CE1-2 can be disposed between the fourth insulating layer IL4 and the fifth insulating layer IL5. The first and second capacitor electrodes CE1-2 can be disposed in the same layer as the third semiconductor pattern AP3. In other words, the first and second capacitor electrodes CE1-2 and the third semiconductor pattern AP3 can be located in the second semiconductor layer 107. In some embodiments, the first and second capacitor electrodes CE1-2 can comprise an oxide semiconductor in a manner similar to that of the third semiconductor pattern AP3. In some embodiments, the first and second capacitor electrodes CE1-2 can be formed during the same process as the third semiconductor pattern AP3.

[0127] Figure 9A is a plan view of a portion of a display device according to yet another embodiment. Figure 9B is a cross-sectional view of the display device of Figure 9A taken along line IXb-IXb’ of Figure 9A

[0128] Referring to Figure 9A and Figure 9B together, the second connection electrode 12 can be provided on a different layer than the layers in the embodiments shown in Figure 7A and Figure 7B

[0129] The second connection electrode 12 can be provided on the fifth insulating layer IL5. For example, the second connection electrode 12 can be provided between the fifth insulating layer IL5 and the sixth insulating layer IL6. The second connection electrode 12 can be arranged in the same layer as the 1-2 capacitor electrode CE1-2, the first connection electrode 11, and the 3-1 gate electrode G3a. In other words, the first connection electrode 11, the second connection electrode 12, the 1-2 capacitor electrode CE1-2, and the 3-1 gate electrode G3a can be located in the third electrode layer 109. In some embodiments, the first connection electrode 11, the second connection electrode 12, the 1-2 capacitor electrode CE1-2, and the 3-1 gate electrode G3a can be formed during the same process.

[0130] The second connection electrode 12 can overlap the first gate electrode G1 in plan view and be connected to the first gate electrode G1 through an opening defined in the third to fifth insulating layers IL3, IL4, and IL5. The second connection electrode 12 can overlap the third source region S3 in plan view and be connected to the third source region S3 through an opening defined in the fifth insulating layer IL5.

[0131] In some embodiments, as shown in Figure 9A , the 1-2 capacitor electrode CE1-2 can be separate from the second connection electrode 12. The 1-2 capacitor electrode CE1-2 can be located in the same layer as the second connection electrode 12 and can also overlap the first gate electrode G1 (or the 1-1 capacitor electrode CE1-1) in plan view. The 1-2 capacitor electrode CE1-2 can substantially take the shape of a frame having an opening in one direction and thus can partially surround a portion of the second connection electrode 12 that overlaps the first gate electrode G1 in plan view.

[0132] Figure 10A is a plan view of a portion of a display device according to yet another embodiment. Figure 10B is a cross-sectional view of the display device of Figure 10A taken along line Xb-Xb’ of Figure 10A ​​​

[0133] Reference is made together with Figure 10A and Figure 10B the features of the embodiments shown in Figure 9A and Figure 9B may be different from the shape of the 1-2 capacitor electrodes CE1-2 and the layer in which the 1-2 capacitor electrodes CE1-2 are provided.

[0134] The 1-2 capacitor electrodes CE1-2 can be provided over the fourth insulating layer IL4. For example, the 1-2 capacitor electrodes CE1-2 can be provided between the fourth insulating layer IL4 and the fifth insulating layer IL5. The 1-2 capacitor electrodes CE1-2 can be arranged in the same layer as the third semiconductor pattern AP3. In other words, the 1-2 capacitor electrodes CE1-2 and the third semiconductor pattern AP3 can be located in the second semiconductor layer 107. In some embodiments, the 1-2 capacitor electrodes CE1-2 can include an oxide semiconductor in a similar manner as the third semiconductor pattern AP3. In some embodiments, the 1-2 capacitor electrodes CE1-2 can be formed during the same process as the third semiconductor pattern AP3.

[0135] The 1-2 capacitor electrodes CE1-2 can be arranged in a different layer, e.g., in the second semiconductor layer 107, compared to the second connection electrode 12, and thus, unlike the embodiments shown in Figure 9A the 1-2 capacitor electrodes CE1-2 can take the shape of a complete frame without an open side.

[0136] Figure 11A is an enlarged plan view of part of a display device according to yet another embodiment. Figure 11B is a cross-sectional view of the display device of Figure 11A taken along the line XIb-XIb’. Figure 11A

[0137] Reference is made together with Figure 11A and Figure 11B both the first semiconductor pattern AP1 and the third semiconductor pattern AP3 can be provided over the first insulating layer IL1. Thus, both the first semiconductor layer 101 and the second semiconductor layer 107 can be located over the first insulating layer IL1, i.e., in the same layer.

[0138] ​The second insulating layer IL2 can be provided over the first semiconductor layer 101 and the second semiconductor layer 107. The first gate electrode G1, the 3-1 gate electrode G3a, the first connection electrode 11, and the second connection electrode 12 can be provided on the second insulating layer IL2. The first gate electrode G1, the 3-1 gate electrode G3a, the first connection electrode 11, and the second connection electrode 12 can be arranged in the same layer. For example, the first gate electrode G1, the 3-1 gate electrode G3a, the first connection electrode 11, and the second connection electrode 12 can be located in the first electrode layer 103. In some embodiments, the first gate electrode G1, the 3-1 gate electrode G3a, the first connection electrode 11, and the second connection electrode 12 can be formed during the same process.

[0139] The first gate electrode G1 and the first semiconductor pattern AP1 can be insulated by the second insulating layer IL2. The first gate electrode G1 can overlap the first channel region C1 of the first semiconductor pattern AP1 in a plan view. The 3-1 gate electrode G3a and the third semiconductor pattern AP3 can be insulated by the second insulating layer IL2. The 3-2 gate electrode G3b can be provided under the third semiconductor pattern AP3. In some embodiments, the 3-2 gate electrode G3b can be provided between the barrier layer BAR and the first insulating layer IL1. The 3-2 gate electrode G3b and the third semiconductor pattern AP3 can be insulated by the first insulating layer IL1. The 3-1 gate electrode G3a and the 3-2 gate electrode G3b can overlap the third channel region C3 of the third semiconductor pattern AP3 in a plan view.

[0140] The first connection electrode 11 can be connected to the first source region S1 of the first semiconductor pattern AP1 and the third drain region D3 of the third semiconductor pattern AP3. The first connection electrode 11 can overlap the first source region S1 in a plan view and be connected to the first source region S1 through a first opening defined in the second insulating layer IL2. The first connection electrode 11 can overlap the third drain region D3 in a plan view and be connected to the third drain region D3 through a second opening defined in the second insulating layer IL2.

[0141] The second connection electrode 12 can be connected to the third source region S3 of the third semiconductor pattern AP3. The second connection electrode 12 can overlap the third source region S3 in a plan view and be connected to the third source region S3 through an opening defined in the second insulating layer IL2. As Figure 11B The second connection electrode 12 can be integrally formed with the first gate electrode G1 as shown in FIG. 1B. Thus, the first gate electrode G1 can serve as the 1-1 capacitor electrode CE1-1 and can serve as a part of the second connection electrode 12. The first gate electrode G1 and the third source region S3 can be connected to each other through the second connection electrode 12.

[0142] A third insulating layer IL3 can be provided over the first electrode layer 103. The 1-2 capacitor electrode CE1-2 can be provided on the third insulating layer IL3. The 1-2 capacitor electrode CE1-2 can be located in the second electrode layer 105.

[0143] A fourth to sixth insulating layer IL4, IL5 and IL6 can be sequentially provided over the second electrode layer 105. The third connection electrode 13 can overlap the first drain region D1 in a plan view and can be provided on the sixth insulating layer IL6. The third connection electrode 13 can be connected to the first drain region D1 through an opening defined in the second to sixth insulating layers IL2, IL3, IL4, IL5 and IL6. In another embodiment, the fifth insulating layer IL5 and the sixth insulating layer IL6 can be omitted, and the third connection electrode 13 can be provided on the fourth insulating layer IL4. The third connection electrode 13 can be located in the fourth electrode layer 111. However, unlike the embodiment shown in Figure 5B , the third electrode layer 109 (refer to Figure 5B ) is omitted in the embodiment shown in Figure 11B . Thus, the fourth electrode layer 111 can be understood as a “substantially third” electrode layer.

[0144] Figure 12A is an enlarged plan view schematically showing a part of the display device according to an embodiment. Figure 12B is a cross-sectional view of the display device of Figure 12A taken along the line XIIb-XIIb’ thereof. Figure 12A is a cross-sectional view of the display device of Figure 12C taken along the line XIIc-XIIc’ thereof. Figure 12A is a cross-sectional view of the display device of Figure 12A taken along the line XIIc-XIIc’ thereof.

[0145] In some embodiments, Figure 12A may be an enlarged plan view of the region M of Figure 5B but one or more embodiments are not limited thereto. Features of one or more embodiments described below with reference to Figures 12A to 14 may also be similarly applied to Figures 6A to 11B . Thus, it should be understood that the following description can generally apply to the connection relationship between the third drain region D3 of the third semiconductor pattern AP3 and the first connection electrode 11 and / or the connection relationship between the third source region S3 and the second connection electrode 12.

[0146] With reference to Figure 12A , the first connection electrode 11 can be connected to the third semiconductor pattern AP3 through an opening or a contact hole CNT defined in the fifth insulating layer IL5.

[0147] The first connection electrode 11 can overlap the contact hole CNT in a plan view. The fifth insulating layer IL5 can include a plurality of protrusions IL5-EX protruding toward the contact hole CNT. Due to the protrusions IL5-EX, the contact hole CNT can have a shape of a bent puzzle piece in a plan view. A portion of the first connection electrode 11 can overlap the protrusions IL5-EX in a plan view. A portion of the contact hole CNT can overlap the first connection electrode 11 in a plan view, and another portion of the contact hole CNT can not overlap the first connection electrode 11 in a plan view. For example, the contact hole CNT can include a first region R1 overlapping the first connection electrode 11 in a plan view and a second region R2 not overlapping the first connection electrode 11 in a plan view. The first region R1 can be understood as a portion of the contact hole CNT filled by the first connection electrode 11 when the first connection electrode 11 is disposed therein. On the other hand, the second region R2 can be understood as a portion of the contact hole CNT not filled by the first connection electrode 11 when the first connection electrode 11 is not disposed therein and a portion of an upper surface of the third semiconductor pattern AP3 is exposed therein during at least a portion of the process. As a result, the contact hole CNT can include an open region (e.g., the second region R2) not covered by the first connection electrode 11.

[0148] Referring to Figure 12B In the first region R1, the contact hole CNT can be filled by the first connection electrode 11. The first connection electrode 11 can fill the contact hole CNT in the first region R1 and can be in direct contact with the upper surface of the third semiconductor pattern AP3.

[0149] The first connection electrode 11 can be in direct contact with and cover a side surface of the protrusion IL5-EX of the fifth insulating layer IL5 facing the contact hole CNT. In addition, the first connection electrode 11 can be in direct contact with and cover a portion of the upper surface of the fifth insulating layer IL5 (e.g., a portion of the upper surface of the protrusion IL5-EX). The sixth insulating layer IL6 can cover the fifth insulating layer IL5 and the first connection electrode 11.

[0150] Referring to Figure 12C The contact hole CNT can include a first region R1 in which the first connection electrode 11 is disposed and a second region R2 in which the first connection electrode 11 is not disposed.

[0151] In the first region R1, the first connection electrode 11 and the third semiconductor pattern AP3 can directly contact each other. Due to the second region R2, a part of the side surface of the first connection electrode 11 can be separated from the side surface of the fifth insulating layer IL5. The second region R2 in which the first connection electrode 11 and the fifth insulating layer IL5 are separated from each other can be filled with the sixth insulating layer IL6. Thus, in the second region R2, the sixth insulating layer IL6 and the third semiconductor pattern AP3 can directly contact each other.

[0152] Implementation Figures 12A to 12C The process of the embodiment shown in FIG. 10 can be performed in the following order. First, the contact hole CNT can be formed by etching the fifth insulating layer IL5 disposed on the third semiconductor pattern AP3. Next, the first connection electrode 11 can be placed. Next, a part of the third semiconductor pattern AP3 can be doped with impurities (dopants) by injecting dopants through the contact hole CNT. Next, the fifth insulating layer IL5 and the first connection electrode 11 can be covered by placing the sixth insulating layer IL6. In the above process, when the first connection electrode 11 completely covers the contact hole CNT, there can be no path for the dopants to reach the third semiconductor pattern AP3. According to the embodiment, because the second region R2 of the contact hole CNT is not covered by the first connection electrode 11, a part of the upper surface of the third semiconductor pattern AP3 can be exposed in the second region R2 until the sixth insulating layer IL6 is placed. Thus, a part of the third semiconductor pattern AP3 can be doped by injecting dopants through the second region R2. The doped part of the third semiconductor pattern AP3 is denoted as DP in FIG. 10. Figure 12C

[0153] The part of the third semiconductor pattern AP3 doped through the second region R2 can be understood as a buffer region BR of the third semiconductor pattern AP3. The buffer region BR can overlap the second region R2 in a plan view. Because the buffer region BR is a doped region and can have electrical conductivity, the buffer region BR can electrically connect a part of the third semiconductor pattern AP3 not directly contacting the first connection electrode 11 to the first connection electrode 11. In the embodiment, the part of the third semiconductor pattern AP3 not overlapping the contact hole CNT in a plan view can be electrically connected to the first connection electrode 11 through the buffer region BR. For example, referring to FIGS. 9 and 10 together, Figure 12A and Figure 12B , the part of the third semiconductor pattern AP3 under the protrusion IL5-EX of the fifth insulating layer IL5 can be electrically connected to the first connection electrode 11 through the buffer region BR.

[0154] Figure 13 is an enlarged plan view schematically showing a part of a display device according to another embodiment.

[0155] Reference Figure 13 ​The contact hole CNT can have a substantially square or rectangular shape. The first connection electrode 11 can have a substantially cross shape, and can include a protrusion 11-EX protruding toward the fifth insulating layer IL5. At least a portion of the protrusion 11-EX of the first connection electrode 11 can overlap with the fifth insulating layer IL5. The first region R1 of the contact hole CNT can overlap with the first connection electrode 11 in a plan view, and the second region R2 can not overlap with the first connection electrode 11 in a plan view.

[0156] Figure 14 FIG. 1 is a plan view schematically showing a portion of a display device according to an embodiment of the present disclosure.

[0157] Reference will now be made to Figure 14 The contact hole CNT and the first connection electrode 11 can both have a substantially rectangular shape. The first connection electrode 11 can overlap with only a portion of the contact hole CNT (e.g., a left portion of the contact hole CNT) in a plan view, and the overlapping region can be regarded as the first region R1. The remaining portion (e.g., a right portion of the contact hole CNT) can not overlap with the first connection electrode 11 in a plan view, and the corresponding region can be regarded as the second region R2.

[0158] However, the present disclosure is not limited to the embodiments shown in Figure 12A , Figure 13 and Figure 14 , and any structure in which the first connection electrode 11 covers only a portion of the contact hole CNT can be included in the present disclosure, regardless of the shapes of the first connection electrode 11 and the contact hole CNT.

[0159] According to one or more of the above embodiments, a display device in which high integration of a circuit can be achieved by placing a first connection electrode and a gate electrode of a transistor including an oxide semiconductor in the same layer, the first connection electrode and a second connection electrode connecting a transistor including a silicon semiconductor and a transistor including an oxide semiconductor to each other can be provided. However, one or more embodiments are not limited thereto.

[0160] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope as defined by the following claims.

Claims

1. A display device comprising: a substrate over which a display element is disposed; a first transistor disposed over the substrate and including a first semiconductor pattern including a silicon semiconductor; a second transistor disposed over the substrate and including a second semiconductor pattern including an oxide semiconductor and a second-1 gate electrode insulated from and disposed over the second semiconductor pattern; and a first connection electrode connecting the first semiconductor pattern and the second semiconductor pattern to each other, wherein the first connection electrode and the second-1 gate electrode are disposed in the same layer.

2. The display device according to claim 1, further comprising: a first gate electrode insulated from and disposed over the first semiconductor pattern.

3. The display device according to claim 2, further comprising: a second connection electrode connecting the first gate electrode and the second semiconductor pattern to each other. The second connection electrode and the first connection electrode are disposed in the same layer.

4. The display device according to claim 3, wherein 5. The display device according to claim 2, further comprising: a second-2 gate electrode insulated from and disposed under the second semiconductor pattern.

6. The display device according to claim 2, further comprising: a capacitor electrode insulated from and disposed over the first gate electrode, wherein the first connection electrode and the capacitor electrode are disposed in the same layer. The first gate electrode and the second-2 gate electrode are disposed in the same layer.

7. The display device according to claim 5, wherein The first semiconductor pattern and the second semiconductor pattern are disposed in the same layer.

8. The display device according to claim 1, wherein The first connection electrode is connected to the second semiconductor pattern through a contact hole defined in an insulating layer disposed between the first connection electrode and the second semiconductor pattern, 9. The display device according to any one of claims 1 to 8, wherein, wherein the contact hole includes a first region overlapping with the first connection electrode and a second region not overlapping with the first connection electrode in a plan view.

10. A display device comprising: a substrate; a first transistor disposed over the substrate and including a first semiconductor pattern including a silicon semiconductor and a first gate electrode insulated from and disposed over the first semiconductor pattern, wherein the first semiconductor pattern includes a first channel region overlapping with the first gate electrode and first source and drain regions provided on both sides of the first channel region opposite to each other; a second transistor disposed over the substrate, including a second semiconductor pattern including an oxide semiconductor and a second-1 gate electrode insulated from and disposed over the second semiconductor pattern, and electrically connected to the first transistor, wherein the second semiconductor pattern includes a second channel region overlapping with the second-1 gate electrode and second source and drain regions provided on both sides of the second channel region opposite to each other; a first connection electrode connected to one of the first source region and the first drain region of the first semiconductor pattern; a second connection electrode connected to one of the second source region and the second drain region of the second semiconductor pattern; and ​ an insulating layer arranged between the first connection electrode and the second connection electrode, wherein the second connection electrode is arranged under the insulating layer and the first connection electrode is arranged on the insulating layer.

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