Multi-chip high-density packaging structure
By designing the substrate and interconnect bridges, high-density multi-chip packaging was achieved, solving the problems of complex packaging and high cost in existing technologies, and achieving the effect of high-density packaging and low cost.
Patent Information
- Application Number
- CN202520141155.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2035-01-21
AI Technical Summary
Existing 2.5D and 3D packaging processes are complex and costly, limiting the widespread application of multi-chip high-density packaging, especially for high-value products, which urgently require low-cost multi-chip high-density interconnect solutions.
The chip adopts a substrate and interconnect bridge structure, with interconnect lines integrated in the substrate and micro-solder pillars densely arranged on the interconnect bridge. It is connected to the substrate through an adhesive layer to achieve high-density lateral interconnection between the chip and the interconnect bridge. Combined with mature manufacturing process, it reduces technical difficulty and cost.
It achieves high-density chip packaging, improves packaging density and bandwidth, and combines the advantages of high transmission speed of 2.5D packaging and low cost of 2.2D packaging. The process is simple and low-cost.
Smart Images
Figure CN223912865U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to microelectronic chip packaging technical field, especially a kind of multi-chip high-density packaging structure. BACKGROUND
[0002] Shortening the interconnection pitch between chips is one of the key goals of modern integrated circuit development, the core is through process, design and equipment iteration, constantly reduce the interconnection pitch between chips and increase the interconnection bandwidth between chips to improve performance. With the industry's unlimited pursuit of computing power and performance, drive chip packaging develops from 2D to 2.xD and 3D integration, its typical feature is multi-chip high-density interconnection, such as 2.5D packaging through interlayer interconnection, compared with conventional substrate level interconnection, the interconnection pitch between GPU / CPU and I / O, HBM chip is shortened, and 3D packaging further adopts through silicon via to realize chip vertical stacking, the shortest interconnection pitch between chips and the optimal product performance are obtained, which can effectively improve performance and reduce power consumption while improving chip integration, so that the system has more excellent electrical and thermal characteristics.
[0003] But currently 2.5D and 3D packaging process is complex, design cycle is long and difficult, equipment requirement is high, cost is high, only HPC, GPU, Al and other high-value products are adopted, Intel's 2.3D EMIB packaging technology embeds silicon interconnection bridge in substrate, although the packaging difficulty is reduced, but the manufacturing difficulty of substrate is increased, the cost improvement is not obvious, IBM's technology also has similar problems in large-area hole opening on substrate, which limits its larger-scale application. For large-scale, low-cost application scenarios of high-density chip packaging, it is urgent to propose a lower-cost multi-chip high-density interconnection scheme based on existing mature process. UTILITY MODEL CONTENT
[0004] The utility model aims at the deficiency in the above background art, provide a kind of multi-chip high-density interconnection scheme with lower cost.
[0005] In order to achieve the above purpose, the utility model provides a kind of multi-chip high-density packaging structure, including substrate, chip and interconnection bridge.
[0006] The substrate is integrally provided with interconnection circuit, and the substrate is provided with a plurality of solder balls.
[0007] The interconnection bridge is densely provided with a plurality of micro solder columns, and the interconnection bridge is integrally provided with high-density fine-pitch circuit in transverse interconnection, and the line width / line spacing is less than the line width / line spacing of the substrate.
[0008] The solder joint on the chip includes a regular solder joint and a micro solder joint, the regular solder joint is bonded with the solder ball, and the micro solder joint is bonded with the micro solder column.
[0009] Further, the interconnection bridge is fixedly connected with the substrate.
[0010] Further, the interconnection bridge is connected with the substrate through an adhesive layer.
[0011] Further, the material of the interconnection bridge is silicon or glass or organic film.
[0012] Further, the material of the adhesive layer is glue or solder paste.
[0013] Further, the thickness of the interconnection bridge is set such that, after the interconnection bridge is fixed with the substrate through the adhesive layer, the chip can be horizontally packaged, and the normal solder joint and the micro solder joint can be respectively bonded with the solder ball and the micro solder column.
[0014] Further, the bonding position between the chip and the substrate and the interconnection bridge is protected by filling glue.
[0015] Further, the chip is any chip suitable for packaging, and the number of the chip is two or more.
[0016] The above scheme of the utility model has the following beneficial effects:
[0017] The multi-chip high-density packaging structure provided by the utility model realizes high-density horizontal interconnection of multiple adjacent chips through an interconnection bridge, has the characteristics of mature technology and low technical difficulty, and the interconnection bridge and the substrate are manufactured based on mature technology without increasing additional process links, and meanwhile, the packaging density and bandwidth of the chip can be significantly improved, and the advantages of fast transmission speed of 2.5D packaging technology and low cost of 2.2D packaging technology are comprehensively combined.
[0018] Other beneficial effects of the utility model will be described in detail in the following specific embodiment part. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figure 1 It is a whole structure schematic view of embodiment 1 of the utility model;
[0020] Figure 2 It is a process route S1 schematic view of embodiment 1 of the utility model;
[0021] Figure 3 It is a process route S2 schematic view of embodiment 1 of the utility model;
[0022] Figure 4 It is a process route S3 schematic view of embodiment 1 of the utility model;
[0023] Figure 5 It is a whole structure schematic view of embodiment 2 of the utility model.
[0024]
Explanation of reference signs
[0025] 1 - substrate; 2 - first chip; 3 - second chip; 4 - interconnection bridge; 5 - solder ball; 6 - micro solder column; 7 - adhesive layer; 8 - underfill adhesive; 9 - third chip; 10 - fourth chip. DETAILED DESCRIPTION
[0026] To make the technical problems, technical schemes and advantages to be solved by the present application clearer, the following will be described in detail in conjunction with the drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of the present application. In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as there is no conflict.
[0027] In the description of the present application, it should be pointed out that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.
[0028] In the description of the present application, it should be pointed out that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be a locking connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or the communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0029] Embodiment 1:
[0030] As Figure 1As shown, an embodiment of this utility model provides a multi-chip high-density packaging structure for 2.2D chip packaging, including a substrate 1, a first chip 2, a second chip 3, and an interconnect bridge 4. The substrate 1 integrates interconnect lines and has multiple solder balls 5. The first chip 2 and the second chip 3 are both bonded to the substrate 1 via the solder balls 5. Specifically, in this embodiment, the solder joints on the first chip 2 and the second chip 3 include conventional solder joints and micro solder joints. The conventional solder joints correspond to the solder balls 5 on the substrate 1, while the micro solder joints correspond to the micro solder pillars 6 on the interconnect bridge 4.
[0031] In this embodiment, the interconnect bridge 4 is used to connect adjacent first chips 2 and second chips 3, or to connect multiple adjacent chips. The interconnect bridge 4 is densely covered with multiple micro-solder pillars 6, which are relatively small in size and spacing. Simultaneously, the interconnect bridge 4 integrates high-density, fine-pitch lateral interconnects, with linewidth / spacing typically smaller than that of the substrate 1 (commonly 10 / 10μm). Therefore, compared to interconnecting chips within the substrate 1, the interconnect bridge 4 allows for lateral interconnection of two chips, achieving higher integration through high-density, fine-pitch lines. Of course, for chips that do not require high-density interconnection, the interconnect lines within the substrate 1 can be used directly.
[0032] It should be noted that in this embodiment, the interconnect bridge 4 can be made of silicon, glass, or organic film (such as polyimide, ABF, etc.). The bottom surface of the interconnect bridge 4 is connected to the substrate 1 through an adhesive layer 7, which can be made of glue, solder paste, etc. The adhesive layer 7 serves to connect and fix the interconnect bridge 4, ensuring it is firmly encapsulated on the substrate 1. Simultaneously, the material of the adhesive layer 7 effectively buffers internal stress caused by packaging deformation, further improving the quality of multi-chip packaging. It is worth mentioning that in this embodiment, the high-density fine-pitch lines in the interconnect bridge 4 are not directly connected to the interconnect lines in the substrate 1. The method of bonding the interconnect bridge 4 to the substrate 1 through the adhesive layer 7 combines the advantages of the high transmission speed of 2.5D packaging technology and the low cost of 2.2D packaging technology.
[0033] The process route for the multi-chip high-density packaging structure provided in this embodiment is as follows:
[0034] S1, as Figure 2 As shown, the interconnect bridge 4 is encapsulated with the substrate 1, and the interconnect bridge 4 and the substrate 1 are fixedly connected by the adhesive layer 7 (adhesive).
[0035] S2, as Figure 3As shown, the first chip 2 and the second chip 3 are simultaneously bonded with the interconnection bridge 4 and the substrate 1 through thermal compression bonding or a reflow process, vertical interconnection of the first chip 2, the second chip 3 and the substrate 1 is realized, and horizontal interconnection of the first chip 2 and the second chip 3 is realized.
[0036] S3, as shown in the figure, the bonding position between the chip and the substrate 1 and the interconnection bridge 4 is filled and protected by the underfilling glue 8. Figure 4
[0037] As can be seen, the thickness of the interconnection bridge 4 needs to be set reasonably, so that after the interconnection bridge 4 is fixed with the substrate 1 through the adhesive layer 7, the first chip 2 and the second chip 3 can be horizontally packaged, and the conventional solder joints and the micro solder joints can be accurately bonded with the solder balls 5 and the micro solder columns 6 respectively.
[0038] As described above, the multi-chip high-density packaging structure provided by the embodiment has the characteristics of mature process and low technical difficulty, the interconnection bridge 4 and the substrate 1 are manufactured based on mature process, and no additional process links are added, and at the same time, the packaging density and bandwidth of the chip can be significantly improved, and the advantages of fast transmission speed of 2.5D packaging technology and low cost of 2.2D packaging technology are combined.
[0039] Embodiment 2:
[0040] The embodiment 2 of the utility model provides another multi-chip high-density packaging structure, and the main difference from the embodiment 1 is that four chips are directly connected through an interconnection bridge 4, as shown in the figure. Figure 5
[0041] Among them, the chip includes the first chip 2, the second chip 3, the third chip 9 and the fourth chip 10, four chips are located at four diagonal positions in a square area, and the interconnection bridge 4 is arranged at the center position of the square area. Each chip is bonded with the micro solder column 6 at the diagonal position of the interconnection bridge 4 through the micro solder joint. Therefore, the horizontal interconnection between the four chips is completed through an interconnection bridge 4, and the packaging density and bandwidth are further improved.
[0042] Of course, in other embodiments, more chips can also be connected through an interconnection bridge 4, for example, 2x3, etc.
[0043] It should be noted that the chips in the embodiment 1 and the embodiment 2 are any chip suitable for packaging, which can be multiple same type chips or multiple different type chips, for example, I / O, HBM chip, which is not limited in the embodiment. Based on the requirements of packaging efficiency, packaging size, etc., multiple chips will be generally packaged. In combination of the embodiment 1 and the embodiment 2, the multi-chip high-density packaging structure provided by the embodiment can realize high-density horizontal interconnection of chips in various arrangement forms, and is flexible in application.
[0044] Any technical features in the above embodiments can be combined, and for the sake of brevity, not all possible combinations are described above, however, any combination of these technical features is considered to be within the scope of the present disclosure.
[0045] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.
Claims
1. A multi-chip high-density package structure, characterized by comprising: The substrate, the chip and the interconnection bridge are included; The interconnection line is integrated in the substrate, and the substrate is provided with a plurality of solder balls; A plurality of micro solder columns are densely arranged on the interconnection bridge, and high-density fine-pitch lines are integrated in the interconnection bridge and are transversely interconnected, and the line width / line spacing is smaller than that of the substrate; The solder points on the chip include conventional solder points and micro solder points, the conventional solder points are bonded with the solder balls, and the micro solder points are bonded with the micro solder columns.
2. The multi-chip high-density package structure of claim 1, wherein, The interconnection bridge is fixedly connected with the substrate.
3. The multi-chip high-density package structure of claim 2, wherein, The interconnection bridge is connected with the substrate through an adhesive layer.
4. The multi-chip high-density package structure of claim 3, wherein, The material of the interconnection bridge is silicon or glass or an organic film.
5. The multi-chip high-density package structure of claim 3, wherein, The material of the adhesive layer is glue or solder paste.
6. The multi-chip high-density package structure of claim 3, wherein, The thickness of the interconnection bridge is set such that, after the interconnection bridge is fixed with the substrate through the adhesive layer, the chip can be horizontally packaged, and the conventional solder points and the micro solder points can be bonded with the solder balls and the micro solder columns respectively.
7. The multi-chip high-density package structure of claim 1, wherein, The bonding positions between the chip and the substrate and the interconnection bridge are protected by filling glue.
8. A multi-chip high-density package structure according to any one of claims 1-7, wherein, The chip is any chip suitable for packaging, and the number of the chip is two or more.