Semiconductor epitaxy and semiconductor structure

Abstract

The utility model discloses a semiconductor epitaxy and a semiconductor structure, and belongs to the technical field of semiconductors. The semiconductor epitaxy at least comprises a substrate; the first buffer layer is arranged on the substrate, and the first buffer layer is of an amorphous structure; and the second buffer layer is arranged on the first buffer layer, and the second buffer layer is of a polycrystalline structure. Through the semiconductor epitaxy provided by the utility model, high-quality semiconductor epitaxy can be formed.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the field of semiconductor technology, especially relates to a semiconductor epitaxy and semiconductor structure. BACKGROUND

[0002] In semiconductor epitaxy, a buffer layer is formed on a substrate. The buffer layer can reduce the deformation and adaptation caused by the difference in lattice parameters between the substrate and the semiconductor layer thereon, so that the defects and distortions in the crystal growth process are reduced, thereby improving the device performance and reliability.

[0003] When the lattice structure of the buffer layer only has one kind of lattice structure, only the deformation and adaptation caused by the difference in lattice parameters between the substrate and the semiconductor layer thereon can be reduced, and the reduction degree is limited, and a high-quality semiconductor epitaxial structure cannot be obtained. UTILITY MODEL CONTENT

[0004] The utility model aims at providing a semiconductor epitaxy and semiconductor structure, which can solve the problem that a buffer layer with only one kind of lattice structure cannot obtain a high-quality semiconductor epitaxial structure.

[0005] To solve the above technical problem, the utility model is realized by the following technical scheme:

[0006] The utility model provides a semiconductor epitaxy, which comprises:

[0007] a substrate;

[0008] a first buffer layer, which is arranged on the substrate and is an amorphous structure; and

[0009] a second buffer layer, which is arranged on the first buffer layer and is a polycrystalline structure.

[0010] In an embodiment of the utility model, the first buffer layer and the second buffer layer are aluminum nitride layers.

[0011] In an embodiment of the utility model, the first buffer layer is an aluminum nitride layer formed by using metal organic chemical vapor deposition.

[0012] In an embodiment of the utility model, the thickness of the first buffer layer ranges from 5 nm to 10 nm.

[0013] In an embodiment of the utility model, the second buffer layer is an aluminum nitride layer formed by using physical vapor deposition.

[0014] In an embodiment of the utility model, the thickness of the second buffer layer is 20 nm.

[0015] In an embodiment of the utility model, the first buffer layer and the second buffer layer (002) direction half peak full width is less than or equal to 1 °.

[0016] In an embodiment of the utility model, the first buffer layer and the second buffer layer (002) direction half peak full width is less than or equal to 0.7 °.

[0017] In an embodiment of the utility model, the first buffer layer and the second buffer layer's uniformity RMS value is less than or equal to 1nm.

[0018] The utility model also provides a kind of semiconductor structure, including the semiconductor epitaxy as any one of the above.

[0019] Summarized above, the utility model provides a kind of semiconductor epitaxy and semiconductor structure, first buffer layer and the second buffer layer of amorphous lattice structure are formed on substrate, and the lattice structure of second buffer layer and semiconductor layer is more adapted, can more greatly reduce the defect and structural distortion caused by lattice structure between substrate and semiconductor layer, further improve the quality of formed semiconductor epitaxy.

[0020] Certainly, it is not necessary to achieve all the advantages described above while implementing any product of the utility model. DRAWINGS

[0021] In order to more clearly illustrate the technical scheme of the embodiments of the utility model, the following will briefly introduce the drawings needed to be used in embodiment description, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained according to these drawings without creating labor.

[0022] Figure 1 It is the structure schematic view of semiconductor device in an embodiment.

[0023] Figure 2 It is the structure schematic view of compound semiconductor sputtering device in an embodiment.

[0024] Figure 3 It is the layout schematic view of magnetron in an embodiment.

[0025] Figure 4 It is the layout schematic view of magnetron in another embodiment.

[0026] Figure 5 It is the structure schematic view of electrode assembly in an embodiment.

[0027] Figure 6 It is the structure schematic view of electrode assembly and dielectric layer in an embodiment.

[0028] Figure 7 A schematic diagram of the structure of an anode sheet in an embodiment.

[0029] Figure 8 A schematic diagram of the structure of an electrostatic chuck in an embodiment.

[0030] Figure 9 A schematic diagram of the structure of an electrode assembly and a substrate in an electrostatic chuck in an embodiment.

[0031] Figure 10 A schematic diagram of the distribution of positive and negative sheets on a chuck in an embodiment.

[0032] Figure 11 A schematic diagram of the structure of a base in an electrostatic chuck in an embodiment.

[0033] Figure 12 A schematic diagram of the structure of a semiconductor epitaxy in an embodiment. DETAILED DESCRIPTION

[0034] The other advantages and effects of the present application can be easily understood by those skilled in the art from the content disclosed in the specification. The present application can also be implemented or applied in other different specific embodiments, and each detail in the specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0035] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only show the components related to the present application in the diagrams, not the number, shape and size of the components when actually implemented. The shapes, number and proportions of the components when actually implemented can be randomly changed, and the layout pattern of the components can be more complex.

[0036] In the present application, it should be noted that if terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like appear, the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, if the terms "first" and "second" appear, they are only for description and differentiation purposes, and cannot be understood as indicating or implying relative importance.

[0037] Please refer to Figure 1As shown, the semiconductor device 100 provided in the present application can complete the transmission of the wafer and the deposition of various common semiconductor films. In an embodiment of the present application, the semiconductor device 100 can include a physical vapor deposition device, a chemical vapor deposition device, an atomic layer deposition (ALD) device, a transfer device and / or a combined system of other semiconductor devices 100, forming a semiconductor device system.

[0038] Referring to Figure 1 As shown, in an embodiment of the present application, the semiconductor device 100 is provided with a plurality of chambers. Specifically, the semiconductor device 100 can include a transfer chamber and a plurality of growth chambers arranged around the transfer chamber. Among them, the growth chamber can be a physical vapor deposition chamber, or a chemical vapor deposition chamber, an atomic layer deposition (ALD) growth chamber or other deposition working chamber. And the number of transfer chambers and growth chambers can be set according to the needs.

[0039] Referring to Figure 1 As shown, in a specific embodiment of the present application, the semiconductor device 100 includes two transfer chambers, i.e. a first transfer chamber 101 and a second transfer chamber 102, and the first transfer chamber 101 and the second transfer chamber 102 are communicated through a connecting channel 103. The growth chamber arranged around the first transfer chamber 101 is, for example, a plasma sputtering chamber 104, to realize the physical deposition of the semiconductor film on the wafer. The second transfer chamber 102 is communicated with the first transfer chamber 101 through two connecting channels 103, one of which is used as a transfer path from the first transfer chamber 101 to the second transfer chamber 102, and the other is used as a transfer path from the second transfer chamber 102 to the first transfer chamber 101. The growth chamber arranged around the second transfer chamber 102 is, for example, a compound deposition chamber 105, to realize the chemical deposition of the semiconductor film on the wafer. Among them, the compound deposition chamber 105 can include, for example, a common aluminum nitride deposition chamber, an N-type gallium nitride deposition chamber, a P-type gallium nitride deposition chamber and an aluminum gallium nitride deposition chamber. In other embodiments, according to actual needs, a third transfer chamber and a fourth transfer chamber or more transfer chambers can be arranged in the semiconductor device 100, and the two adjacent chambers are communicated through two connecting channels.

[0040] It should be noted that in some embodiments, cleaning chambers or preheating chambers or other auxiliary chambers can also be arranged around the transfer chamber to realize the cleaning or preheating of the semiconductor structure. In other embodiments, a mechanical arm is arranged in the transfer chamber to realize the flow of the wafer in each growth chamber or adjacent transfer chamber.

[0041] Referring to Figure 1As shown in the utility model one embodiment, the inlet of the transfer cavity of wafer in and out is provided with inlet 106 and outlet 107. In this embodiment, the first transfer cavity 101 is used as the transfer cavity of wafer in and out, that is, the inlet of the first transfer cavity 101 is provided with inlet 106 and outlet 107. Among them, the wafer enters the transfer cavity from the inlet 106, and the wafer is transferred out of the transfer cavity from the outlet 107. In all transfer cavities, the transfer station 108 is provided, which is communicated with other semiconductor equipment 100. Before entering other semiconductor equipment 100, the wafer is passed through the transfer station 108 to avoid mutual pollution between adjacent semiconductor equipment 100.

[0042] It should be noted that in other embodiments, the wafer in and out transfer cavity can also be the second transfer cavity, the third transfer cavity or the fourth transfer cavity and other transfer cavities, and the inlet and outlet are arranged at the inlet of the other transfer cavities.

[0043] Please refer to Figure 1 As shown in the utility model one embodiment, the inlet of the first transfer cavity 101 can also be provided with a transition cavity (not shown in the figure). The transition cavity is arranged between the external environment and the transfer cavity, and the transition cavity can provide a vacuum space. The wafer loading device is arranged at the inlet of the transition cavity, and one, two or more wafer carriers can be arranged on each wafer loading device to realize the loading of one, two or more wafers.

[0044] Please refer to Figure 1 And Figure 2 As shown in the utility model one embodiment, one of the growth cavities around the transfer cavity is a semiconductor sputtering equipment 200, which can realize the production of binary compound, ternary compound, quaternary compound or other multi-component compound thin film.

[0045] Specifically, please refer to Figure 2 As shown in the utility model one embodiment, the semiconductor sputtering equipment 200 includes a cavity 201, a first target material 202 arranged in the cavity 201, a second target material 203 arranged in the cavity 201, a reaction gas source 204 and a carrier 205 introduced into the cavity 201. Among them, the first target material 202 is arranged at the first side in the cavity 201, the second target material 203 is arranged at the second side in the cavity 201, the carrier 205 is arranged at the third side in the cavity 201, and the carrier 205 is provided with a substrate 206. Among them, the first side, the second side and the third side represent different positions in the cavity 201, so that the first target material 202 at the first side and the second target material 203 at the second side can be sputtered on the surface of the substrate 206 on the carrier 205 at the third side.

[0046] It should be noted that the present application does not limit the number and position of the target material and the reaction gas source. The embodiment takes one first target material and one second target material arranged in the cavity as an example for illustration. In other embodiments, two or more first target materials and two or more second target materials can also be arranged in the cavity, and the ion sputtering of the target material on the substrate can be realized, and the reaction gas source can also be arranged according to the demand.

[0047] Please refer to Figure 2 As shown in the figure, in an embodiment of the present application, the cavity 201 is made of high-temperature-resistant material, and can be made of alloy or other high-temperature-resistant material, so that the cavity 201 can withstand, for example, 1200℃ or higher high-temperature-resistant material.

[0048] Please refer to Figure 2 As shown in the figure, in an embodiment of the present application, the first target material 202 is a liquid target material at room temperature, and is arranged on the bottom wall inside the cavity 201, thereby ensuring stable placement of the liquid target material. In other embodiments, if the first target material 202 is a non-liquid target material, the first target material 202 can also be arranged on the side wall inside the cavity 201, or the first target material 202 can be placed obliquely at the connection between the bottom wall and the side wall inside the cavity 201, or the first target material 202 can be placed obliquely at the connection between the top wall and the side wall inside the cavity 201.

[0049] Please refer to Figure 2 As shown in the figure, in an embodiment of the present application, a first base 207 is arranged on the bottom wall of the cavity 201, and the first target material 202 is placed on the surface of the first base 207. The diameter of the first target material 202 is, for example, 150mm-400mm, and in the embodiment, the first target material 202 is, for example, gallium. Gallium is in a liquid state at room temperature. The semiconductor sputtering device 200 provided by the embodiment can realize the preparation of gallium-containing compounds. The purity of gallium is greater than or equal to 99.999%.

[0050] Please refer to Figure 2As shown, in one embodiment of this invention, a first electrode 208 is disposed in the first base 207, and the first electrode 208 is, for example, a cathode. An electric field is formed between the first electrode 208 and the anode disposed on the stage 205, thereby causing electrons to move towards the stage 205. In this embodiment, to increase the uniformity and intensity of the electric field between the first base 207 and the stage 205, the first electrode 208 is laid on the cross-section of the first base 207. Furthermore, the orthographic projection of the first electrode 208 in the first base 207 coincides with the first target 202, which can confine electrons within the minimum range of the electric field between the first base 207 and the stage 205, thereby increasing the sputtering efficiency of ions. That is, the diameter of the first electrode 208 in the first base 207 is the same as that of the first target 202, and is, for example, 150mm to 400mm.

[0051] Please see Figure 2 As shown, in one embodiment of this utility model, a magnetron 209 is further provided in the first base 207. The magnetron 209 is disposed in the first base 207, and the plane of the magnetron 209 is parallel to the plane of the first electrode 208. In this embodiment, the first base 207 is cylindrical, and the cross-section of the first base 207 is circular. Combined with... Figure 3 and Figure 4 As shown, the magnetron 209 is located in a sector-shaped cross-section with the center of the first base 207 as the center and any length greater than 0 as the radius, and the central angle of this sector-shaped cross-section is greater than zero. In this sector-shaped cross-section, the magnetrons 209 are arranged in an S-shape, or the magnetrons 209 cover the entire sector-shaped cross-section. When the first base 207 rotates around its center under the drive of the DC power supply 211, the first magnetron rotates accordingly, and the generated magnetic field is parallel to the cross-section of the first base 207. Compared to covering the entire cross-section of the first base 207 with magnetrons 209, placing the magnetrons 209 in the sector-shaped cross-section of the first base 207 and rotating the first base 207 generates a more uniform magnetic field, thereby improving the uniformity of the thin film formed on the substrate 206. In some embodiments, the position and / or number of magnetrons 209 can be adjusted to correspond to changes in the magnetic field within the adjustment cavity.

[0052] Please see Figure 2 As shown, in one embodiment of this utility model, a cooling water circuit 210 is further provided in the first base 207, and flowing cooling water is provided in the cooling water circuit 210 to ensure that the temperature of the first base 207 and the device on the first base 207 is stable within a certain range. In this embodiment, the temperature of the cooling water is, for example, 18°C ​​to 20°C.

[0053] Please see Figure 2As shown in the utility model one embodiment, semiconductor sputtering equipment 200 still is provided with direct current (Direct Current, DC) power supply 211 and radio frequency (radio frequency, RF) power supply 212, and direct current power supply 211 and radio frequency power supply 212 are electrically connected to first electrode 208, and direct current power supply 211 and radio frequency power supply 212 provide power supply and bias for first electrode 208, to realize the adjustment of electric field, and then adjust the path of ion sputtering. Wherein, direct current power supply 211 and radio frequency power supply 212 can be arranged outside cavity 201, and first electrode 208 in cavity 201 can be electrically connected through cavity 201. The maximum power of direct current power supply 211 is for example 15000W, and the maximum power of radio frequency power supply 212 is for example 8000W. In working, the specific power of direct current power supply 211 and radio frequency power supply 212 can be adjusted according to actual demand.

[0054] Please refer to Figure 2 As shown in the utility model one embodiment, second target material 203 is solid target material at normal temperature, and second target material 203 is arranged on the side wall inside cavity 201. In other embodiments, second target material 203 can also be arranged on the bottom wall inside cavity 201, or second target material 203 is placed obliquely at the junction of the bottom wall and the side wall inside cavity 201, or second target material 203 is placed obliquely at the junction of the top wall and the side wall inside cavity 201.

[0055] Please refer to Figure 2 As shown in the utility model one embodiment, to realize the fixation of second target material 203, second pedestal 213 is further arranged on the side wall inside cavity 201. Second pedestal 213 is fixed on the side wall of cavity 201, and second target material 203 is fixed on the surface of second pedestal 213. The diameter of second target material 203 is for example 50mm~300mm, and in the embodiment, first target material 202 is for example aluminum. Wherein, the purity of aluminum is greater than or equal to 99.999%.

[0056] Please refer to Figure 2 As shown in the utility model one embodiment, in second target material 203, first electrode 208 is arranged, and first electrode 208 is for example cathode, and forms electric field with anode arranged on carrier 205, and then makes electron move to the direction of carrier 205. In the embodiment, first electrode 208 is laid on the cross section of second pedestal 213. The orthographic projection of first electrode 208 in second pedestal 213 on the surface of second pedestal 213 coincides with second target material 203, can constrain electron between the minimum range electric field between second pedestal 213 and carrier 205, and then increase the sputtering efficiency of ion. That is, the diameter of first electrode 208 in second pedestal 213 is same with second target material 203, and is for example 50mm~300mm.

[0057] Please refer toFigure 2 As shown in the embodiment of the utility model, the magnetron 209 is arranged in the second base 213. The magnetron 209 is arranged in the second base 213, and the plane where the magnetron 209 is arranged is parallel to the plane where the first electrode 208 is arranged. In the embodiment, the second base 213 is arranged in a cylindrical shape, and the cross section of the second base 213 is circular. In combination with the first electrode 208, the second base 213 and the magnetron 209 form a semiconductor sputtering device 200. Figure 3 And Figure 4 As shown in the embodiment of the utility model, the magnetron 209 is arranged in the second base 213. The magnetron 209 is arranged in the second base 213, and the plane where the magnetron 209 is arranged is parallel to the plane where the first electrode 208 is arranged. In the embodiment, the second base 213 is arranged in a cylindrical shape, and the cross section of the second base 213 is circular. In combination with the first electrode 208, the second base 213 and the magnetron 209 form a semiconductor sputtering device 200.

[0058] As shown in the embodiment of the utility model, the magnetron 209 is arranged in the second base 213. The magnetron 209 is arranged in the second base 213, and the plane where the magnetron 209 is arranged is parallel to the plane where the first electrode 208 is arranged. In the embodiment, the second base 213 is arranged in a cylindrical shape, and the cross section of the second base 213 is circular. In combination with the first electrode 208, the second base 213 and the magnetron 209 form a semiconductor sputtering device 200. Figure 2 As shown in the embodiment of the utility model, the magnetron 209 is arranged in the second base 213. The magnetron 209 is arranged in the second base 213, and the plane where the magnetron 209 is arranged is parallel to the plane where the first electrode 208 is arranged. In the embodiment, the second base 213 is arranged in a cylindrical shape, and the cross section of the second base 213 is circular. In combination with the first electrode 208, the second base 213 and the magnetron 209 form a semiconductor sputtering device 200.

[0059] As shown in the embodiment of the utility model, the magnetron 209 is arranged in the second base 213. The magnetron 209 is arranged in the second base 213, and the plane where the magnetron 209 is arranged is parallel to the plane where the first electrode 208 is arranged. In the embodiment, the second base 213 is arranged in a cylindrical shape, and the cross section of the second base 213 is circular. In combination with the first electrode 208, the second base 213 and the magnetron 209 form a semiconductor sputtering device 200. Figure 2 As shown in the embodiment of the utility model, the magnetron 209 is arranged in the second base 213. The magnetron 209 is arranged in the second base 213, and the plane where the magnetron 209 is arranged is parallel to the plane where the first electrode 208 is arranged. In the embodiment, the second base 213 is arranged in a cylindrical shape, and the cross section of the second base 213 is circular. In combination with the first electrode 208, the second base 213 and the magnetron 209 form a semiconductor sputtering device 200.

[0060] As shown in the embodiment of the utility model, the magnetron 209 is arranged in the second base 213. The magnetron 209 is arranged in the second base 213, and the plane where the magnetron 209 is arranged is parallel to the plane where the first electrode 208 is arranged. In the embodiment, the second base 213 is arranged in a cylindrical shape, and the cross section of the second base 213 is circular. In combination with the first electrode 208, the second base 213 and the magnetron 209 form a semiconductor sputtering device 200. Figure 2As shown in the utility model one embodiment, in the semiconductor sputtering device 200 still be provided with pre sputtering window 214, pre sputtering window 214 is fixed on the side wall inside cavity 201 through first connecting rod 214. Specifically, pre sputtering window 214 is fixed on motor 215 inside cavity 201 through first connecting rod 214, motor 215 is fixed on the side wall inside cavity 201, and motor 215 is close to second base 213 setting. One end of first connecting rod 214 is fixedly connected in the output end of motor 215, when motor 215 rotates, first connecting rod 214 rotates with motor 215. The other end of first connecting rod 214 is fixedly connected pre sputtering window 214. And pre sputtering window 214 is plate-shaped setting, the orthographic projection of pre sputtering window 214 on second target material 203 covers second target material 203. In the embodiment, pre sputtering window 214 is round plate setting, and the diameter of pre sputtering window 214 is greater than the diameter of second target material 203, and the diameter of pre sputtering window 214 is specifically for example 70mm~330mm.

[0061] Please refer to Figure 2 As shown in the utility model one embodiment, when first connecting rod 214 rotates with motor 215, pre sputtering window 214 also rotates with first connecting rod 214. When pre sputtering window 214 rotates with first connecting rod 214, pre sputtering window 214 is allowed to cut off the sputtering path of second target material 203 to substrate 206, so that the ion generated by second target material 203 sputters on pre sputtering window 214. Therefore, between each sputtering, drive motor 215 rotates, so that pre sputtering window 214 fixed on first connecting rod 214 rotates to the sputtering path of second target material 203 to substrate 206, at this time, the ion generated by second target material 203 sputters on pre sputtering window 214. When the sputtering of the oxidized substance on the surface of second target material 203 is completed, drive motor 215 again, so that pre sputtering window 214 fixed on first connecting rod 214 rotates away from the position of sputtering path, and the ion generated by second target material 203 can sputter to the surface of substrate 206 along the sputtering path.

[0062] Please refer to Figure 2 As shown in the utility model one embodiment, in the semiconductor sputtering device 200 still be provided with pre sputtering window 214, pre sputtering window 214 is fixed on the side wall inside cavity 201 through first connecting rod 214. Specifically, pre sputtering window 214 is fixed on motor 215 inside cavity 201 through first connecting rod 214, motor 215 is fixed on the side wall inside cavity 201, and motor 215 is close to second base 213 setting. One end of first connecting rod 214 is fixedly connected in the output end of motor 215, when motor 215 rotates, first connecting rod 214 rotates with motor 215. The other end of first connecting rod 214 is fixedly connected pre sputtering window 214. And pre sputtering window 214 is plate-shaped setting, the orthographic projection of pre sputtering window 214 on second target material 203 covers second target material 203. In the embodiment, pre sputtering window 214 is round plate setting, and the diameter of pre sputtering window 214 is greater than the diameter of second target material 203, and the diameter of pre sputtering window 214 is specifically for example 70mm~330mm.

[0063] Please refer to Figure 2As shown in the utility model one embodiment, in the cavity 201 in the top wall, be provided with the platform 205. The platform 205 surface places the substrate 206. Can be through structure engagement, electrostatic attraction or other arbitrary fixed mode, the substrate 206 is fixed on the platform 205. And the platform 205 is fixed on the top wall in the cavity 201 through the lifting structure 216, through the lifting structure 216, can adjust the distance between the substrate 206 fixed on the platform 205 and the top wall, and then adjust the distance between the substrate 206 and the target material. In some embodiments, the lifting structure 216 can also rotate, when the lifting structure 216 rotates, the platform 205 rotates around the center, so that the substrate 206 on the platform 205 rotates, and then makes the deposited compound film more uniform.

[0064] Please refer to Figure 2 As shown in the utility model one embodiment, in the cavity 201 in the top wall, be provided with the heating base 217. The heating base 217 is located on the side of the platform 205 away from the substrate 206, and the heating base 217 is provided with an electric circuit to adjust the temperature of the heating base 217, and then adjust the temperature of the substrate 206, realize the heating of the substrate 206. In this embodiment, the heating base 217 is cylindrically arranged, and the diameter of the heating base 217 is, for example, 250mm~350mm, one, two or more substrates 206 can be arranged on the surface of the heating base 2052.

[0065] In different embodiments, the growth temperature (substrate wafer temperature) in the cavity 201 can be greater than 650 DEG C, for example, 650 DEG C.~1900 DEG C. The substrate wafer grown in the cavity 201 can be sapphire, silicon, silicon carbide, aluminum nitride or other substrates, wafers, and the size of the substrate wafer to be plated in the cavity 201 can be, for example, 2 inches, 4 inches, 6 inches and / or 8 inches.

[0066] Please refer to Figure 2 As shown in the utility model one embodiment, in the cavity 201 in the top wall, still be provided with the second electrode 218, the second electrode 218 is the anode, and the first electrode 208 arranged in the first base 207 and the second base 213 form an electric field. The electron follows the electric field, from the first target material 202 and the second target material 203 to the substrate 206, collides with the inert gas atom, generates inert gas positive ion and new electron, the new electron moves to the substrate 206, and the generated inert gas ion is bombarded on the first target material 202 and the second target material 203 under the action of the electric field, so that the target material sputters.

[0067] It should be noted that, please refer to Figure 2In the embodiment, the distance between the center of the first target 202 and the center of the substrate 206 is, for example, 10 cm to 17 cm, and the distance between the center of the second target 203 and the center of the substrate 206 is, for example, 10 cm to 12 cm. The distance between the center of the first target 202 and the center of the substrate 206, and the distance between the center of the second target 203 and the center of the substrate 206 are limited, so that the sputtered ions from the two targets cannot react in a short path to form a compound film on the surface of the substrate 206, and the sputtered ions from the two targets cannot react in a long path to form a granular protrusion on the surface of the substrate 206, which affects the quality of the formed compound film.

[0068] Referring to Figure 2 In an embodiment of the utility model, the semiconductor sputtering device 200 is further provided with a gas inlet pipe 219, and the gas inlet pipe 219 is connected with an external gas source and the cavity 201 to supply inert gas and reaction gas in the cavity 201. The external gas source includes an inert gas source and a reaction gas source 204. Before the reaction, the inert gas is introduced into the cavity 201 through the gas inlet pipe 219, so that the cavity 201 is close to vacuum. At this time, the pressure in the cavity 201 is less than 10 -6 Pa, for example, 10 -7 Pa. When the compound film is formed, the reaction gas is introduced into the cavity 201 through the gas inlet pipe 219, and the reaction gas reacts with the sputtered ions from the target to form a compound film on the surface of the substrate 206. When the reaction gas is introduced into the cavity 201, the working pressure in the cavity 201 is set to 0.6 Pa to 1.2 Pa.

[0069] Referring to Figure 2 In an embodiment of the utility model, the gas inlet pipe 219 surrounds the carrier 205, and the gas inlet pipe 219 can form a plurality of gas rings, and the plurality of gas rings are arranged side by side in the lifting direction of the carrier 205. The diameter of the gas ring formed by the gas inlet pipe 219 is greater than the diameter of the carrier 205, for example, 150 mm to 600 mm. A plurality of openings (not shown in the figure) are arranged on the side of each gas ring close to the substrate 206, and the distance between adjacent openings is equal, so that the openings are uniformly distributed on the gas ring. At this time, the inert gas or reaction gas introduced through the gas inlet pipe 219 can be more uniformly introduced into the cavity.

[0070] Referring to Figure 2As shown, the present application does not limit the type of inert gas source and reaction gas source 204, and the inert gas source and reaction gas source 204 can be passed according to the compound film to be formed. In the present embodiment, the inert gas passed into the cavity 201 is, for example, argon, and the reaction gas passed into the cavity 201 is, for example, nitrogen. In combination with the materials of the first target 202 and the second target 203, an aluminum gallium nitride film can be formed on the substrate 206 in the present embodiment. In other embodiments, the materials of the targets and the types of the gases passed in can be adjusted to form other compound films.

[0071] Referring to Figure 2 As shown, in an embodiment of the present application, an air outlet 220 is further arranged in the chamber, the air outlet 220 is arranged on the side wall of the chamber, and the air outlet 220 is located on the side of the chamber close to the bottom wall. The air outlet 220 is connected with a power device 221, the power device 221 can extract the gas in the chamber through the air outlet 220. A cover plate 222 is arranged on the side of the air outlet 220, and the cover plate 222 is movably connected on the side of the air outlet 220. The cover plate 222 is connected with a motor 224 through a second connecting rod 223. With the rotation of the motor 224, the cover plate 222 is allowed to cover the air outlet 220. At the same time, with the rotation of the motor 224, the cover plate 222 is also allowed to expose the air outlet 220.

[0072] Referring to Figure 2 and Figure 5 As shown, in an embodiment of the present application, the substrate 206 is fixed on the carrier 205 by electrostatic attraction. Correspondingly, an electrode assembly 300 is arranged in the carrier 205. The electrode assembly 300 is located on the side close to the surface of the carrier 205, and can provide a large suction force, so that the substrate 206 is fixed on the surface of the carrier 205 by electrostatic attraction.

[0073] Referring to Figure 5 and Figure 6As shown in the utility model one embodiment, electrode assembly 300 includes positive plate 301 and negative plate 302, and positive plate 301 and negative plate 302 are stacked. Between positive plate 301 and negative plate 302, and the two sides opposite to positive plate 301 and negative plate 302, there are insulating medium layer 303. And three insulating medium layers 303 wrap up positive plate 301 and negative plate 302. And dielectric layer 304 is arranged on the insulating medium layer 303 on the side of positive plate 301 away from negative plate 302, and the insulating medium layer 303 is the surface of platform 205, so substrate 206 is adsorbed on the medium layer. When placing substrate 206 on platform 205, connecting positive plate 301 to the positive pole of power supply, or connecting negative plate 302 to the negative pole of power supply, an electric field can be formed between positive plate 301 or negative plate 302 and dielectric layer 304. And at the same time, connecting positive plate 301 to the positive pole of power supply, and connecting negative plate 302 to the negative pole of power supply, can release the free charge generated in dielectric layer 304, and faster and stable desorption treatment can be carried out.

[0074] Please refer to Figure 5 and Figure 7 As shown in the utility model one embodiment, negative plate 302 is in the form of a sheet, and the cross section of negative plate 302 is rectangular. Positive plate 301 includes a plurality of first positive strips 3011 arranged side by side, and equal spacing is provided between adjacent first positive strips 3011. And one end of the plurality of first positive strips 3011 is connected by second positive strip 3012. The positive plate 301 composed of a plurality of first positive strips 3011 with spacing makes the adsorption force of platform 205 larger when substrate 206 is within the adsorption range of platform 205 (for example, the distance between substrate 206 and the surface of platform 205 is less than 0.05mm), and the adsorption force of platform 205 is very small when substrate 206 is away from the surface of platform 205 by a predetermined distance (for example, the distance between substrate 206 and the surface of platform 205 is greater than 1mm). At this time, when substrate 206 is placed on platform 205, platform 205 firmly fixes substrate 206 by adsorption force, and when substrate 206 is removed from platform 205, as long as it is away from platform 205 by a predetermined distance, substrate 206 can be easily peeled off from platform 205. In this embodiment, positive plate 301 is for example a positive plate 301 arranged in a comb shape. In other embodiments, first positive strips 3011 can be bent and deformed to form positive plates 301 of other shapes, such as fan-shaped, wave-shaped, etc. Second positive strip 3012 can realize the connection of a plurality of first positive strips 3011.

[0075] Please refer to Figure 5 and Figure 6As shown in the utility model one embodiment, for enhancing the space electric field between the positive plate 301 and the negative plate 302, the cross section of the positive plate 301 is provided with multiple protrusions 3013, and the spacing between the multiple protrusions 3013 is equal. That is, the cross section of the first positive strip 3011 is provided with multiple protrusions 3013. Specifically, in the embodiment, the cross section of the positive plate 301 is provided with, for example, 4 protrusions 3013, and the cross section of the positive plate 301 is provided in a cross shape. In other embodiments, the cross section of the positive plate 301 can also be provided with, for example, 6 protrusions 3013 or 8 protrusions 3013, etc. The cross section of the positive plate 301 is provided with multiple protrusions 3013, which enhances the space electric field and thus increases the adsorption force, so that the adsorption can be better controlled at a certain voltage. The cross section of the positive plate 301 is provided with multiple protrusions 3013, which changes the uniformity of the electric field. Compared with the cross section of the positive plate 301 provided in a rectangular shape, the cross section of the positive plate 301 provided with multiple protrusions 3013 has more uniform adsorption force and is not easy to break.

[0076] Please refer to Figure 8 As shown in the utility model one embodiment, the carrier 205 includes a chuck 2051, a base 2052 and multiple fixing members 2053. The chuck 2051 includes a base material 305 and an electrode assembly 300 arranged on the base material 305, and the base 2052 is connected with the chuck 2051. The multiple fixing members 2053 cooperate with each other to fix the chuck 2051 and the base 2052 together.

[0077] Specifically, please refer to Figure 8 , Figure 9 and Figure 10 As shown in the utility model one embodiment, the base material 305 is provided in a circular shape, the electrode assembly 300 is arranged on the base material 305, and the negative plate 302 contact point is arranged at the center of the base material 305. The positive plate 301 is bent and arranged in a ring shape, that is, multiple first positive strips 3011 are bent and arranged in a circular ring shape, and multiple second positive strips 3012 are used to connect the first positive strips 3011. The multiple second positive strips 3012 form a cross shape. The positive plate contact point can be arranged at the edge of the base material 305, and the negative plate contact point can be arranged at the center of the base material 305. At the bottom of the base material 305, a recess plug 3051 is arranged. The negative plate contact point and the positive plate contact point are electrically connected to the recess plug 3051, and are connected to the outside through the recess plug 3051.

[0078] Please refer to Figure 8 , Figure 9 , Figure 10 and Figure 11As shown in the utility model one embodiment, the base 2052 is provided with the protruding plug 3081, the protruding plug 3081 is adapted with the recessed plug 3051, allows the protruding plug 3081 to be inserted in the recessed plug 3051, and then realizes the power supply of electrode assembly 300.And in the base 2052, still be provided with airflow layer 308, heating layer 307 and cooling layer 306.And airflow layer 308 is set on heating layer 307, heating airflow layer 308 by heating layer 307, realizes the preheating function of the stage 205.The airflow circuit is arranged in the airflow layer 308, and the heated airflow can be introduced into the airflow circuit as the main medium of heating.The cooling layer 306 is set on the side of heating layer 307 away from airflow layer 308, and the cooling circuit is arranged in the cooling layer 306, so that the heating layer 307 can be quickly cooled when heating is not required.

[0079] Please refer to Figure 8 As shown in the utility model one embodiment, the fixing part 2053 includes a plurality of buckles, and the plurality of buckles on both sides of the chuck 2051 and the base 2052 are buckled with each other to fix the chuck 2051 and the base 2052 together.The plurality of buckles can be connected by a mortise and tenon structure or other structures such as bolts.

[0080] Please refer to Figure 8 As shown in the utility model one embodiment, the buckle near the surface of the chuck 2051 can also be provided with a pressure sensor (not shown in the figure), when the pressure sensor senses that the substrate 206 on the chuck 2051 has been adsorbed, the buckle can fall down for secondary fixation to prevent accidents.At the same time, if the pressure changes are not obvious when the substrate 206 just enters the chuck 2051, an alarm processing is performed to avoid problems in adsorption.

[0081] In one embodiment, the growth rate of the thin film is, for example, 0.1 nm / s to 1.5 nm / s, and for example, 0.3 nm / s to 1.2 nm / s, by the apparatus of the present application. In one embodiment, the full width at half maximum (FWHM) of the (002) direction of the thin film (e.g., AlN, GaN or other thin film) having a thickness of 1.1 um to 200 nm can be less than or equal to 1°, and for example, less than or equal to 0.7°. In one embodiment, the full width at half maximum (FWHM) of the (002) direction of the thin film (e.g., AlN, GaN or other thin film) having a thickness of 150 nm to 210 nm can be less than or equal to 1.5°, and for example, less than or equal to 0.9°. In one embodiment, the full width at half maximum (FWHM) of the (002) direction of the thin film (e.g., AlN, GaN or other thin film) having a thickness of 50 nm to 100 nm can be less than or equal to 0.5°, and for example, less than or equal to 0.1°. In addition, the uniformity RMS value of the thin film can be less than or equal to 1 nm, and for example, less than or equal to 0.7 nm, and the number of particle defects (particle > 0.3 um) on the thin film can be, for example, 50 to 150, by the apparatus of the present application.

[0082] In different embodiments, the temperature inside the cavity can be detected, and the temperature of the components inside the cavity can be controlled according to the detected temperature, so that there is no excessive temperature difference in the high-temperature environment inside the reaction chamber, thereby reducing the particle problem. For example, during the growth process, the working temperature of the substrate can be lower than the working temperature of the target.

[0083] In one embodiment, the shielding member inside the reaction chamber can be connected to the potential of the cavity to reduce the arc, thereby reducing the generation of particle defects.

[0084] In one embodiment, when the apparatus of the present application is a multi-target system, the grown thin film can be, for example, AlGaN, AlScN, P-type GaN, N-type GaN or other material thin film.

[0085] In one embodiment, the substrate for growing the thin film can be, for example, a deep-width ratio of 1:1 to 5:1, by the apparatus of the present application.

[0086] Referring to FIG. 12, the present application also provides a semiconductor epitaxial 40 formed using the semiconductor apparatus 100 provided by the present application. The semiconductor epitaxial 40 includes a substrate 400, a first buffer layer 401 disposed on the substrate 400, and a second buffer layer 402 disposed on the first buffer layer 401. The first buffer layer 401 is an amorphous structure, and the second buffer layer 402 is a polycrystalline structure.

[0087] Referring to FIG. 12, the present application also provides a semiconductor epitaxial 40 formed using the semiconductor apparatus 100 provided by the present application. The semiconductor epitaxial 40 includes a substrate 400, a first buffer layer 401 disposed on the substrate 400, and a second buffer layer 402 disposed on the first buffer layer 401. The first buffer layer 401 is an amorphous structure, and the second buffer layer 402 is a polycrystalline structure. Figure 12As shown in the embodiment of the present application, the substrate 400 can be various suitable substrate materials, and the material of the substrate 400 can be a semiconductor substrate 400 material such as silicon (Si), silicon carbide (SiC), sapphire ((Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc. In this embodiment, the substrate 400 is, for example, a silicon (Si) based material, such as silicon (Si) or silicon carbide (SiC) and the like.

[0088] Referring to Figure 12 As shown in the embodiment of the present application, at least two kinds of lattice form buffer layers are provided on the substrate 400. Specifically, the first buffer layer 401 is an amorphous structure, and the second buffer layer 402 is a polycrystalline structure, and the second buffer layer 402 is provided on the first buffer layer 401. By providing the second buffer layer 402 of the polycrystalline structure on the first buffer layer 401 of the amorphous structure, a more stable and better quality buffer layer can be obtained.

[0089] Referring to Figure 12 As shown in the embodiment of the present application, the first buffer layer 401 is an amorphous aluminum nitride (AlN) buffer layer. In this embodiment, the first buffer layer 401 can be grown using metal-organic chemical vapor deposition (MOCVD). When the first buffer layer 401 is formed using metal-organic chemical vapor deposition, trimethylaluminum (TMAl) gas can be used as an aluminum source, and ammonia (NH3) gas can be used as a nitrogen source and introduced into a reaction chamber for reaction to form an aluminum nitride buffer layer as the first buffer layer 401. When forming the first buffer layer 401, the growth temperature is in the range of, for example, 1000°C to 1400°C, and the growth pressure is in the range of, for example, 10 Torr to 100 Torr. The specific growth temperature and range are set according to the equipment used and the quality requirements of the target film. By forming the first buffer layer through metal-organic chemical vapor deposition, the reaction conditions can be precisely controlled, parasitic reactions in the gas phase can be effectively reduced, the generation of nanoparticles can be reduced, and thus the growth efficiency and quality of the film can be improved.

[0090] Referring to Figure 12 As shown in the embodiment of the present application, the thickness of the first buffer layer 401 formed is in the range of 5nm to 10nm, and can be, for example, 5nm, 7nm, 8nm or 10nm, or 56.5nm, 8.5nm or 9.5nm, etc.

[0091] Referring to Figure 12In an embodiment of the present application, the second buffer layer 402 is an aluminum nitride buffer layer with a polycrystalline structure. In the embodiment, the second buffer layer 402 can be grown by physical vapor deposition (PVD). When the second buffer layer 402 is formed by physical vapor deposition, a sputtering method can be used to form aluminum nitride as the second buffer layer 402. Specifically, the aluminum nitride target material can be placed in an inert gas environment, a high-energy ion beam or electron beam is applied to make the atoms on the surface of the target sputter and deposit on the substrate 400 to form an aluminum nitride buffer layer. The aluminum nitride buffer layer formed by the sputtering method has good uniformity and density.

[0092] Referring to Figure 12 In an embodiment of the present application, the thickness of the second buffer layer 402 formed is in the range of 20nm to 25nm, and can be specifically 20nm, or 21nm, 22nm or 25nm, etc.

[0093] Referring to Figure 12 In an embodiment of the present application, the second buffer layer 402 with a polycrystalline structure is formed on the first buffer layer 401 with an amorphous structure. The first buffer layer 401 with an amorphous structure has a high thermal conductivity, so that the semiconductor device formed can quickly conduct heat energy from the inside of the device under high-temperature working environment, effectively reducing the working temperature, and can significantly improve the stability and life of the semiconductor device formed. At the same time, the first buffer layer 401 with an amorphous structure has a low dielectric constant, which can reduce the loss in the signal transmission process and effectively improve the working frequency of the device and the efficiency of signal processing. The first buffer layer 401 with an amorphous structure has good chemical and physical stability at high temperatures, which can improve the quality of the buffer layer formed. The lattice structure of the first buffer layer 401 with an amorphous structure is more matched with the lattice structure of the substrate 400, and the lattice structure of the second buffer layer 402 with a polycrystalline structure is more matched with the semiconductor layer formed thereon. From the first buffer layer 401 to the second buffer layer 402, the stress caused by the mismatch of the lattice constant between the substrate 400 and the semiconductor layer on the buffer layer can be gradually reduced, the formation of dislocations and other defects can be reduced, and thus the stability of the overall structure can be improved.

[0094] Referring to Figure 12 The semiconductor epitaxial layer 40 provided by the present application can be applied to semiconductor devices such as diodes, photodiodes, light-emitting diodes, transistors, field effect transistors, voltage stabilizers, sensors, power devices, radio frequency devices, etc., and any semiconductor structure in these semiconductor devices.

[0095] The utility model provides a kind of semiconductor epitaxy and semiconductor structure, the semiconductor epitaxy includes substrate, first buffer layer being set on substrate, second buffer layer being set on first buffer layer, and first buffer layer is amorphous structure, and second buffer layer is polycrystalline structure.

[0096] The above disclosed embodiments of the utility model are only used to help the description of the utility model. The embodiments do not describe all the details, and the utility model is not limited to the specific embodiments. Obviously, according to the content of the specification, many modifications and changes can be made. The specification selects and specifically describes these embodiments, in order to better explain the principle and practical application of the utility model, so that the skilled in the art can well understand and use the utility model. The utility model is limited by the claims and the whole scope and equivalents.

Claims

1. A semiconductor epitaxial layer, characterized by, At least comprising: a substrate; a first buffer layer disposed on the substrate, the first buffer layer being amorphous structure; and a second buffer layer disposed on the first buffer layer, the second buffer layer being polycrystalline structure. The first buffer layer and the second buffer layer are aluminum nitride layers.

2. The semiconductor epitaxy of claim 1, wherein The first buffer layer is an aluminum nitride layer formed using metal organic chemical vapor deposition.

3. The semiconductor epitaxy of claim 1, wherein The first buffer layer has a thickness ranging from 5 nm to 10 nm.

4. The semiconductor epitaxy of claim 1, wherein The second buffer layer is an aluminum nitride layer formed using physical vapor deposition.

5. The semiconductor epitaxy of claim 1, wherein The second buffer layer has a thickness of 20 nm.

6. The semiconductor epitaxy of claim 1, wherein The first buffer layer and the second buffer layer have a full width at half maximum in the (002) direction less than or equal to 1°.

7. The semiconductor epitaxy of claim 1, wherein The first buffer layer and the second buffer layer have a full width at half maximum in the (002) direction less than or equal to 0.7°.

8. The semiconductor epitaxy of claim 1, wherein, The first buffer layer and the second buffer layer have a uniformity RMS value less than or equal to 1 nm.

9. The semiconductor epitaxy of claim 1, wherein A semiconductor epitaxy comprising any one of claims 1 to 9.

10. A semiconductor structure, characterized by ​

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