Multi-platform compatible test carrier plate based on wafer chip mass production test
By designing a multi-platform compatible wafer chip test substrate, the problems of compatibility and high cost of traditional substrates are solved, improving flexibility and efficiency, and ensuring the accuracy of test results and the reliability of chips.
Patent Information
- Application Number
- CN202520400360.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2026-02-17
- Estimated Expiration
- 2035-03-10
AI Technical Summary
Traditional test substrates are typically only compatible with test platforms from a single manufacturer or model, which limits the flexibility and efficiency of chip testing. Furthermore, the different interface requirements of different test platforms result in complex and costly substrate designs, making it difficult to adapt to rapidly changing market demands.
Design a multi-platform compatible test carrier board for wafer chip mass production testing, including functional interface modules, test modules, temperature monitoring modules, early warning modules, and temperature control modules. It can be adapted to multiple test platforms. The modular design improves flexibility and efficiency, and ensures the accuracy of test results and the long-term reliability of the chip.
It achieves high compatibility with multiple testing platforms, improves the flexibility and efficiency of chip testing, reduces production costs, shortens hardware design cycles, and ensures the accuracy of test results and the long-term reliability of chips.
Smart Images
Figure CN223926567U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor testing technology, and in particular to a multi-platform compatible test carrier board for wafer chip mass production testing. Background Technology
[0002] In semiconductor manufacturing, functional testing (FT) and parameter testing (CP) of chips on wafers are crucial steps in ensuring chip quality. Traditional test substrates are typically only compatible with test platforms from a single manufacturer or model, limiting the flexibility and efficiency of chip testing. Furthermore, different test platforms have varying interface requirements for substrates, leading to complex substrate designs, high costs, and difficulty in adapting to rapidly changing market demands.
[0003] Therefore, it is of great significance to develop a universal test carrier board that is compatible with multiple test platforms. Utility Model Content
[0004] The purpose of this invention is to address the shortcomings of traditional test carriers, which are usually only compatible with a single manufacturer or model of test platform, thus limiting the flexibility and efficiency of chip testing. This invention proposes a multi-platform compatible test carrier for wafer chip mass production testing.
[0005] To achieve the above objectives, the present invention adopts the following technical solution:
[0006] A multi-platform compatible test carrier board for wafer chip mass production testing includes a test carrier board on which:
[0007] Functional interface module;
[0008] The test module is connected to the functional interface module. The test module includes a CP test unit and an FT test unit, and the CP test unit is connected to the FT test unit.
[0009] A temperature monitoring module is used to perform temperature testing on the CP test unit and the FT test unit, and the temperature monitoring module is connected to the CP test unit and the FT test unit respectively;
[0010] The early warning module is connected to the temperature monitoring module;
[0011] A temperature control module, which is connected to an early warning module.
[0012] Furthermore, the functional interface module includes a power supply channel unit, a digital channel unit connected to the power supply channel unit, a mixed signal unit connected to the channel unit, a memory function test dedicated channel unit connected to the mixed signal test dedicated channel unit, and a relay switch control channel unit connected to the memory function test dedicated channel unit, wherein the power supply channel unit is connected to the relay switch control channel unit.
[0013] Furthermore, the power supply channel unit is connected to the relay switch control channel unit, and the relay switch control channel unit is connected to the test module.
[0014] Furthermore, the temperature monitoring module is equipped with a temperature sensor.
[0015] Furthermore, the temperature control module includes a cooling unit, which is a heat sink.
[0016] Furthermore, the early warning module is an alarm, and the early warning module is connected to the temperature monitoring module.
[0017] Compared with the prior art, the advantages of this utility model are:
[0018] 1. This solution is highly compatible and can be adapted to various test platforms from different manufacturers and models, improving the flexibility and efficiency of chip testing;
[0019] 2. The temperature range setting for wafer chip testing in this solution can better utilize the chip's performance, ensuring the accuracy of test results and the long-term reliability of the chip. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a flowchart of the multi-platform compatible test carrier board based on wafer chip mass production testing proposed in this utility model;
[0022] Figure 2 This is a flowchart of the functional interface module of the multi-platform compatible test carrier board based on wafer chip mass production testing proposed in this utility model.
[0023] Figure 3 This is a flowchart of the test module portion of the multi-platform compatible test carrier board based on wafer chip mass production testing proposed in this utility model.
[0024] Figure 4 This is a flowchart of the temperature control module of the multi-platform compatible test carrier board based on wafer chip mass production testing proposed in this utility model.
[0025] Figure 5 This is a schematic diagram of a multi-platform compatible test carrier board for wafer chip mass production testing proposed in this utility model.
[0026] The correspondence between the numbers in the attached diagram is as follows:
[0027] 1. Test Carrier Board; 101. Functional Interface Module; 1011. Power Supply Channel Unit; 1012. Digital Channel Unit; 1013. Mixed Signal Unit; 1014. Dedicated Channel Unit for Mixed Signal Testing; 1015. Dedicated Channel Unit for Memory Function Testing; 1016. Relay Switch Control Channel Unit; 102. Test Module; 1021. CP Test Unit; 1022. FT Test Unit; 103. Temperature Monitoring Module; 104. Early Warning Module; 105. Temperature Control Module; 1051. Cooling Unit. Detailed Implementation
[0028] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0029] Reference Figures 1-5 A multi-platform compatible test substrate 1 for wafer chip mass production testing includes a test substrate 1, on which the following are provided:
[0030] Functional interface module 101, which adopts Digital Slot communication interface;
[0031] Test module 102 is connected to functional interface module 101. Test module 102 includes CP test unit 1021 and FT test unit 1022, and CP test unit 1021 and FT test unit 1022 are connected. The CP side-view unit and FT test unit 1022 used by test module 102 are respectively used for chip screening and process monitoring after wafer manufacturing and application performance and reliability verification of packaged chips.
[0032] Temperature monitoring module 103 is used to perform temperature testing on CP test unit 1021 and FT test unit 1022. Temperature monitoring module 103 is set with temperature sensor and is connected to CP test unit 1021 and FT test unit 1022 respectively.
[0033] The early warning module 104 is connected to the temperature monitoring module 103. The early warning module 104 uses an alarm to alert staff when a malfunction occurs.
[0034] Temperature control module 105 is connected to early warning module 104.
[0035] In this embodiment, the functional interface module 101 includes a power supply channel unit 1011, a digital channel unit 1012 connected to the power supply channel unit 1011, a mixed signal unit 1013 connected to the channel unit, a memory function test dedicated channel unit 1015 connected to the mixed signal test dedicated channel unit 1014, and a relay switch control channel unit 1016 connected to the memory function test dedicated channel unit 1015. The power supply channel unit 1011 is connected to the relay switch control channel unit 1016.
[0036] In this embodiment, the power supply channel unit 1011 is connected to the relay switch control channel unit 1016, and the relay switch control channel unit 1016 is connected to the test module 102.
[0037] In this embodiment, the temperature control module 105 includes a cooling unit 1051, which is a heat sink.
[0038] In this embodiment, the early warning module 104 is an alarm, and the early warning module 104 is connected to the temperature monitoring module 103.
[0039] The testing process is performed as follows:
[0040] S1: Select digital channel unit 1012, power supply channel unit 1011, mixed signal unit 1013, mixed signal dedicated test channel unit, memory function test dedicated channel unit 1015, and relay switch control channel unit 1016 to be electrically bridged with the specifications of the chip and test platform.
[0041] S2: Performs CP testing, which tests threshold voltage, on-resistance, leakage current, and the functions of high-speed signals and low-speed digital circuits. It detects the basic functions and performance parameters of each die on the wafer, which can eliminate unqualified dies, reduce the cost of subsequent packaging and testing, and improve yield.
[0042] S3: The initial warning temperature range of the temperature sensor (model: DS18B20) of the temperature monitoring module 103 is set to 20°C to 28°C. When the temperature exceeds the range, the temperature sensor sends a signal to the cooling unit 1051 of the temperature control module 105 and the warning module 104. The heat sink receives the signal and automatically cools down the chip to ensure that it is in the optimal operating temperature state, so as to give full play to the performance of the chip, ensure the accuracy of the test results and the long-term reliability of the chip. The heat sink of the cooling unit 1051 is a water-cooled heat sink (AQUA ELITE 240) to quickly cool down the chip. At the same time, the warning module 104 receives the signal and alerts the staff through the alarm (model: JTW-ZCD-831).
[0043] S4: Perform FT test, apply input signals to the chip function, collect output signals, determine whether the chip meets the design requirements, mark, sort or tape the chip according to the test results, and test logic function, memory read and write function, DC current and voltage parameters, as well as environmental test and aging test.
[0044] S5: During chip testing, the chip itself will heat up. When the temperature exceeds the range value, the temperature sensor sends a signal to the cooling unit 1051 of the temperature control module 105 and the early warning module 104. The heat sink receives the signal and automatically cools down to ensure it is at its optimal operating temperature, fully utilizing the chip's performance and ensuring the accuracy of test results and the long-term reliability of the chip. The heat sink model of the cooling unit 1051 is: (AQUA ELITE) 240) The heat sink rapidly cools the chip, while the early warning module 104 receives the signal and alerts the staff via an alarm (model: JTW-ZCD-831). This embodiment is highly compatible: it can adapt to various test platforms from different manufacturers and models, improving the flexibility and efficiency of chip testing. By recycling the carrier board, resource waste is reduced, production costs are lowered, and the concept of green manufacturing is followed to quickly respond to market changes. The modular design allows the carrier board to quickly adapt to new technologies and standards, shortening the hardware design cycle. Optimized layout and wiring and multi-layer PCB technology ensure the stability and long-term reliability of the carrier board. The test platform is compatible with platforms including but not limited to: J750, J750ex, J750HD, S100, P2, and 3380P.
[0045] All structures in this application can be customized in terms of material and length according to actual usage. The attached drawings are schematic structural diagrams, and the actual dimensions can be adjusted accordingly.
[0046] The above description is only a preferred embodiment of this practice, but the scope of protection of this embodiment is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the scope of the technology disclosed in this embodiment, based on the technical solution and the inventive concept of this embodiment, should be covered within the scope of protection of this embodiment.
Claims
1. A multi-platform compatible test board based on wafer chip production test, comprising a test board, characterized in that, The test board is provided with: a functional interface module; a test module connected with the functional interface module, the test module comprising a CP test unit and an FT test unit, and the CP test unit being connected with the FT test unit; a temperature monitoring module for temperature testing of the CP test unit and the FT test unit, the temperature monitoring module being connected with the CP test unit and the FT test unit respectively; a pre-warning module connected with the temperature monitoring module; a temperature control module connected with the pre-warning module.
2. The multi-platform compatible test board for wafer-chip volume production testing of claim 1, wherein, The functional interface module comprises a power supply channel unit, a digital channel unit connected with the power supply channel unit, a mixed signal unit connected with the channel unit, a Memory function test dedicated channel unit connected with a mixed signal test dedicated channel unit, and a relay switch control channel unit connected with the Memory function test dedicated channel unit, the power supply channel unit being connected with the relay switch control channel unit.
3. The multi-platform compatible test board for wafer-chip volume production testing of claim 2, wherein, The power supply channel unit is connected with the relay switch control channel unit, and the relay switch control channel unit is connected with the test module.
4. The multi-platform compatible test board for wafer-chip volume production testing of claim 1, wherein, The temperature monitoring module is a temperature sensor.
5. The multi-platform compatible test board for wafer-chip volume production testing of claim 1, wherein, The temperature control module comprises a cooling unit, and the cooling unit is a radiator.
6. The multi-platform compatible test board for wafer-chip volume production testing of claim 1, wherein, The pre-warning module is an alarm, and the pre-warning module is connected with the temperature monitoring module.