Full-function reconfigurable digital array radar brick based on SOC chip

Abstract

The utility model provides a full-function reconfigurable digital array radar brick based on an SOC chip, and relates to the technical field of wireless signals. According to the utility model, a framework is composed of full-function independent bricks and comprises a structure installation piece, a digital processing board, a transmitting / receiving digital integrated board, a radio frequency transmitting / receiving board and an antenna unit. Wherein each brick comprises a structure mounting part, a digital processing board, a transmitting / receiving digital integrated board, a radio frequency transmitting / receiving board and an antenna unit, a complete radar front-end function is realized through multi-layer layered architecture integration, and each brick can be matched with a signal processing plug-in box to realize a complete radar; in addition, when two or more full-function reconfigurable digital array radar bricks carry out radar reconstruction, interdigital splicing is carried out through the staggered arrangement structure of the full-function reconfigurable digital array radar bricks; therefore, according to the utility model, the integration level of the sub-array architecture is improved, so that the sub-array architecture has a complete radar front-end function and a flexible system reconstruction capability.

Description

TECHNICAL FIELD

[0001] The utility model relates to wireless signal technical field especially a full function reconfigurable digital array radar brick based on SOC chip. BACKGROUND

[0002] The existing digital array radar adopts modularized subarray architecture to realize, and takes solid-state active phased array and digital array technology as core features.

[0003] The prior art has three significant defects, and these inherent defects seriously restrict the rapid deployment capability and multi-task adaptability of the radar system:

[0004] First, the integration degree of the subarray architecture is limited, and when the analog TR component needs to be integrated, the physical size and weight will be significantly increased, which is difficult to realize compact layout.

[0005] Second, a single subarray does not have complete radar front-end functions and must rely on external antennas, power supplies and signal processing systems to work together.

[0006] Third, the system reconfiguration capability is insufficient, and the existing subarray only supports beam forming reconfiguration at the signal level, and cannot realize radar system level function reconfiguration through physical combination, resulting in the need to redesign the hardware platform for different application scenarios.

[0007] Therefore, it is necessary to provide a full function reconfigurable digital array radar brick based on SOC chip to solve the technical problems of limited integration degree of subarray architecture, no complete radar front-end function and insufficient system reconfiguration capability. SUMMARY

[0008] The utility model aims at overcoming the shortcomings of prior art, provides a full function reconfigurable digital array radar brick based on SOC chip, improves the integration degree of subarray architecture, makes it have complete radar front-end function, and has flexible system reconfiguration capability.

[0009] To achieve the above-mentioned purpose, the application provides a full function reconfigurable digital array radar brick based on SOC chip, which comprises a structure mounting piece, a digital processing board, a transmitting / receiving digital integrated board, a radio frequency transmitting / receiving board and an antenna unit.

[0010] The structure mounting piece comprises a front cover plate, a shielding plate and a back plate, wherein the front cover plate and the back plate are both staggered arrangement structures, the staggered arrangement structure is arranged by a plurality of rectangular areas in the same plane at equal intervals, and the two spaced rectangular areas are arranged in parallel with each other.

[0011] The digital processing board comprises an FPGA chip and a digital processing circuit board; wherein the FPGA chip is arranged on the digital processing circuit board, the digital processing circuit board is arranged in accordance with an equal ratio contraction of an interlaced arrangement structure, and is arranged inside the back plate, and the FPGA chip is electrically connected with the upper computer;

[0012] The transmitting / receiving digital integrated board is composed of multiple digital TR boards; wherein the digital TR board comprises a SOC chip set and a digital integrated circuit board; the digital TR board is arranged in accordance with an equal ratio contraction of a rectangular area, and is arranged inside the digital processing circuit board; the SOC chip set is arranged on the digital integrated circuit board, and is electrically connected with the digital processing board respectively;

[0013] The radio frequency transmitting / receiving board is composed of multiple radio frequency TR boards; wherein the radio frequency TR board is provided with multiple radio frequency transceiving channels, a power supply and a control module; the radio frequency TR board is arranged in accordance with an equal ratio contraction of a rectangular area, is arranged inside the digital TR board, and a shielding plate is arranged in the middle for isolation, and is electrically connected with the corresponding antenna board respectively;

[0014] The antenna unit is composed of multiple antenna boards; wherein the antenna board is arranged in accordance with a rectangular area and is arranged in an interlaced arrangement structure, the front cover plate and the back plate encapsulate the digital processing board, the transmitting / receiving digital integrated board and the radio frequency transmitting / receiving board inside, and the antenna unit is arranged outside the front cover plate.

[0015] As a further solution, the antenna board is arranged by using a patch radiation array element, comprising a top layer PCB board, a first structural adhesive film layer, a PMI foam layer, a second structural adhesive film layer, a bottom layer PCB board, an adhesive film layer and an antenna ground plate arranged in sequence, and the edges are encapsulated by 3M tape, a sealing ring and silicone rubber.

[0016] As a further solution, the radio frequency transceiving channel comprises a transmitting channel, a receiving channel and a switching channel; wherein,

[0017] The transmitting channel comprises a transmitting input interface, a first amplifier and a second amplifier; wherein the transmitting input interface is electrically connected with the first amplifier, the first amplifier is electrically connected with the power supply and the control module and the second amplifier, and the second amplifier is electrically connected with the power supply and the control module;

[0018] The receiving channel comprises a limiter, a low noise amplifier and a receiving output interface; wherein the limiter is electrically connected with the low noise amplifier, and the low noise amplifier is electrically connected with the receiving output interface;

[0019] The switching channel comprises a transceiving switching switch and a filter; wherein the transceiving switching switch is electrically connected with the second amplifier, the amplitude limiter, the filter, the power supply and the control module respectively, and the other end of the filter is electrically connected with the antenna board.

[0020] As a further solution, the power supply and control module comprises a power management module and a control management module; wherein the power management module is set through a power management chip, the control management module is set through an MCU, and the power management module is electrically connected with each radio frequency TR board, digital TR board and digital processing circuit board respectively.

[0021] As a further solution, the SOC chip set comprises a first SOC chip and a second SOC chip, and the digital integrated circuit board comprises a first radio frequency transceiver chip, a second radio frequency transceiver chip and a line-to-board connector; wherein,

[0022] The first SOC chip is electrically connected with the first radio frequency transceiver chip; wherein a bidirectional JESD204B channel 1, a JESD204B channel 2, an SPI*2 channel and a GPIO*10 channel are arranged between the first SOC chip and the first radio frequency transceiver chip, and a unidirectional synchronous signal input channel, a synchronous signal output channel and a reference clock channel are arranged between the first SOC chip and the first radio frequency transceiver chip;

[0023] The second SOC chip is electrically connected with the second radio frequency transceiver chip, and adopts the same electrical connection relationship as that between the first SOC chip and the first radio frequency transceiver chip; the first radio frequency transceiver chip and the second radio frequency transceiver chip are electrically connected with the transmitting channel and the receiving channel of each radio frequency transceiver channel respectively;

[0024] One end of the line-to-board connector is electrically connected with the power supply and control module, the first SOC chip is connected with the I2C interface of the line-to-board connector, and the second SOC chip is connected with the RF_INHB interface, the RF_TX_DRAIN interface and the RF_TXRX_SWITCH interface of the line-to-board connector respectively.

[0025] As a further solution, a clock synchronization adapter and a power adapter are further arranged; wherein the clock synchronization adapter is electrically connected with the FPGA chip, and the power adapter is electrically connected with the power management module.

[0026] As a further solution, when two or more full-function reconfigurable digital array radar bricks are used for radar reconstruction, the interdigital splicing is performed through the staggered arrangement structure of each full-function reconfigurable digital array radar brick, and each clock synchronization adapter is electrically connected with each other, and each power adapter is electrically connected with each other.

[0027] As a further solution, the digital processing circuit board comprises a clock management unit, an Ethernet PHY module, a DDR4 module, a FLASH module, a drive interface chipset module, a digital processing interface group and a high-speed signal transmission interface; wherein,

[0028] The FPGA chip is electrically connected with the Ethernet PHY module, the DDR4 module, the FLASH module and the drive interface chipset module respectively, and the Ethernet PHY module is electrically connected with the high-speed signal transmission interface;

[0029] The clock management unit comprises a CLK clock driver and a clock crystal oscillator; wherein the CLK clock driver is electrically connected with the clock crystal oscillator, the FPGA chip, the high-speed signal transmission interface and the digital processing interface group respectively;

[0030] The high-speed signal transmission interface is provided through a plurality of SEAF8-20 board-to-board connectors, and is electrically connected with the FPGA chip, the drive interface chipset module, the CLK clock driver and the high-speed signal transmission interface respectively;

[0031] The high-speed signal transmission interface comprises an ERF8-035 board-to-board connector and a power connector; wherein the board-to-board connector is electrically connected with the FPGA chip, the CLK clock driver, the SEAF8-20 board-to-board connector and the ERF8-035 board-to-board connector respectively, and the ERF8-035 board-to-board connector is electrically connected with the SEAF8-20 board-to-board connector and the power management module.

[0032] Compared with the related art, the full-function reconfigurable digital array radar brick based on the SOC chip provided by the present application has the following advantages:

[0033] The full-function independent brick architecture of the present application comprises a structure mounting member, a digital processing board, a transmitting / receiving digital integrated board, a radio frequency transmitting / receiving board and an antenna unit; wherein each brick comprises a structure mounting member, a digital processing board, a transmitting / receiving digital integrated board, a radio frequency transmitting / receiving board and an antenna unit, and a complete radar front-end function is realized through multi-layer hierarchical architecture integration, and each brick can be matched with a signal processing plug-in box to realize a complete radar; in addition, when two or more full-function reconfigurable digital array radar bricks are used for radar reconstruction, the interdigital splicing is realized through the staggered arrangement structure of each full-function reconfigurable digital array radar brick; therefore, the present application improves the integration degree of the subarray architecture, so that it has a complete radar front-end function and flexible system reconstruction capability. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application.

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the application or the related art, the accompanying drawings needed to be used in the embodiments or the related art description will be briefly introduced, and obviously, other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0036] Figure 1 A structural schematic diagram of a full-function reconfigurable digital array radar brick based on an SOC chip is provided in the utility model.

[0037] Figure 2 A structural schematic diagram of vertical interconnection is provided in the utility model.

[0038] Figure 3 An external structural schematic diagram of an antenna board is provided in the utility model.

[0039] Figure 4 A structural schematic diagram of a static sealing structure is provided in the utility model.

[0040] Figure 5 An internal interface structural schematic diagram of an antenna board is provided in the utility model.

[0041] Figure 6 A structural schematic diagram of a radio frequency transceiving channel is provided in the utility model.

[0042] Figure 7 A structural schematic diagram of a digital integrated circuit board is provided in the utility model.

[0043] Figure 8 A structural schematic diagram of a digital processing circuit board is provided in the utility model.

[0044] Among them, the reference signs: 1, back plate; 2, digital processing board; 3, digital TR board; 4, radio frequency TR board; 5, shielding plate; 6, front cover plate; 7, antenna unit; 8, clock synchronization adapter; 9, power adapter; 10, vertical interconnection; 11, 3M adhesive tape; 12, top layer PCB board; 13, first structural adhesive film layer; 14, PMI foam layer; 15, second structural adhesive film layer; 16, bottom layer PCB board; 17, adhesive film layer; 18, antenna floor; 19, silicone rubber; 20, sealing ring.

[0045] The purpose implementation, functional characteristics and advantages of the application will be further explained with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be described clearly and completely in combination with the drawings in the embodiments of the utility model below. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. The components of the embodiments of the utility model described and shown in the drawings here can be arranged and designed in various different configurations.

[0047] Please refer to Figure 1 The embodiment of the application provides a full-function reconfigurable digital array radar brick based on an SOC chip, which comprises a structural mounting part, a digital processing plate 2, a transmitting / receiving digital integrated plate, a radio frequency transmitting / receiving plate and an antenna unit 7; wherein,

[0048] The structural mounting part comprises a front cover plate 6, a shielding plate 5 and a back plate 1; wherein the front cover plate 6 and the back plate 1 are both staggered arrangement structures, the staggered arrangement structure is arranged by multiple rectangular areas arranged equidistantly and staggered in the same plane, and the two spaced rectangular areas are arranged in parallel with each other;

[0049] The digital processing plate 2 comprises an FPGA chip and a digital processing circuit board; wherein the FPGA chip is arranged on the digital processing circuit board, the digital processing circuit board is arranged according to the equi-ratio contraction of the staggered arrangement structure, and the digital processing circuit board is arranged inside the back plate 1, and the FPGA chip is electrically connected with the upper computer;

[0050] The transmitting / receiving digital integrated plate is composed of multiple digital TR plates 3; wherein the digital TR plate 3 comprises an SOC chip set and a digital integrated circuit board; the digital TR plate 3 is arranged according to the equi-ratio contraction of the corresponding rectangular area and is arranged inside the digital processing circuit board; the SOC chip set is arranged on the digital integrated circuit board and is electrically connected with the digital processing plate 2 respectively;

[0051] The radio frequency transmitting / receiving plate is composed of multiple radio frequency TR plates 4; wherein the radio frequency TR plate 4 is provided with multiple radio frequency transceiving channels, power supplies and control modules; the radio frequency TR plate 4 is arranged according to the equi-ratio contraction of the corresponding rectangular area, is arranged inside the digital TR plate 3 and the shielding plate 5 is arranged in the middle to isolate, and is electrically connected with the corresponding antenna plate respectively;

[0052] The antenna unit 7 is composed of multiple antenna plates; wherein the antenna plate is arranged according to the corresponding rectangular area and is arranged in the staggered arrangement structure, the front cover plate 6 and the back plate 1 encapsulate the digital processing plate 2, the transmitting / receiving digital integrated plate and the radio frequency transmitting / receiving plate inside, and the antenna unit 7 is arranged outside the front cover plate 6.

[0053] It should be noted that: the embodiment adopts a full-function independent brick structure, each brick contains a structural mount, a digital processing board 2, a transmitting / receiving digital integrated board, a radio frequency transmitting / receiving board and an antenna unit 7, and the complete radar front-end function is realized through multi-layer hierarchical architecture integration; each brick can be matched with a signal processing plug-in box to realize a complete radar, in addition, multiple bricks can be reconfigured to build a new radar, realizing the reconfiguration of radar functions.

[0054] The multi-layer hierarchical architecture is as shown in Figure 1 The hierarchical arrangement between the multiple layers of the brick and the placement order between the layers are designed and optimized multiple times, and are connected through a vertical interconnection 10 structure as shown in Figure 2 The design simultaneously realizes the reduction of inter-board transmission loss, the reduction of electromagnetic compatibility influence and the increase of vibration stability; and can ensure that all board cards and devices are placed in a compact space.

[0055] In a specific embodiment, the antenna board is provided with patch radiating elements, the patch radiating elements are double-patch radiating element structures, and every four radiating elements are packaged into a group and mounted on the front shell of the brick through screw connection. Every four radiating elements packaged into a group should have sufficient structural rigidity and should not be easily damaged.

[0056] In order to ensure that each group of radiating elements and the radio frequency TR board 4 are blind-plugged in place, the front cover plate 6 of the brick is designed with a positioning pin for blind-plugging and positioning of the patch radiating element, and the patch radiating element and the radio frequency TR board 4 are electrically connected by considering a full escapement or half escapement socket adapter with a tolerance of ≤0.1mm.

[0057] Based on the structural vibration resistance, heat conduction and electromagnetic shielding requirements, the radio frequency TR board 4 and the digital TR board 3 are installed with a shielding plate 5 to isolate the two sides, and 8 screws not less than M2.5 specifications are installed on a single board, and are directly installed on the shielding plate 5.

[0058] The digital processing board 2 is directly installed on the back plate 1 of the brick. The radio frequency TR board 4, the digital TR board 3 and the digital processing board 2 are installed as blind-plugging vertical interconnections 10 in the same communication structure; the communication connection preferably has a certain amount of floating plug and socket.

[0059] As shown in Figure 3 The radiating element mounting surface contains four connectors, and on the basis of meeting the waterproof requirement, a static sealing structure of Figure 4 "rectangular groove + shaped filler" is used to reasonably utilize the limited structural space; the waterproof measures between the front cover plate 6 and the back plate 1 are similar to the waterproof measures of the radiating element group structure, and also use the static sealing structure of "rectangular groove + shaped filler".

[0060] As shown in Figure 5As shown, the antenna board includes top layer PCB board 12, first structural adhesive film layer 13, PMI foam layer 14, second structural adhesive film layer 15, bottom layer PCB board 16, adhesive film layer 17 and antenna ground plate 18 arranged in sequence, and is edge-sealed by 3M adhesive tape 11, sealing ring 20 and silicone rubber 19.

[0061] The antenna board processing process mainly involves the following parts: reflector plate processing, printed board processing, printed board and connector welding SMT production line, reflector plate printed board and PMI foam pressing.

[0062] The reflector plate printed board and PMI foam pressing process integrally bonds and forms the printed board and PMI foam in a high-temperature box through adhesive film CF3350 and structural adhesive film AF126-2.

[0063] As shown in Figure 6 The radio frequency transceiving channel includes a transmitting channel, a receiving channel and a switching channel; wherein,

[0064] The transmitting channel includes a transmitting input interface, a first amplifier and a second amplifier; wherein, the transmitting input interface is electrically connected with the first amplifier, the first amplifier is electrically connected with the power supply and control module and the second amplifier, and the second amplifier is electrically connected with the power supply and control module;

[0065] The receiving channel includes a limiter, a low-noise amplifier and a receiving output interface; wherein, the limiter is electrically connected with the low-noise amplifier, and the low-noise amplifier is electrically connected with the receiving output interface;

[0066] The switching channel includes a transceiving switching switch and a filter; wherein, the transceiving switching switch is electrically connected with the second amplifier, the limiter, the filter and the power supply and control module respectively, and the other end of the filter is electrically connected with the antenna board.

[0067] In a specific embodiment, the radio frequency TR board 4 contains four radio frequency transceiving channels; wherein, the receiving channel and the transmitting channel work in time-sharing mode; when the transmitting channel works, the transceiving switching switch selects the transmitting channel, the radio frequency signal sent from the front-stage board card is amplified to more than 10W by two-stage amplifiers, and is transmitted to the rear-end antenna to radiate energy to space through the transceiving switch, and a low-pass filter is designed after the transceiving switch to improve the harmonic suppression capability of the transmitting signal. When the receiving channel works, the transceiving switching switch selects the receiving channel, the signal received by the antenna is sent to the limiter by the selection switch after the filter, and then is amplified by the low-noise amplifier and sent to the rear-stage board card for sampling processing.

[0068] The +48V DC power supplied by the power supply is converted into different voltages by the power supply and control module to provide power supply for the first amplifier, the second amplifier and the low noise amplifier. In order to ensure the time-sharing work of the radio frequency TR board 4, the power supply and control module generates corresponding timing control signals to control the conduction state of the transceiver switching switch; when the transmitting channel works, the control signal is generated to enable the transmitting channel of the transceiver switching switch, and at the same time, the second amplifier is enabled and the low noise amplifier is disabled; when the receiving channel works, the control signal is generated to enable the receiving channel of the transceiver switching switch, and at the same time, the second amplifier is disabled and the low noise amplifier is enabled.

[0069] The power supply and control module includes a power management module and a control management module; wherein the power management module is set by a power management chip, the control management module is set by an MCU, and the power management module is electrically connected with each radio frequency TR board 4, the digital TR board 3 and the digital processing circuit board.

[0070] In use, the control management module can realize temperature monitoring, current and voltage monitoring, and real-time monitoring of the working state of the RF TR board, and transmit state information to the upper system through the I2C or UART communication interface, thereby improving the health management capability of the radio frequency TR board 4.

[0071] As shown in Figure 7 The SOC chip set includes a first SOC chip and a second SOC chip, and the digital integrated circuit board includes a first radio frequency transceiver chip, a second radio frequency transceiver chip and a line-to-board connector; wherein,

[0072] The first SOC chip is electrically connected with the first radio frequency transceiver chip; wherein a bidirectional JESD204B channel 1, a JESD204B channel 2, an SPI*2 channel and a GPIO*10 channel are arranged between the first SOC chip and the first radio frequency transceiver chip, and a unidirectional synchronous signal input channel, a synchronous signal output channel and a reference clock channel are arranged between the first SOC chip and the first radio frequency transceiver chip;

[0073] The second SOC chip is electrically connected with the second radio frequency transceiver chip, and adopts the same electrical connection relationship as the first SOC chip and the first radio frequency transceiver chip; the first radio frequency transceiver chip and the second radio frequency transceiver chip are respectively electrically connected with the transmitting channel and the receiving channel of each radio frequency transceiver channel;

[0074] One end of the line-to-board connector is electrically connected with the power supply and control module, the first SOC chip is connected with the I2C interface of the line-to-board connector, and the second SOC chip is respectively connected with the RF_INHB interface, the RF_TX_DRAIN interface and the RF_TXRX_SWITCH interface of the line-to-board connector.

[0075] The digital TR board 3 takes two pieces of radio frequency SOC chips as the core, mainly completes digital-to-analog conversion of the digital signal from the digital processing board 2; and receives analog-to-digital conversion of the signal from the P1-P8 port. The SOC chip is embedded with a phase-locked loop and a basic signal preprocessing unit, and each piece of radio frequency SOC has two data channels. The two pieces of SOC chips introduce control signals, configuration signals, reference clocks and data signals through the P20 and P21 ports. Therefore, the configuration of the SOC chip is mainly realized through the digital processing board 2.

[0076] The P1-P8 port mainly realizes the reception and transmission of the radio frequency signal. Since the system needs to switch the transceiver switch according to the working mode during operation, the digital TR board 3 provides power supply for the radio frequency TR board 4 through the P9 port and relays the control signal of the digital processing board 2; and designs an I2C interface for uploading the state information of the radio frequency TR board 4.

[0077] As shown in Figure 8 , the digital processing circuit board includes a clock management unit, an Ethernet PHY module, a DDR4 module, a FLASH module, a driving interface chip set module, a digital processing interface group and a high-speed signal transmission interface; wherein,

[0078] The FPGA chip is electrically connected with the Ethernet PHY module, the DDR4 module, the FLASH module and the driving interface chip set module, and the Ethernet PHY module is electrically connected with the high-speed signal transmission interface;

[0079] The clock management unit includes a CLK clock driver and a clock crystal oscillator; wherein the CLK clock driver is electrically connected with the clock crystal oscillator, the FPGA chip, the high-speed signal transmission interface and the digital processing interface group;

[0080] The high-speed signal transmission interface is set through a plurality of SEAF8-20 board-to-board connectors, and is electrically connected with the FPGA chip, the driving interface chip set module, the CLK clock driver and the high-speed signal transmission interface;

[0081] The high-speed signal transmission interface includes an ERF8-035 board-to-board connector and a power connector; wherein the board-to-board connector is electrically connected with the FPGA chip, the CLK clock driver, the SEAF8-20 board-to-board connector and the ERF8-035 board-to-board connector, and the ERF8-035 board-to-board connector is electrically connected with the SEAF8-20 board-to-board connector and the power management module.

[0082] As shown in Figure 1 , a clock synchronization adapter 8 and a power adapter 9 are also provided; wherein the clock synchronization adapter 8 is electrically connected with the FPGA chip, and the power adapter 9 is electrically connected with the power management module.

[0083] When two or more full-function reconfigurable digital array radar bricks are reconfigured into a radar, the interdigitated splicing is realized through the staggered arrangement structure of each full-function reconfigurable digital array radar brick, and each clock synchronization adapter 8 is electrically connected to each other, and each power adapter 9 is electrically connected to each other, so that the power supply is unified and the clock is synchronized.

[0084] The above are only some embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structural transformation made by using the content of the present application specification and drawings, or direct / indirect application in other related technical fields is included in the patent protection scope of the present application.

Claims

1. A full-function reconfigurable digital array radar tile based on an SOC chip, characterized in that, The structure mounting piece, the digital processing plate (2), the transmitting / receiving digital integrated plate, the radio frequency transmitting / receiving plate and the antenna unit (7) are included; wherein, The structure mounting piece includes a front cover plate (6), a shielding plate (5) and a back plate (1); wherein, the front cover plate (6) and the back plate (1) are both staggered arrangement structures, the staggered arrangement structure is arranged by multiple rectangular areas in the same plane equidistantly and staggered, and the two spaced rectangular areas are arranged in parallel with each other; The digital processing plate (2) includes an FPGA chip and a digital processing circuit board; wherein, the FPGA chip is arranged on the digital processing circuit board, the digital processing circuit board is arranged in accordance with the equi-ratio shrinkage of the staggered arrangement structure, and the digital processing circuit board is arranged inside the back plate (1), and the FPGA chip is electrically connected with the upper computer; The transmitting / receiving digital integrated plate is composed of multiple digital TR plates (3); wherein, the digital TR plate (3) includes an SOC chip set and a digital integrated circuit board; the digital TR plate (3) is arranged in accordance with the equi-ratio shrinkage of the corresponding rectangular area and is arranged inside the digital processing circuit board; the SOC chip set is arranged on the digital integrated circuit board and is electrically connected with the digital processing plate (2) respectively; The radio frequency transmitting / receiving plate is composed of multiple radio frequency TR plates (4); wherein, the radio frequency TR plate (4) is provided with multiple radio frequency transceiving channels, power supply and control modules; the radio frequency TR plate (4) is arranged in accordance with the equi-ratio shrinkage of the corresponding rectangular area, is arranged inside the digital TR plate (3) and the shielding plate (5) is arranged in the middle to isolate, and is electrically connected with the corresponding antenna plate respectively; The antenna unit (7) is composed of multiple antenna plates; wherein, the antenna plate is arranged in accordance with the corresponding rectangular area and is arranged in the staggered arrangement structure, the front cover plate (6) and the back plate (1) encapsulate the digital processing plate (2), the transmitting / receiving digital integrated plate and the radio frequency transmitting / receiving plate inside, and the antenna unit (7) is arranged outside the front cover plate (6).

2. The fully functional reconfigurable digital array radar tile based on SOC chip according to claim 1, characterized in that, The antenna plate is arranged by patch radiation elements, including a top layer PCB board (12), a first structural adhesive film layer (13), a PMI foam layer (14), a second structural adhesive film layer (15), a bottom layer PCB board (16), an adhesive film layer (17) and an antenna ground plate (18) arranged in sequence, and the edge is packaged by 3M tape (11), a sealing ring (20) and silicone rubber (19).

3. The fully functional reconfigurable digital array radar tile based on SOC chip according to claim 2, characterized in that, The radio frequency transceiving channel includes a transmitting channel, a receiving channel and a switching channel; wherein, The transmitting channel includes a transmitting input interface, a first amplifier and a second amplifier; wherein, the transmitting input interface is electrically connected with the first amplifier, the first amplifier is electrically connected with the power supply and control module and the second amplifier, and the second amplifier is electrically connected with the power supply and control module; The receiving channel includes a limiter, a low noise amplifier and a receiving output interface; wherein, the limiter is electrically connected with the low noise amplifier, and the low noise amplifier is electrically connected with the receiving output interface; The switching channel comprises a transceiving switching switch and a filter; wherein the transceiving switching switch is electrically connected with the second amplifier, the amplitude limiter, the filter, the power supply and the control module respectively, and the other end of the filter is electrically connected with the antenna board.

4. The fully functional reconfigurable digital array radar tile based on SOC chip according to claim 3, characterized in that, The power supply and control module comprises a power management module and a control management module; wherein the power management module is set by a power management chip, the control management module is set by an MCU, and the power management module is electrically connected with each radio frequency TR board (4), digital TR board (3) and digital processing circuit board respectively.

5. The fully functional reconfigurable digital array radar tile based on SOC chip according to claim 4, characterized in that, The SOC chip set comprises a first SOC chip and a second SOC chip, and the digital integrated circuit board comprises a first radio frequency transceiver chip, a second radio frequency transceiver chip and a line-to-board connector; wherein, The first SOC chip is electrically connected with the first radio frequency transceiver chip; wherein a bidirectional JESD204B channel 1, a JESD204B channel 2, an SPI*2 channel and a GPIO*10 channel are arranged between the first SOC chip and the first radio frequency transceiver chip, and a unidirectional synchronous signal input channel, a synchronous signal output channel and a reference clock channel are arranged between the first SOC chip and the first radio frequency transceiver chip; The second SOC chip is electrically connected with the second radio frequency transceiver chip, and adopts the same electrical connection relationship as that between the first SOC chip and the first radio frequency transceiver chip; the first radio frequency transceiver chip and the second radio frequency transceiver chip are electrically connected with the transmitting channel and the receiving channel of each radio frequency transceiver channel respectively; One end of the line-to-board connector is electrically connected with the power supply and control module, the first SOC chip is connected with the I2C interface of the line-to-board connector, and the second SOC chip is connected with the RF_INHB interface, the RF_TX_DRAIN interface and the RF_TXRX_SWITCH interface of the line-to-board connector respectively.

6. The fully functional reconfigurable digital array radar tile based on SOC chip according to claim 4, characterized in that, A clock synchronization adapter (8) and a power adapter (9) are further arranged; wherein the clock synchronization adapter (8) is electrically connected with the FPGA chip, and the power adapter (9) is electrically connected with the power management module.

7. The fully functional reconfigurable digital array radar tile based on SOC chip according to claim 6, characterized in that, When two or more full-function reconfigurable digital array radar bricks are reconfigured, the interdigital splicing is performed through the staggered arrangement structure of each full-function reconfigurable digital array radar brick, and each clock synchronization adapter (8) is electrically connected with each other, and each power adapter (9) is electrically connected with each other.

8. The fully functional reconfigurable digital array radar tile based on SOC chip according to claim 1, characterized in that, The digital processing circuit board comprises a clock management unit, an Ethernet PHY module, a DDR4 module, a FLASH module, a driving interface chip set module, a digital processing interface group and a high-speed signal transmission interface; wherein, The FPGA chip is electrically connected with the Ethernet PHY module, the DDR4 module, the FLASH module and the driving interface chip set module respectively, and the Ethernet PHY module is electrically connected with the high-speed signal transmission interface; The clock management unit comprises a CLK clock driver and a clock crystal oscillator; wherein the CLK clock driver is electrically connected with the clock crystal oscillator, the FPGA chip, the high-speed signal transmission interface and the digital processing interface group respectively. The high-speed signal transmission interface is arranged through a plurality of SEAF8-20 board-to-board connectors and is electrically connected with the FPGA chip, the driving interface chip set module, the CLK clock driver and the high-speed signal transmission interface respectively. The high-speed signal transmission interface is arranged through an ERF8-035 board-to-board connector and a power connector; wherein the board-to-board connector is electrically connected with the FPGA chip, the CLK clock driver, the SEAF8-20 board-to-board connector and the ERF8-035 board-to-board connector respectively, and the ERF8-035 board-to-board connector is electrically connected with the SEAF8-20 board-to-board connector and the power management module.

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