Low-power-consumption dual-power-supply input circuit
By using a switching circuit instead of diode isolation in a dual-power system, and employing PMOS and NMOS transistors to achieve zero voltage drop and reverse current protection during power switching, the problems of high power loss and temperature rise in existing technologies are solved, achieving low power consumption and high reliability power switching.
Patent Information
- Application Number
- CN202520398334.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-07
- Publication Date
- 2026-02-17
- Estimated Expiration
- 2035-03-07
AI Technical Summary
In existing dual-power supply systems, diode isolation suffers from high power loss, significant temperature rise, and is unsuitable for low-power scenarios.
Switching circuits are used to replace diode isolation. A switching circuit composed of PMOS and NMOS transistors is used to achieve zero voltage drop, reverse current protection and seamless switching of power supply. The power switching process is optimized by combining delay and fast response circuits.
It achieves ultra-low power consumption, reduces power loss by 95%, enables seamless power switching, improves system reliability, and reduces costs by 20%.
Smart Images
Figure CN223928124U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic circuit technology, and in particular to a low-power dual power input circuit for use in dual power supply or multi power supply systems, especially suitable for battery-powered devices, Internet of Things terminals and low-energy electronic products. Background Technology
[0002] In existing dual-power supply systems, diode isolation is commonly used to prevent backflow, but this has the following drawbacks:
[0003] 1. Diodes have a large forward voltage drop (typically 0.7V). For example, at a current of 5A, the power loss of a single diode can be as high as 3.5W.
[0004] 2. Significant temperature rise under high current conditions; actual measurements show that the diode surface temperature can reach over 60℃, affecting system reliability.
[0005] 3. Not suitable for low-power scenarios, such as battery devices where additional losses will significantly shorten battery life.
[0006] Therefore, there is an urgent need for a low-loss, high-reliability dual-power input solution. Utility Model Content
[0007] This invention aims to provide a low-power dual-power input circuit that replaces diode isolation with a switching circuit, achieving zero voltage drop during power switching, reverse current protection, and seamless switching. It is suitable for high-current, low-energy-consumption scenarios. The technical solution is as follows:
[0008] A low-power dual-supply input circuit includes: a first switching circuit, a second switching circuit, and a reverse-current protection circuit;
[0009] The first switching circuit is based on a PMOS transistor and is used to control the on / off state of the first power input terminal to the output terminal. It includes a delay circuit consisting of a resistor R1 and a capacitor C1 to ensure that the output is delayed and shut off when power is lost.
[0010] The second switching circuit is based on a PMOS transistor and is used to control the on / off state of the second power supply input terminal to the output terminal. It includes a fast response circuit composed of resistor R3 and capacitor C4, whose response time is less than the delay time of the delay circuit.
[0011] The anti-backflow circuit is used to forcibly shut off the path between the first power input terminal and the output terminal when the second power input terminal is input, thereby achieving unidirectional isolation.
[0012] Furthermore, the first switching circuit also includes a first PMOS transistor, a second PMOS transistor, and a first switching transistor. The sources of the first PMOS transistor and the second PMOS transistor are connected to the first node, and their gates are connected to the second node. Their drains are connected to the first power input terminal and the power output terminal, respectively. The control terminal of the first switching transistor is connected to the first node through a resistor. When the first switching transistor is turned on, it pulls the second node down to ground, which is used to control the on / off state of the power input terminal to the power output terminal. Resistor R1 and capacitor C1 are connected in parallel, bridging the first node and the second node.
[0013] The second switching circuit includes a third PMOS transistor, a fourth PMOS transistor, a second switching transistor, and a fast response circuit. The drains of the third and fourth PMOS transistors are connected to the third node. The sources are connected to the second power input terminal and the power output terminal, respectively. Resistor R3 and capacitor C4 are connected in parallel, bridging the gate and source of the third PMOS transistor. The gate of the third PMOS transistor is also grounded through a resistor. The control terminal of the second switching transistor is connected to the third node through a resistor, and is used to control the synchronous turn-on / turn-off of the fourth and third PMOS transistors.
[0014] Furthermore, the delay duration of the delay circuit is 1-10ms.
[0015] Furthermore, the on-resistance of the PMOS transistor at 10A is less than 10mΩ.
[0016] Furthermore, the first and second switching transistors are NMOS transistors.
[0017] Furthermore, the anti-backflow circuit includes a third switching transistor; the input terminal of the third switching transistor is the output terminal of the anti-backflow circuit; the output terminal of the third switching transistor is grounded; the control terminal of the third switching transistor is connected to the second power input terminal through a resistor, and is also grounded through a resistor.
[0018] Furthermore, the third switch is an NMOS transistor.
[0019] Technical advantages:
[0020] 1. Ultra-low loss: PMOS on-resistance <10mΩ (@10A current), voltage drop <0.1V, power loss reduced by 95% compared to diode solutions;
[0021] 2. Seamless switching: The delay circuit (C1 = 10μF, R1 = 100kΩ) provides an approximately 1ms turn-off delay to avoid output interruption;
[0022] 3. Low cost: The entire circuit uses common discrete components, and the BOM cost is 20% lower than that of traditional solutions. Attached Figure Description
[0023] Figure 1 This is a circuit block diagram of the low-loss dual-input power supply circuit of this utility model.
[0024] Figure 2 This is the circuit diagram of the low-loss dual-input power supply circuit of this utility model. Detailed Implementation
[0025] To further illustrate the various embodiments, the present invention provides accompanying drawings. These drawings are part of the disclosure of the present invention and are mainly used to illustrate the embodiments, and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementations and the advantages of the present invention. Components in the drawings are not drawn to scale, and similar component symbols are generally used to represent similar components.
[0026] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments.
[0027] like Figure 1 As shown, this utility model provides a low-power dual power input circuit, which consists of a first switching circuit 10, a second switching circuit 20, and an anti-reverse power supply circuit 30.
[0028] The first switching circuit 10 is used to control the on / off state of power supply 1 (POWER IN1) to output terminal (POWER OUT), and includes a delay circuit to ensure that the output is delayed in the event of a power failure.
[0029] The second switching circuit 20 is used to control the on / off state of the power supply 2 (POWER IN2) to the output terminal, and optimizes the response speed through parallel resistors and capacitors (R3, C4).
[0030] The anti-reverse current circuit 30 is used to forcibly shut off the path of power supply 1 (POWER IN1) when power supply 2 (POWER IN2) is input, so as to achieve unidirectional isolation.
[0031] Figure 2 A specific embodiment of a low-power dual-supply input circuit is given. The first switching circuit 10 consists of Q1, Q2, Q5, R1, R4, R5, R12, C1, C2, C3, etc. The second switching circuit consists of Q3, Q4, Q6, R2, R3, R6, R7, R8, R10, C4, etc. The reverse-current protection circuit consists of Q7, R9, R11, C5, C6, etc.
[0032] The circuit connection is explained as follows:
[0033] 1. First switching circuit 10:
[0034] PMOS transistors Q1 and Q2: The source is connected to the first node N1, the gate is connected to the second node N2, and the drain is connected to POWER IN1 and POWER OUT respectively;
[0035] Delay circuit: R1 (100kΩ) and C1 (10μF) are connected in parallel between N1 and the second node N2;
[0036] Control logic: The gate of NMOS transistor Q5 is connected to N1 through R4 (10kΩ) and grounded through R12 (1kΩ).
[0037] 2. Second switching circuit 20:
[0038] PMOS transistors Q3 and Q4: The drains are connected to the fourth node N4, and the sources are connected to POWER IN2 and POWER OUT respectively;
[0039] Fast response circuit: R3 (5kΩ) and C4 (1μF) are connected in parallel between the gate of Q3 and POWER IN2.
[0040] 3. Anti-reverse current circuit 30:
[0041] NMOS transistor Q7: The gate is connected to POWER IN2 through R9 (20kΩ) and grounded through R11 (5kΩ);
[0042] Output control: Q7 drain is connected to Q5 gate, forcibly pulling its voltage down to 0V to turn off Q1 / Q2.
[0043] The resistance and capacitance values mentioned above are reference values and can be adjusted as needed.
[0044] The following provides a further explanation of the circuit's operating logic.
[0045] 1. Power Supply Mode 1:
[0046] When POWER IN1 receives a 12V input, Q5 turns on, causing Q1 / Q2 to turn on, and POWER OUT outputs 12V. If POWER IN1 loses power, C1 discharges through R1, and Q1 and Q2 turn off after a 1ms delay.
[0047] 2. Power supply mode 2:
[0048] When POWER IN2 inputs 12V, Q7 turns on, causing the gate voltage of Q5 to be pulled down to 0V, forcibly turning off Q1 / Q2;
[0049] Q3 / Q4 are quickly turned on via R3-C4, and POWER OUT switches to power supply 2 (switching time <0.5ms).
[0050] 3. Anti-backflow function:
[0051] When there is no input to POWER IN1, Q4 is cut off because there is no voltage at its source, thus blocking reverse current.
[0052] When there is no input to POWER IN2, Q7 is turned off, and the power supply path 1 returns to normal.
[0053] It should be noted that the response time of the fast response circuit and the delay time of the delay circuit can be set as needed, but the response time of the fast response circuit must be less than the delay time of the delay circuit to avoid discontinuous output during power switching, which could cause the back-end system to shut down and crash.
[0054] Since the on-state voltage drop (@10A) of the PMOS transistor is less than 0.1V and the power loss (@10A) is less than 0.1W, while the on-state voltage drop (@10A) of the diode is 0.7V and the power loss (@10A) reaches 7W, the power loss of this circuit is reduced by 95% compared with the diode solution, achieving ultra-low power consumption.
[0055] It should be noted that Q5, Q6, and Q7 are preferably NMOS transistors for low loss, but NPN transistors and other semiconductor switching devices can also be used.
[0056] This circuit also has the advantage of low cost: the entire circuit uses general-purpose discrete components, and the BOM cost is 20% lower than that of traditional solutions.
[0057] Although the present invention has been specifically shown and described in conjunction with preferred embodiments, those skilled in the art should understand that various changes in form and detail may be made to the present invention without departing from the spirit and scope of the present invention as defined in the appended claims, and all such changes shall be within the scope of protection of the present invention.
Claims
1. A low power consumption dual power supply input circuit, characterized by comprising: Comprise: The first switch circuit, the second switch circuit and the anti-reflux circuit; The first switch circuit based on PMOS tube, for controlling the conduction / off of the first power input to the output, containing the delay circuit composed of resistor R1 and capacitor C1, to ensure that the output delay closes when power failure; The second switch circuit based on PMOS tube, for controlling the conduction / off of the second power input to the output, including the fast response circuit composed of resistor R3 and capacitor C4, which responds for less than the delay time of the delay circuit; The anti-reflux circuit is used to force the path of the first power input and the output to be closed when the second power input is input, realizing one-way isolation.
2. The low-power double power input circuit of claim 1, wherein: The first switch circuit further comprises a first PMOS tube, a second PMOS tube and a first switch tube, the source of the first PMOS tube and the second PMOS tube is connected to the first node, the gate is connected to the second node, and the drain is connected to the first power input and the power output respectively; The control end of the first switch tube is connected to the first node through a resistor, which pulls down the second node to ground when it is turned on, for controlling the conduction / off of the first power input to the power output; Resistor R1 and capacitor C1 are connected in parallel across the first node and the second node; The second switch circuit comprises a third PMOS tube, a fourth PMOS tube, a second switch tube and a fast response circuit, the drains of the third PMOS tube and the fourth PMOS tube are connected to the third node; The source is connected to the second power input and the power output respectively; Resistor R3 and capacitor C4 are connected in parallel across the gate and source of the third PMOS tube; The gate of the third PMOS tube is also connected to ground through a resistor; The control end of the second switch tube is connected to the third node through a resistor, for controlling the synchronous conduction / off of the fourth PMOS tube and the third PMOS tube.
3. The low power dual supply input circuit of claim 2, wherein: The delay time of the delay circuit is 1-10ms.
4. The low power dual supply input circuit of claim 2, wherein: The on-resistance of the PMOS tube is less than 10mΩ at 10A.
5. The low power dual supply input circuit of claim 2, wherein: The first switch tube and the second switch tube are NMOS tubes.
6. The low power dual supply input circuit of claim 1, wherein: The anti-reflux circuit comprises a third switch tube; The input end of the third switch tube is the output end of the anti-reflux circuit; The output end of the third switch tube is connected to ground; The control end of the third switch tube is connected to the second power input through a resistor and connected to ground through a resistor.
7. The low power dual supply input circuit of claim 6, wherein: The third switch tube is an NMOS tube.