Display device

Abstract

The utility model relates to a display device. The display device includes a display panel including a display area defined therein. The display panel comprises a pixel and a first sensor, the pixel comprises a pixel driving circuit and a light-emitting element, and the first sensor comprises a first sensor driving circuit and a first sensing element. Wherein the first sensing element includes a first electrode electrically connected to the first sensor driving circuit, a semiconductor layer electrically disconnected from the first electrode, and a second electrode electrically connected to the semiconductor layer, and the light emitting element is electrically connected to the pixel driving circuit and the second electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0036858, filed on March 18, 2024, and all benefits arising therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of this disclosure relate to a display device with improved sensing reliability. Background Technology

[0004] Display devices display images to provide information to users or provide various functions that enable organic communication with users, such as sensing user input. Recently, display devices have typically included functions for sensing information provided by the user (e.g., biometric information). Furthermore, display devices may also include functions for sensing the illuminance of the surrounding environment. That is, display devices include sensors for sensing fingerprints and / or illuminance. In such display devices, capacitive methods for sensing changes in electrostatic capacitance provided between electrodes, optical methods for sensing incident light using optical sensors, or ultrasonic methods for sensing vibrations using piezoelectric elements can be used as user information identification methods. Utility Model Content

[0005] Embodiments of this disclosure provide a display device with improved sensing reliability.

[0006] An embodiment of the present invention provides a display device, which includes a display panel and a display area defined therein. The display panel includes pixels and a first sensor. The pixels include a pixel driving circuit and a light-emitting element. The first sensor includes a first sensor driving circuit and a first sensing element. The first sensing element includes a first electrode electrically connected to the first sensor driving circuit, a semiconductor layer electrically disconnected from the first electrode, and a second electrode electrically connected to the semiconductor layer. The light-emitting element is electrically connected to the pixel driving circuit and the second electrode.

[0007] In an embodiment, the display panel may further include a second sensor, which includes a second sensor driving circuit and a second sensing element different from the first sensing element. A first area and a second area adjacent to the first area may be defined in the display area, and the second sensor may be disposed in the first area.

[0008] In an embodiment, the second sensing element may include a first electrode electrically connected to the second sensor driving circuit, a semiconductor layer electrically connected to the first electrode of the second sensing element, and a second electrode electrically connected to the semiconductor layer of the second sensing element.

[0009] In an embodiment, the first sensor can be disposed in the second area.

[0010] In an embodiment, the second sensor driving circuit can include: a second reset transistor including a gate electrode receiving a reset control signal, a first electrode receiving a first reset voltage, and a second electrode connected to a first sensing node therein; a second amplification transistor including a first electrode receiving a sensor driving voltage, a second electrode connected to a second sensing node therein, and a gate electrode connected to the first sensing node therein; and a second output transistor including a first electrode connected to the second sensing node therein, a second electrode connected to a readout line, and a gate electrode receiving an output control signal.

[0011] In an embodiment, the first sensor driving circuit can include: a first reset transistor including a gate electrode receiving a reset control signal, a first electrode, and a second electrode connected to a first sensing node therein; a first amplification transistor including a first electrode receiving a sensor driving voltage, a second electrode connected to a second sensing node therein, and a gate electrode connected to the first sensing node therein; and a first output transistor including a first electrode connected to the second sensing node therein, a second electrode connected to a readout line, and a gate electrode receiving an output control signal.

[0012] In an embodiment, a first reset voltage having a different voltage level from the first reset voltage can be provided to the first electrode of the first reset transistor.

[0013] In an embodiment, a second reset voltage having a different voltage level from the first reset voltage can be provided to the first electrode of the first reset transistor.

[0014] In an embodiment, the first sensor driving circuit can include: a first amplification transistor including a first electrode receiving a sensor driving voltage, a second electrode connected to a second sensing node therein, and a gate electrode receiving a second reset voltage having a different voltage level from the first reset voltage; and a first output transistor including a first electrode connected to the second sensing node therein, a second electrode connected to a readout line, and a gate electrode receiving an output control signal.

[0015] In an embodiment, the display device can further include an anti-reflection layer disposed on the display panel, wherein the anti-reflection layer includes: a black matrix layer having a first opening overlapping the light emitting element therein when viewed in a plan view; and a color filter layer disposed on the first opening.

[0016] In an embodiment, a second opening overlapping the second sensing element can be defined in the black matrix layer when viewed in a plan view.

[0017] In one implementation, when viewed in a plan view, a third opening overlapping the first sensing element may be defined in the black matrix layer.

[0018] In one implementation, the black matrix layer may overlap with the first sensing element when viewed in a plan view.

[0019] In an implementation, the first region may include a first-first region and a second-first region disposed between the first-first region and the second region. A second opening overlapping with the second sensing element may be defined in the black matrix layer in the first-first region, and the black matrix layer may overlap with the second sensing element in the second-first region.

[0020] In one implementation, a third region adjacent to the first and second regions may be defined in the display area, and each of the first and second sensors may be spaced apart from the third region.

[0021] In an embodiment of this utility model, the display device includes: a base layer; a circuit layer disposed on the base layer and including a pixel driving circuit and a first sensor driving circuit; an element layer disposed on the circuit layer and including a light-emitting element, a first sensing element and a pixel defining layer; and an encapsulation layer disposed on the element layer, wherein the first sensing element includes a first electrode disposed on the circuit layer and covered by the pixel defining layer, a semiconductor layer disposed on the pixel defining layer, and a second electrode covering the semiconductor layer.

[0022] In one implementation, a first region and a second region adjacent to the first region may be defined in the base layer, and a first sensor driving circuit and a first sensing element may be disposed in the second region.

[0023] In an implementation, the first sensor driving circuit may include: a first reset transistor, including a gate electrode for receiving a reset control signal, a first electrode, and a second electrode connected thereto to a first sensing node; a first amplification transistor, including a first electrode for receiving a sensor driving voltage, a second electrode connected thereto to a second sensing node, and a gate electrode connected thereto to the first sensing node; and a first output transistor, including a first electrode connected thereto to the second sensing node, a second electrode connected to a readout line, and a gate electrode for receiving an output control signal.

[0024] In one implementation, a first reset voltage may be provided to the first electrode of the first reset transistor.

[0025] In an implementation, the first sensor driving circuit may include: a first amplifying transistor, including a first electrode for receiving a sensor driving voltage, a second electrode connected thereto to a second sensing node, and a gate electrode for receiving a second reset voltage; and a first output transistor, including a first electrode connected thereto to the second sensing node, a second electrode connected to a readout line, and a gate electrode for receiving an output control signal. Attached Figure Description

[0026] The above and other features of the present invention will become more apparent from the accompanying drawings, which describe the embodiments of the present invention in further detail with reference to the drawings:

[0027] Figure 1 This is a perspective view of a display device according to an embodiment of the present invention;

[0028] Figure 2 This is a cross-sectional view showing a portion of a display device according to an embodiment of the present invention;

[0029] Figure 3 This is a block diagram of a display device according to an embodiment of the present invention;

[0030] Figure 4 This is a plan view of the display area of ​​the display panel according to an embodiment of the present invention;

[0031] Figure 5A It is according to the embodiments of this utility model along Figure 4 A cross-sectional view of the display device taken by line I-I';

[0032] Figure 5B This is an equivalent circuit diagram of the pixel and the first sensor according to an embodiment of the present invention;

[0033] Figure 6A It is according to the embodiments of this utility model along Figure 4 A cross-sectional view of the display device taken by line II-II';

[0034] Figure 6B This is an equivalent circuit diagram of the pixel and the second sensor according to an embodiment of the present invention;

[0035] Figure 7 According to another embodiment of this utility model, along Figure 4 A cross-sectional view of the display device taken by line I-I';

[0036] Figure 8 This is a plan view of the display area of ​​the display panel according to an embodiment of the present invention;

[0037] Figure 9AIt is according to the embodiments of this utility model along Figure 8 A cross-sectional view of the display device taken by line III-III';

[0038] Figure 9B This is an equivalent circuit diagram of the pixel and the second sensor according to an embodiment of the present invention;

[0039] Figure 10 This is a plan view of the display area of ​​the display panel according to an embodiment of the present invention;

[0040] Figure 11 This is an equivalent circuit diagram of the pixel and the first sensor according to an embodiment of the present invention; and

[0041] Figure 12 This is an equivalent circuit diagram of the pixel and the first sensor according to an embodiment of the present invention. Detailed Implementation

[0042] The present invention will now be described more fully with reference to the accompanying drawings, in which various embodiments are illustrated. However, the present invention may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0043] It will be understood that when an element or layer is referred to as being "on," "connected to," or "attached to" another element or layer, it may be directly on, directly connected to, or directly attached to the other element or layer, or there may be an intervening third element or layer between them. Conversely, when an element is referred to as being "directly" on another element, there is no intervening element.

[0044] The same reference numerals in the accompanying drawings denote the same elements. Furthermore, in order to effectively depict the technical content, the thickness, proportions, and dimensions of the elements have been exaggerated in the drawings.

[0045] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0046] Furthermore, terms such as “below,” “lower,” “upper,” and “upper” are used to explain the relationships between the items shown in the accompanying drawings. These terms are used as relative concepts and are described with reference to the directions shown in the accompanying drawings.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. Thus, reference to “a” followed by “the” in a claim includes one element and multiple elements. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” or “containing” and / or “comprising” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0048] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, it will be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly stated herein.

[0049] Embodiments are described herein with reference to cross-sectional views, which are schematic representations of idealized embodiments. Therefore, variations in the shapes depicted in the figures will be anticipated due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include shape deviations, for example, due to manufacturing processes. For instance, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0050] In the following description, embodiments of the present invention will be described with reference to the accompanying drawings.

[0051] Figure 1 This is a perspective view of a display device according to an embodiment of the present invention.

[0052] refer to Figure 1 The display device DD can be implemented as a mobile phone, tablet computer, vehicle, navigator, gaming device, or wearable device, but is not limited thereto. Figure 1 The image shows an example of a display device DD being a mobile phone.

[0053] exist Figure 1 The illustration shows an embodiment where the display device DD is a rigid, bar-shaped display device, but is not limited thereto. In another embodiment, for example, the display device DD may be of a foldable, rollable, or slidable type.

[0054] The top surface of the display device DD can be defined as a display surface IS, and the display surface IS can lie on a plane defined by a first direction DR1 and a second direction DR2. The image IM generated in the display device DD can be provided to the user through the display surface IS.

[0055] In the following text, the normal direction that is substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. The third direction DR3 may be the thickness direction. In this specification, "when viewed in a plan view" may mean the state of being viewed in the third direction DR3. That is, the plane may be parallel to the surface defined by the first direction DR1 and the second direction DR2.

[0056] In this embodiment, the display surface IS can be divided into a transmissive region TA and a border region BZA. The transmissive region TA is the area in which the image IM is displayed. No image is displayed in the border region BZA. The user views the image IM through the transmissive region TA. In this embodiment, as... Figure 1 As shown, the transmission region TA can be a rectangular shape with rounded edges. However, this is merely an example, and the transmission region TA can have various shapes such as rectangular, circular, or square, and is not limited to any one embodiment.

[0057] The border region BZA is adjacent to the transmission region TA. The border region BZA may have a specified color. In one embodiment, the border region BZA may surround the transmission region TA. Therefore, the shape of the transmission region TA may be substantially defined by the border region BZA. However, this is only an example. In another embodiment, the border region BZA may be configured to be adjacent only to one side of the transmission region TA, or it may be omitted.

[0058] The display device DD can detect external input applied from the outside. External input can include various types of input provided from outside the display device DD. In embodiments, for example, external input can include external input applied at a predetermined distance near or adjacent to the display device DD (e.g., hover input) and touch input using a user's body part US_F. Furthermore, external input can be of various types, such as force, pressure, temperature, or light. External input can be provided by a separate device, such as an active pen or digitizer pen. Additionally, the display device DD can detect the user's biometric information applied from the outside or measure the brightness of the surrounding environment.

[0059] The appearance of the display device DD can consist of a window WM and a housing EDC. In an embodiment, for example, the window WM and the housing EDC can be combined with each other, and other components of the display device DD, such as the display module, can be housed therein.

[0060] The front surface of the window WM defines the display surface IS of the display device DD. The window WM may include an optically transparent insulating material. In embodiments, for example, the window WM may include glass or plastic. The window WM may have a multilayer structure or a single-layer structure. In embodiments, for example, the window WM may include multiple plastic films bonded with an adhesive, or it may include a glass substrate and plastic films bonded with an adhesive.

[0061] The housing EDC can comprise a material with relatively high rigidity. For example, the housing EDC can comprise multiple frames and / or plates, which include glass, plastic, metal, or combinations thereof. The housing EDC can stably protect the components housed within the display device DD from external impacts. Although not shown in the figures, a battery module or the like configured to provide power for the overall operation of the display device DD can be disposed between the display module and the housing EDC.

[0062] Figure 2 This is a cross-sectional view showing a portion of a display device according to an embodiment of the present invention.

[0063] refer to Figure 2 The implementation of the display device DD may include a display panel DP, a sensor layer SL, and an anti-reflective layer RPL.

[0064] The display panel DP can be configured to essentially generate an image IM (see [link]). Figure 1 The display panel DP can be an emitting display panel, such as an organic light-emitting display panel, an inorganic light-emitting display panel, an organic-inorganic light-emitting display panel, a quantum dot display panel, a micron-sized light-emitting diode (LED) display panel, or a nano-LED display panel. In the following description, for ease of description, the display panel DP will primarily be described as an embodiment of an organic light-emitting display panel, but it is not limited thereto.

[0065] The display panel DP may include a base layer BL, a pixel layer PXL, and a packaging layer TFE. According to embodiments of the present invention, the display panel DP may be a flexible display panel or a rigid display panel. In embodiments, for example, the display panel DP may be a foldable display panel that folds around a folding axis, a rollable display panel that at least a portion of which is rolled around a roll axis, or a slidable display panel.

[0066] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, but the material is not particularly limited. Furthermore, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate, etc.

[0067] The pixel layer PXL can be set on the base layer BL. The pixel layer PXL can include the circuit layer DP_CL and the component layer DP_ED.

[0068] The circuit layer DP_CL is disposed between the base layer BL and the component layer DP_ED. The circuit layer DP_CL includes at least one insulating layer and circuit elements. Hereinafter, the insulating layer included in the circuit layer DP_CL is referred to as the intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film.

[0069] Circuit elements may include pixel drive circuitry (PDC) (see Figure 5B ) and the first sensor driving circuit O_SD1 (see Figure 5B ) and the second sensor driving circuit O_SD2 (see Figure 6B ), Pixel driver circuit PDC (see Figure 5B ) includes multiple pixels (PX) used to display the image (see Figure 3 In each of the following, the first sensor drive circuit O_SD1 (see...) Figure 5B ) and the second sensor driving circuit O_SD2 (see Figure 6B This includes multiple sensors FX used to identify external information (see...) Figure 3 The circuit layer DP_CL can also include connections to the pixel driver circuit PDC (see...). Figure 5B ) and / or the first sensor drive circuit O_SD1 (see Figure 5B ) and the second sensor driving circuit O_SD2 (see Figure 6B The signal lines of the sensors FX may be located in the second region AR2 (see [link]). In an implementation, the multiple sensors FX may include those located in the second region AR2 (see [link]). Figure 4 The first sensor FX1 in ) (see Figure 4 ) and set in the first area AR1 (see Figure 4 The second sensor FX2 in ) (see Figure 4), and the description will be provided below.

[0070] The element layer DP_ED can include light-emitting elements ED contained in each of multiple pixels PX (see [link to ED]). Figure 5B ) and the first sensing element OPD1 contained in multiple sensors FX (see Figure 5A ) and the second sensing element OPD2 (see Figure 6A In an implementation, for example, the first sensing element OPD1 (see...) Figure 5A ) and the second sensing element OPD2 (see Figure 6A Each of these can be a photodiode, such as an organic photodiode. The second sensing element, OPD2 (see...). Figure 6A This can be a sensor configured to detect light reflected from a user's fingerprint or to react to light reflected from a user's fingerprint. The circuit layer DP_CL and the component layer DP_ED will be described in more detail below.

[0071] A TFE (Transmission Electrode Interior) layer is disposed on the DP_ED component layer to encapsulate the DP_ED component layer. The TFE layer may include at least one inorganic film and at least one organic film. The inorganic film may include inorganic materials and protects the DP_ED component layer from moisture / oxygen. The inorganic film may include, but is not particularly limited to, silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, etc. The organic film may include organic materials and protects the DP_ED component layer from foreign matter such as dust particles.

[0072] The sensor layer SL can be disposed on the display panel DP. The sensor layer SL can be disposed or formed on the display panel DP through a continuous process, but this invention is not limited thereto. The sensor layer SL can sense externally input coordinates.

[0073] An anti-reflective layer (RPL) can be applied to the sensor layer (SL). The RPL reduces the reflectivity of external light incident from the outside.

[0074] The antireflective layer RPL may include a color filter layer CF (see Figure 5A ), Black Matrix Layer BM (see Figure 5A ) and planarization layer. Color filter layer CF (see Figure 5A ( ) can have a specified array. In an implementation, for example, a color filter layer CF (see Figure 5A The anti-reflective layer RPL can be arranged according to the emission colors of the pixels included in the display panel DP. In another embodiment, the anti-reflective layer RPL may include a black matrix layer BM (see...). Figure 5AThe anti-reflective layer RPL selectively absorbs light reflected from inside the display panel DP and / or electronic device, or light incident from outside the display panel DP and / or electronic device, in a specific frequency band. In another embodiment, the anti-reflective layer RPL may be a polarizing film.

[0075] Figure 3 This is a block diagram of a display device according to an embodiment of the present invention.

[0076] refer to Figure 3 The implementation of the display device DD includes a display panel DP, a panel driver (or driving circuit), and a driving controller 100. In an implementation, for example, the panel driver includes a data driver 200, a scan driver 300, a transmit driver 350, a voltage generator 400, and a readout circuit 500.

[0077] The display panel DP may include a corresponding transmissive area TA (see...). Figure 1 The display area DA and the corresponding border area BZA (see) Figure 1 The non-display area NDA.

[0078] The display panel DP may include a plurality of pixels PX disposed in the display area DA and a plurality of sensors FX disposed in the display area DA. In one embodiment, for example, each of the plurality of sensors FX may be disposed between two adjacent pixels PX. The plurality of pixels PX and the plurality of sensors FX may be alternately disposed in a first direction DR1 and a second direction DR2. However, the embodiments of the present invention are not limited thereto. In another embodiment, two or more pixels PX may be disposed between two adjacent sensors FX disposed in the first direction DR1, or between two adjacent sensors FX disposed in the second direction DR2.

[0079] The display panel DP also includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, transmit control lines EML1 to EMLn, data lines DL1 to DLm, and readout lines RL1 to RLh. Here, n, m, and h are integers greater than 2.

[0080] Initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, and transmit control lines EML1 to EMLn extend in the second direction DR2. The initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, and transmit control lines EML1 to EMLn are spaced apart from each other in the first direction DR1. Data lines DL1 to DLm and readout lines RL1 to RLh extend in the first direction DR1 and are spaced apart from each other in the second direction DR2.

[0081] Multiple pixels PX are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, transmit control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. In an embodiment, for example, each of the multiple pixels PX may be electrically connected to four scan lines. However, the number of scan lines connected to each of the pixels PX is not limited to this and can be varied.

[0082] Multiple sensors FX are electrically connected to readout lines RL1 to RLh, respectively. One sensor FX can be electrically connected to a scan line, for example, one of the write scan lines SWL1 to SWLn. However, embodiments of this invention are not limited thereto. The number of scan lines connected to each of the sensors FX can be varied.

[0083] In one embodiment, for example, the number of read lines RL1 to RLh may correspond to half the number of data lines DL1 to DLm. However, the embodiments of this invention are not limited to this. Alternatively, the number of read lines RL1 to RLh may correspond to approximately 1 / 4 or approximately 1 / 8 of the number of data lines DL1 to DLm.

[0084] The drive controller 100 receives an image signal RGB and a control signal CTRL. The drive controller 100 generates an image data signal DATA with a converted RGB data format to meet the interface specifications with the data driver 200. The drive controller 100 can output a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal RCS based on the control signal CTRL.

[0085] The data driver 200 can receive a third control signal DCS and an image data signal DATA from the drive controller 100. The data driver 200 converts the image data signal DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm, which will be described below. The data signal has an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0086] The scan driver 300 receives a first control signal SCS from the drive controller 100. The scan driver 300 can output scan signals to the scan lines in response to the first control signal SCS. In one embodiment, for example, in response to the first control signal SCS, the scan driver 300 outputs initialization scan signals to the initialization scan lines SIL1 to SILn and compensated scan signals to the compensated scan lines SCL1 to SCLn. Furthermore, in response to the first control signal SCS, the scan driver 300 can output write scan signals to the write scan lines SWL1 to SWLn and black scan signals to the black scan lines SBL1 to SBLn.

[0087] The scan driver 300 can be located in the non-display area NDA of the display panel DP. However, the implementation is not limited to this. In some implementations, for example, at least a portion of the scan driver 300 can also be located in the display area DA.

[0088] Transmit driver 350 can be located in the non-display area NDA of the display panel DP. Transmit driver 350 receives a second control signal ECS from drive controller 100. In response to the second control signal ECS, transmit driver 350 can output transmit control signals to transmit control lines EML1 to EMLn. Alternatively, scan driver 300 can be connected to transmit control lines EML1 to EMLn. In this case, transmit driver 350 can be omitted, and scan driver 300 can output transmit control signals to transmit control lines EML1 to EMLn.

[0089] Voltage generator 400 generates the voltages required for the operation of the display panel DP. In this embodiment, voltage generator 400 generates a first drive voltage ELVDD, a second drive voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, and a reset voltage Vrst. The reset voltage Vrst may include the first reset voltage Vrst1 (see...). Figure 5B ) and a second reset voltage Vrst2 having a different voltage level than the first reset voltage Vrst1 (see Figure 11 A detailed description will be provided below.

[0090] The readout circuit 500 receives a fourth control signal RCS from the drive controller 100. In response to the fourth control signal RCS, the readout circuit 500 receives sensing signals from readout lines RL1 to RLh. The readout circuit 500 processes the sensing signals and noise signals received from readout lines RL1 to RLh and provides the processed sensing signal S_FS and the processed noise signal S_NS to the drive controller 100. The processed noise signal S_NS can be referred to as the noise-processed signal. The noise-processed signal S_NS can be obtained by processing the signal in the first sensor drive circuit O_SD1 (see...). Figure 5B The noise signal NSd generated in ) (see Figure 5B The signal obtained is from this.

[0091] The readout circuit 500 can provide a reset control signal RST to the sensor FX via the reset control line RCL. In an embodiment, for example, the reset control signal RST can be provided to the reset transistor ST1 of the sensor FX (see...). Figure 5B To turn on the reset transistor ST1.

[0092] Figure 4 This is a plan view of the display area of ​​a display panel according to an embodiment of the present invention. In the description... Figure 4 When implementing the method, for Figure 3 The same elements shown are given the same reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0093] refer to Figure 4 In this implementation, the display area DA may include a first area AR1 and a second area AR2. When viewed in a plan view or on a third-direction DR3, the base layer BL may overlap with the display area DA. The display area DA may be defined within the base layer BL. The first area AR1 and the second area AR2 may be defined within the base layer BL.

[0094] Multiple second regions AR2 can be configured. One of the multiple second regions AR2 can be located adjacent to the first region AR1 in a direction opposite to the second direction DR2. Another of the multiple second regions AR2 can be located adjacent to the first region AR1 in the second direction DR2. In such an implementation, the first region AR1 can be located among the multiple second regions AR2.

[0095] Multiple pixel PX and multiple second sensor FX2 can be set in the first area AR1.

[0096] Multiple pixel PX and multiple first sensor FX1 can be set in the second area AR2.

[0097] Figure 5AIt is according to the embodiments of this utility model along Figure 4 A cross-sectional view of the display device taken by line I-I'. In the description Figure 5A When implementing the method, for Figure 2 The same elements shown are given the same reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0098] refer to Figure 5A The implementation of the display device DD may include a display panel DP, a sensor layer SL, and an anti-reflective layer RPL. The display panel DP may include a base layer BL, a circuit layer DP_CL, a component layer DP_ED, and a package layer TFE.

[0099] At least one inorganic layer is disposed on the top surface of the base layer BL. The inorganic layer may include at least one selected from alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be configured to have multiple layers or a multilayer structure. The multilayer inorganic layer may include barrier layers BR1 and BR2 and / or buffer layer BFL, as described below. The barrier layers BR1 and BR2 and the buffer layer BFL may be optionally provided or omitted.

[0100] Barrier layers BR1 and BR2 effectively prevent foreign objects from entering from the outside. Each of barrier layers BR1 and BR2 may include a silicon oxide layer and a silicon nitride layer. Multiple barrier layers BR1 and BR2 may be provided, and the silicon oxide layer and the silicon nitride layer may be stacked alternately on top of each other.

[0101] Barrier layers BR1 and BR2 may include a first barrier layer BR1 and a second barrier layer BR2. A first rear surface metal layer BMC1 may be disposed between the first barrier layer BR1 and the second barrier layer BR2. In embodiments of this invention, the first rear surface metal layer BMC1 may be omitted.

[0102] A buffer layer BFL can be disposed on barrier layers BR1 and BR2. The buffer layer BFL can enhance the adhesion between the base layer BL and the semiconductor pattern and / or conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer can be stacked alternately on top of each other.

[0103] A first semiconductor pattern may be disposed on the buffer layer BFL. The first semiconductor pattern may include a silicon semiconductor. In an embodiment, for example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. In an embodiment, for example, the first semiconductor pattern may include low-temperature polycrystalline silicon.

[0104] Figure 5AOnly a portion of the first semiconductor pattern is shown disposed on the buffer layer BFL, and another portion of the first semiconductor pattern may be disposed in another region. The first semiconductor pattern may be arranged across a pixel in a specific pattern. The first semiconductor pattern may have different electrical characteristics depending on whether it is doped. The first semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with N-type or P-type dopant. A P-type transistor includes a doped region doped with P-type dopant, and an N-type transistor includes a doped region doped with N-type dopant. The second region may be an undoped region or doped at a lower concentration than the first region.

[0105] The first region can have a higher conductivity than the second region and is essentially used as an electrode or signal line. The second region can essentially correspond to the active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern can be the active region of a transistor, another portion can be the source or drain, and yet another portion can be a connecting electrode or a connecting signal line.

[0106] The first electrode S1, the channel unit A1, and the second electrode D1 of the first transistor T1 are provided by (or defined by a portion of) a first semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 extend from the channel unit A1 in opposite directions.

[0107] Figure 5A A portion of the connection signal line CSL electrically connected to the first semiconductor pattern is shown. Although not shown separately, the connection signal line CSL can be connected to the fifth transistor T5 in the planar diagram (see [reference]). Figure 5B The second electrode.

[0108] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may commonly overlap with multiple pixels and cover the first semiconductor pattern. The first insulating layer 10 may include inorganic and / or organic materials and have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one selected from alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may be a single layer of silicon oxide. In addition to the first insulating layer 10, other insulating layers of the circuit layer DP_CL, which will be described below, may also be inorganic and / or organic layers and have a single-layer or multi-layer structure. Inorganic layers may include at least one selected from the above materials, but are not limited thereto.

[0109] The circuit layer DP_CL can include the pixel driver circuit PDC (see...) Figure 5B For ease of illustration and description, the pixel drive circuit PDC is shown (see [link]). Figure 5BThe first transistor T1 and the third transistor T3.

[0110] The third electrode G1 of the first transistor T1 may be disposed on the first insulating layer 10. The third electrode G1 may be part of a metal pattern. The third electrode G1 of the first transistor T1 may overlap with the channel cell A1 of the first transistor T1. The third electrode G1 of the first transistor T1 may be used as a mask in the process of doping the first semiconductor pattern. The third electrode G1 may include titanium (Ti), silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not particularly limited thereto.

[0111] The second insulating layer 20 may be disposed on the first insulating layer 10 and cover the third electrode G1 of the first transistor T1. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the second insulating layer 20 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer.

[0112] The upper electrode UE and the second rear surface metal layer BMC2 can be disposed on the second insulating layer 20. The upper electrode UE can overlap with the third electrode G1. The upper electrode UE can be part of a metal pattern. A portion of the overlapping third electrode G1 and a portion of the upper electrode UE can define a capacitor Cst (see [link to capacitor diagram]). Figure 5B In embodiments of this invention, the second insulating layer 20 may be replaced by an insulating pattern. In such embodiments, the upper electrode UE may be disposed on the insulating pattern and used as a mask configured to provide the insulating pattern from the second insulating layer 20.

[0113] The second rear surface metal layer BMC2 can be disposed below the oxide thin-film transistor (e.g., the third transistor T3). A constant voltage or signal can be applied to the second rear surface metal layer BMC2.

[0114] The third insulating layer 30 can be disposed on the second insulating layer 20 and cover the upper electrode UE and the second rear surface metal layer BMC2. The third insulating layer 30 can have a single-layer structure or a multi-layer structure. In an embodiment, for example, the third insulating layer 30 can have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0115] A second semiconductor pattern may be disposed on a third insulating layer 30. The second semiconductor pattern may include a silicon-oxide-semiconductor (SOS). The SOS may include multiple regions divided according to whether a metal oxide is reduced. Regions where the metal oxide is reduced (hereinafter referred to as reduced regions) have higher conductivity than regions where the metal oxide is not reduced (hereinafter referred to as non-reduced regions). Reduced regions may substantially serve as the source / drain of a transistor or a signal line. Non-reduced regions may substantially correspond to the active region (or semiconductor region, channel) of a transistor. In other words, a portion of the second semiconductor pattern may be the active region of a transistor, another portion may be the source / drain region of a transistor, and yet another portion may be a signal transmission region.

[0116] The first electrode S3, channel unit A3, and second electrode D3 of the third transistor T3 are provided by a second semiconductor pattern. The first electrode S3 and the second electrode D3 may comprise metal reduced from a metal-oxide-semiconductor. In a cross-sectional view, the first electrode S3 and the second electrode D3 may extend from the channel unit A3 in opposite directions.

[0117] A fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may commonly overlap with multiple pixels and cover the second semiconductor pattern. The fourth insulating layer 40 may include at least one selected from aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0118] The third electrode G3 of the third transistor T3 can be disposed on the fourth insulating layer 40. The third electrode G3 can be part of a metal pattern. The third electrode G3 of the third transistor T3 can overlap with the channel cell A3 of the third transistor T3. The third electrode G3 can be used as a mask in the process of doping the second semiconductor pattern. In an embodiment of the present invention, the fourth insulating layer 40 can be replaced by an insulating pattern.

[0119] The fifth insulating layer 50 can be disposed on the fourth insulating layer 40 and cover the third electrode G3. The fifth insulating layer 50 can be an inorganic layer.

[0120] The first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 may be connected to the connection signal line CSL through a first contact hole CH1 defined or formed through the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50.

[0121] A sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The organic layer may include, but is not particularly limited to, general polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic acid-based polymers, imide-based polymers, aryl ether-based polymers, amide-based polymers, fluorinated polymers, p-xylene-based polymers, vinyl alcohol-based polymers, or blends thereof.

[0122] The second connecting electrode CNE20 may be disposed on the sixth insulating layer 60. The second connecting electrode CNE20 may be connected to the first connecting electrode CNE10 through a second contact hole CH2 defined or formed through the sixth insulating layer 60.

[0123] The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 and cover the second connecting electrode CNE20. The seventh insulating layer 70 may be an organic layer.

[0124] The first electrode layer can be disposed on the circuit layer DP_CL. The pixel defining layer PDL is disposed on the first electrode layer. The first electrode layer may include the anode AE ​​of the light-emitting element ED and the anode AE1 of the first sensing element OPD1. The anode AE ​​of the light-emitting element ED and the anode AE1 of the first sensing element OPD1 can be disposed on the seventh insulating layer 70. The anode AE ​​of the light-emitting element ED can be connected to the second connection electrode CNE20 through the third contact hole CH3 defined or formed through the seventh insulating layer 70. That is, the light-emitting element ED can be electrically connected to the pixel driving circuit PDC disposed in the circuit layer DP_CL (see...). Figure 5B ).

[0125] A film opening PDL-OP is disposed in the pixel defining layer PDL. The film opening PDL-OP exposes at least a portion of the anode AE ​​of the light-emitting element ED. The pixel defining layer PDL may cover the anode AE1 of the first sensing element OPD1.

[0126] In embodiments of this invention, the pixel defining layer (PDL) may further include a black material. The PDL may also include a black organic dye / pigment, such as carbon black or aniline black. The PDL may be provided as a mixture of blue and black organic materials. The PDL may also include a hydrophobic organic material. The PDL may include an insulating material.

[0127] In the implementation method, such as Figure 5AAs shown, the display panel DP may include an emitting region PXA and a non-emitting region NPXA adjacent to the emitting region PXA. The non-emitting region NPXA may surround the emitting region PXA. In such an embodiment, the emitting region PXA is defined to correspond to a portion of the area exposed by the film opening PDL-OP of the anode AE.

[0128] The light-emitting layer EL can be disposed on the anode AE ​​of the light-emitting element ED. The light-emitting layer EL can be disposed in a region corresponding to the membrane opening PDL-OP. The light-emitting layer EL can produce light of a specified color. In one embodiment, the light-emitting layer EL can be a patterned light-emitting layer, but is not limited thereto. In another embodiment, the light-emitting layer EL can be disposed as one of a plurality of emitting regions PXA. Here, the light-emitting layer EL can produce white light or blue light. Furthermore, the light-emitting layer EL can have a multilayer structure referred to as tandem.

[0129] The luminescent layer (EL) may include low molecular weight organic materials or organic polymer materials as luminescent materials. Alternatively, the luminescent layer (EL) may include quantum dots as luminescent materials. The core of the quantum dots may be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, or combinations thereof.

[0130] The cathode (CE) can be disposed on the light-emitting layer (EL). In an embodiment, for example, the cathode (CE) can be commonly disposed in the emitting region (PXA), the non-emitting region (NPXA), and the non-pixel region (NPA). The pixel (PX) and the first sensor (FX1) may not be disposed in the non-pixel region (NPA).

[0131] The circuit layer DP_CL may also include a first sensor driver circuit O_SD1 (see Figure 5B For ease of explanation and description, in Figure 5A The image shows the reset transistor ST1 in the first sensor drive circuit O_SD1. The reset transistor ST1 in the first sensor drive circuit O_SD1 can be referred to as the first reset transistor.

[0132] The first electrode STS1, channel unit STA1, and second electrode STD1 of the reset transistor ST1 are provided by a second semiconductor pattern. The first electrode STS1 and the second electrode STD1 may comprise metal reduced from a metal-oxide-semiconductor. A fourth insulating layer 40 may be configured to cover the first electrode STS1, channel unit STA1, and second electrode STD1 of the reset transistor ST1. The third electrode STG1 of the reset transistor ST1 may be disposed on the fourth insulating layer 40. In an embodiment, the third electrode STG1 may be part of a metal pattern. The third electrode STG1 of the reset transistor ST1 may overlap with the channel unit STA1 of the reset transistor ST1.

[0133] In one implementation, for example, the reset transistor ST1 may be disposed in the same layer as the third transistor T3 (or directly on the same layer as the third transistor T3). In such an implementation, the first electrode STS1, channel unit STA1, and second electrode STD1 of the reset transistor ST1 may be provided in the same process as the first electrode S3, channel unit A3, and second electrode D3 of the third transistor T3. The third electrode STG1 of the reset transistor ST1 may also be provided in the same process as the third electrode G3 of the third transistor T3.

[0134] Although not shown separately, the first sensor drive circuit O_SD1 (see...) Figure 5B The amplifying transistor ST2 (see) Figure 5B The first and second electrodes of the transistor and the output transistor ST3 (see...) Figure 5B The first and second electrodes of the first transistor T1 can be provided in the same process as the first electrode S1 and the second electrode D1 of the first transistor T1. The reset transistor ST1 and the third transistor T3 can be disposed in the same layer (or directly on the same layer) in the same process, thus eliminating the need for an additional process to provide the reset transistor ST1. Therefore, process efficiency can be improved and costs can be reduced. The first sensor drive circuit O_SD1 (see...) Figure 5B The amplifying transistor ST2 (see) Figure 5B This can be referred to as the first amplifying transistor (see...). Figure 5B First sensor drive circuit O_SD1 (see...) Figure 5B The output transistor ST3 (see) Figure 5B This can be referred to as the first output transistor (see...). Figure 5B ).

[0135] The element layer DP_ED may also include a first sensing element OPD1.

[0136] The first sensing element OPD1 may include an anode AE1, a semiconductor layer RL11, and a cathode CE1.

[0137] The anode AE1 of the first sensing element OPD1 can be disposed in the same layer as the anode AE ​​of the light-emitting element ED (or directly on the same layer as the anode AE ​​of the light-emitting element ED). In such an embodiment, the anode AE1 can be disposed on the circuit layer DP_CL and provided simultaneously in the same process as the anode AE ​​of the light-emitting element ED. The anode AE1 can be electrically connected via a separate wiring from the reset transistor ST1. In such an embodiment, the anode AE1 can be electrically connected to the first sensor driving circuit O_SD1 (see...). Figure 5BThe anode AE1 can be referred to as the first electrode.

[0138] The pixel limiting layer (PDL) can be set on the circuit layer (DP_CL). The pixel limiting layer (PDL) can cover the anode (AE1).

[0139] The semiconductor layer RL11 can be disposed on the pixel definition layer PDL. The semiconductor layer RL11 may include organic optical sensing materials. The semiconductor layer RL11 can be provided simultaneously in the same process as the light-emitting layer EL of the light-emitting element ED.

[0140] In this embodiment, since the pixel defining layer PDL is disposed between the anode AE1 and the semiconductor layer RL11, the anode AE1 and the semiconductor layer RL11 can be electrically disconnected. In this embodiment, the semiconductor layer RL11 can be connected to the first sensor driving circuit O_SD1 (see...). Figure 5A The power is disconnected.

[0141] The cathode CE1 can be disposed on the semiconductor layer RL11. The cathode CE1 can be electrically connected to the semiconductor layer RL11. The cathode CE1 of the first sensing element OPD1 can be provided simultaneously in the same process as the cathode CE of the light-emitting element ED. In an embodiment, for example, the cathode CE1 can be integrally disposed with the cathode CE. In such an embodiment, the light-emitting element ED can be electrically connected to the cathode CE1 of the first sensing element OPD1. The cathode CE1 can be referred to as the second electrode.

[0142] In the implementation method, such as Figure 5B As shown, the display panel DP may also include a non-sensing area (NSA). The non-sensing area (NSA) can be an area in which external input is not sensed.

[0143] The encapsulation layer TFE can be disposed on the component layer DP_ED. The encapsulation layer TFE includes inorganic layers or organic layers. In an embodiment of the present invention, the encapsulation layer TFE may include two inorganic layers and an organic layer interposed between them. In an embodiment of the present invention, the encapsulation layer TFE may include multiple inorganic layers and organic layers stacked alternately on top of each other.

[0144] The inorganic encapsulation layer protects the light-emitting element (ED) and the first sensing element (OPD1) from moisture / oxygen, while the organic encapsulation layer protects the ED and OPD1 from foreign matter such as dust particles. The inorganic encapsulation layer may include, but is not particularly limited to, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. The organic encapsulation layer may include, but is not particularly limited to, an acrylic-based organic layer.

[0145] The sensor layer SL can be set on the encapsulation layer TFE. The sensor layer SL can sense external inputs applied from the outside. The sensor layer SL can also sense external inputs from the user's body parts US_F.

[0146] An anti-reflective layer RPL can be disposed on the sensor layer SL. The anti-reflective layer RPL may include a black matrix layer BM and a color filter layer CF.

[0147] The black matrix layer BM effectively prevents external light from being reflected from the sensor layer SL. The material constituting the black matrix layer BM is not particularly limited, as long as the material absorbs light. In some embodiments, the black matrix layer BM may be black and include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof.

[0148] An opening BM-OP can be defined within the black matrix layer BM. The opening BM-OP can overlap with the light-emitting layer EL. The black matrix layer BM can overlap with the first sensing element OPD1. When viewed in a planar view or on a third-direction DR3, the black matrix layer BM can cover the first sensing element OPD1.

[0149] The color filter layer CF can be placed on the black matrix layer BM and the sensor layer SL. The color filter layer CF can transmit light provided by the light-emitting layer EL that overlaps with the color filter layer CF.

[0150] Figure 5B This is an equivalent circuit diagram of the pixel and the first sensor according to an embodiment of the present invention.

[0151] Figure 4 Multiple pixel PXs are shown (see Figure 5B An exemplary equivalent circuit diagram of pixel PXij is shown below. Since multiple pixels PX each have the same circuit structure, the circuit structure of pixel PXij will be described in detail, and descriptions of the remaining pixels PX will be omitted. Furthermore, Figure 4 It shows Figure 5A An exemplary equivalent circuit diagram of one of the plurality of first sensors FX1 shown is provided. Since each of the plurality of first sensors FX1 has the same circuit structure as the others, a detailed description of the circuit structure of the first sensor FX1 will be provided, and descriptions of the remaining first sensors FX1 will be omitted.

[0152] refer to Figure 5B and Figure 5BPixel PXij is connected to the i-th data line DL1 to DLm, the j-th initialization scan line SILj among the initialization scan lines SIL1 to SILn, the j-th compensation scan line SCLj among the compensation scan lines SCL1 to SCLn, the j-th write scan line SWLj among the write scan lines SWL1 to SWLn, the j-th black scan line SBLj among the black scan lines SBL1 to SBLn, and the j-th transmit control line EMLj among the transmit control lines EML1 to EMLn.

[0153] Pixel PXij may include a light-emitting element (ED) and a pixel driving circuit (PDC). The light-emitting element (ED) may include a light-emitting diode (LED). In an embodiment, for example, the light-emitting element (ED) may be an organic light-emitting diode including an organic light-emitting layer, but it is not particularly limited thereto.

[0154] The pixel driving circuit PDC includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a fifth transistor T5, a first emission control transistor ET1 and a second emission control transistor ET2, and a capacitor Cst.

[0155] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, as well as the first emitter control transistor ET1 and the second emitter control transistor ET2, can be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, as well as the first emitter control transistor ET1 and the second emitter control transistor ET2, can be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 can be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the first emitter control transistor ET1, and the second emitter control transistor ET2 can be LTPS transistors.

[0156] In this implementation, since the first transistor T1 is configured to directly affect the brightness of the display device DD, the first transistor T1 can be configured to include a semiconductor layer comprising polycrystalline silicon with high reliability, thereby enabling a display device with high resolution. In such an implementation, the oxide semiconductor has high carrier mobility and low leakage current, and therefore the voltage drop is not large despite the long driving time. In other words, even during low-frequency driving, the color change of the image according to the voltage drop is not large, and therefore low-frequency driving is possible. In this way, it is expected that the oxide semiconductor has small leakage current, and therefore at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can be used as the oxide semiconductor to effectively prevent leakage current that could flow to the gate electrode and substantially reduce power consumption.

[0157] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, as well as the first emitter control transistor ET1 and the second emitter control transistor ET2, can be a P-type transistor, while the other transistors can be N-type transistors. In an embodiment, for example, the first transistor T1, the second transistor T2, and the fifth transistor T5, as well as the first emitter control transistor ET1 and the second emitter control transistor ET2, can be P-type transistors, and the third transistor T3 and the fourth transistor T4 can be N-type transistors.

[0158] The configuration of the pixel driving circuit PDC according to the embodiments of this utility model is not limited to... Figure 5B The implementation shown is as follows. Figure 3 The pixel driver circuit PDC shown is merely an example, and its configuration can be modified. For instance, all of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, and fifth transistor T5, as well as the first emitter control transistor ET1 and the second emitter control transistor ET2, can be either P-type or N-type transistors.

[0159] The j-th initialization scan line SILj, the j-th compensation scan line SCLj, the j-th write scan line SWLj, the j-th black scan line SBLj, and the j-th transmit control line EMLj can respectively transmit the j-th initialization scan signal SIj, the j-th compensation scan signal SCj, the j-th write scan signal SWj, the j-th black scan signal SBj, and the j-th transmit control signal EMj to the pixel PXij. The i-th data line DL transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di can have the same image signal RGB (see image signal RGB) input to the display device DD. Figure 5B The corresponding voltage level.

[0160] The first driving voltage line VL1 and the second driving voltage line VL2 can respectively transmit the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PXij. In addition, the first initialization voltage line VL3 and the second initialization voltage line VL4 can respectively transmit the first initialization voltage Vint1 and the second initialization voltage Vint2 to the pixel PXij.

[0161] A first transistor T1 is connected between a first drive voltage line VL1, which transmits the first drive voltage ELVDD, and a light-emitting element ED. The first transistor T1 includes a first electrode connected to the first drive voltage line VL1 via a first emitter control transistor ET1, a second electrode connected to the anode AE ​​of the light-emitting element ED via a second emitter control transistor ET2, and a third electrode (e.g., a gate electrode) connected to a terminal (e.g., a first node N1) of a capacitor Cst. According to the switching operation of the second transistor T2, the first transistor T1 can receive the i-th data signal Di transmitted by the i-th data line DL1 and provide a drive current Id to the light-emitting element ED.

[0162] The second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line SWLj. The second transistor T2 can be turned on in response to the j-th write scan signal SWj transmitted via the j-th write scan line SWLj, so as to transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0163] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line SCLj. The third transistor T3 can be turned on in response to the j-th compensation scan signal SCj transmitted via the j-th compensation scan line SCLj to connect the third electrode and the second electrode of the first transistor T1, that is, a diode connected to the first transistor T1.

[0164] A fourth transistor T4 is connected between the first node N1 and the first initialization voltage line VL3 to which the first initialization voltage VINT1 is applied. The fourth transistor T4 may include a first electrode connected to the first initialization voltage line VL3 that transmits the first initialization voltage VINT1, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line SILj. The fourth transistor T4 is turned on in response to the j-th initialization scan signal SIj transmitted via the j-th initialization scan line SILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT1 to the first node N1 to initialize the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0165] The first emitter control transistor ET1 includes a first electrode connected to the first drive voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., the gate electrode) connected to the j-th emitter control line EMLj.

[0166] The second emission control transistor ET2 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE ​​of the light-emitting element ED, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line EMLj.

[0167] The first emitter control transistor ET1 and the second emitter control transistor ET2 can be simultaneously turned on in response to the j-th emitter control signal EMj transmitted via the j-th emitter control line EMLj. The first drive voltage ELVDD applied via the turned-on first emitter control transistor ET1 can be compensated via the diode-connected first transistor T1 and then transmitted to the light-emitting element ED.

[0168] The fifth transistor T5 may include a first electrode connected to a second initialization voltage line VL4 that transmits the second initialization voltage VINT2, a second electrode connected to a second emitter control transistor ET2 (e.g., a second node N2), and a third electrode connected to the j-th black scan line SBLj (e.g., a gate electrode). The second initialization voltage VINT2 may have a voltage level not higher than the first initialization voltage VINT1.

[0169] As described above, one end of capacitor Cst is connected to the third electrode of the first transistor T1, and the other end is connected to the first drive voltage line VL1. The cathode of the light-emitting element ED can be connected to the second drive voltage line VL2, which transmits the second drive voltage ELVSS. The second drive voltage ELVSS can have a lower level than the first drive voltage ELVDD.

[0170] The first sensor FX1dj is connected to the d-th readout line RLd, the j-th write scan line SWLj (or output control line), and the reset control line RCL among the readout lines RL1 to RLh.

[0171] The first sensor FX1dj includes a first sensing element OPD1 and a first sensor driving circuit O_SD1.

[0172] The first sensing element OPD1 may be a photodiode. In an embodiment, for example, the first sensing element OPD1 may be an organic photodiode (OPD) comprising organic material in a photoelectric conversion layer. The anode AE1 of the first sensing element OPD1 may be connected to a first sensing node SN1, and the cathode CE1 of the first sensing element OPD1 may be connected to a second driving voltage line VL2 configured to transmit a second driving voltage ELVSS. In an embodiment, a pixel defining layer PDL is disposed between the anode AE1 and the cathode CE1 of the first sensing element OPD1, and therefore the first sensing element OPD1 and the first sensor driving circuit O_SD1 may be electrically disconnected or electrically disconnected from each other.

[0173] Figure 3 An embodiment of the first sensor FX1dj including a first sensing element OPD1 is shown, but the embodiment is not particularly limited thereto. In an embodiment, for example, the first sensor FX1dj may include z light-receiving elements connected in parallel with each other. Here, z can be an integer of 2 or greater.

[0174] The first sensor driving circuit O_SD1 includes three transistors ST1, ST2, and ST3. The three transistors ST1, ST2, and ST3 can be a reset transistor ST1, an amplifying transistor ST2, and an output transistor ST3, respectively. At least one of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 can be an oxide semiconductor transistor (OSB). In one embodiment, for example, the reset transistor ST1 can be an OSB, while the amplifying transistor ST2 and the output transistor ST3 can be LTPS transistors. However, the embodiments of this invention are not limited to this, and for example, in another embodiment, the reset transistor ST1 and the output transistor ST3 can be OSB transistors, while the amplifying transistor ST2 can be an LTPS transistor.

[0175] Furthermore, some of the reset transistor ST1, amplifying transistor ST2, and output transistor ST3 can be P-type transistors, while the others can be N-type transistors. In an embodiment of this invention, amplifying transistor ST2 and output transistor ST3 can be P-type transistors, and reset transistor ST1 can be an N-type transistor. However, the embodiments are not limited to this, and all of the reset transistor ST1, amplifying transistor ST2, and output transistor ST3 can be either N-type or P-type transistors.

[0176] The reset transistor ST1 includes a first electrode connected to a third initialization voltage line VL5 that receives a first reset voltage Vrst1, a second electrode connected to a first sensing node SN1, and a third electrode that receives a reset control signal RST. The third electrode may be referred to as the gate electrode.

[0177] The second electrode of the reset transistor ST1 can be electrically disconnected or electrically disconnected from the first sensing element OPD1. The pixel defining layer PDL can be disposed between the anode AE1 of the first sensing element OPD1 and the semiconductor layer RL11 of the first sensing element OPD1 connected to the reset transistor ST1. Therefore, the reset transistor ST1 and the first sensing element OPD1 can be electrically disconnected or electrically disconnected from each other.

[0178] The reset transistor ST1 can reset the potential of the first sensing node SN1 to the first reset voltage Vrst1 in response to the reset control signal RST. The reset control signal RST can be a signal provided through the reset control line RCL.

[0179] Amplifying transistor ST2 includes a first electrode receiving a sensing drive voltage (or sensor drive voltage) SLVD, a second electrode connected to a second sensing node SN2, and a third electrode connected to a first sensing node SN1. Amplifying transistor ST2 can be turned on in response to the potential of the first sensing node SN1 to apply the sensing drive voltage SLVD to the second sensing node SN2. In embodiments, for example, the sensing drive voltage SLVD can be one of a first drive voltage ELVDD and a first initialization voltage VINT1 and a second initialization voltage VINT2. In an embodiment where the sensing drive voltage SLVD is the first drive voltage ELVDD, the first electrode of amplifying transistor ST2 can be electrically connected to a first drive voltage line VL1. In an embodiment where the sensing drive voltage SLVD is the first initialization voltage VINT1, the first electrode of amplifying transistor ST2 can be electrically connected to a first initialization voltage line VL3. In an embodiment where the sensing drive voltage SLVD is the second initialization voltage VINT2, the first electrode of amplifying transistor ST2 can be electrically connected to a second initialization voltage line VL4.

[0180] Output transistor ST3 includes a first electrode connected to the second sensing node SN2, a second electrode connected to the d-th readout line RLd, and a third electrode for receiving the output control signal. Output transistor ST3 can transmit the noise signal NSd to the d-th readout line RLd in response to the output control signal. The output control signal can be the j-th write scan signal SWj (or j-th output control signal) provided through the j-th write scan line SWLj. In other words, output transistor ST3 can receive the j-th write scan signal SWj provided from the j-th write scan line SWLj as the output control signal.

[0181] When the reset transistor ST1, the amplification transistor ST2, and the output transistor ST3 are driven, a noise signal NSd can be generated.

[0182] The noise signal NSd may include electrical noise generated by the amplifying transistor ST2.

[0183] The readout circuit 500 that has received the noise signal NSd (see...) Figure 3 It can process the noise signal NSd to generate the noise-processed signal S_NS (see...). Figure 3 The noise-processed signal S_NS is then provided to the drive controller 100 (see [link]). Figure 3 ).

[0184] According to an embodiment of the present invention, the semiconductor layer RL11 that receives light to generate an electrical signal can be electrically disconnected (or electrically disconnected) from the anode AE1 of the first sensing element OPD1. In such an embodiment, the black matrix layer BM disposed on the semiconductor layer RL11 can cover the semiconductor layer RL11 to block external light. In such an embodiment, the noise signal NSd provided through the d-th readout line RLd can include only the noise generated in the first sensor drive circuit O_SD1. Readout circuit 500 (see...) Figure 6B The noise signal NSd can be easily obtained from the second sensor FX2dj (see [link]). Figure 6B The measured signal is removed from the second sensor drive circuit O_SD2 (see...) Figure 6A Noise generated in the process. Therefore, a display device with improved sensing reliability can be provided.

[0185] Figure 4 It is according to the embodiments of this utility model along Figure 6A A cross-sectional view of the display device taken by line II-II'. In the description Figure 2 When implementing the method, for Figure 5A and Figure 6A The same elements shown are given the same reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0186] refer to Figure 6B In this implementation, the circuit layer DP_CL may further include a second sensor driving circuit O_SD2 (see...). Figure 6B For ease of illustration and description, the second sensor drive circuit O_SD2 is shown (see [link]). Figure 6B The reset transistor ST1 in the second sensor drive circuit O_SD2 can be referred to as the second reset transistor.

[0187] The first electrode STS1, channel unit STA1, and second electrode STD1 of the reset transistor ST1 are provided by (or defined by a portion of) a second semiconductor pattern. The first electrode STS1 and the second electrode STD1 may comprise metal reduced from a metal-oxide-semiconductor. A fourth insulating layer 40 is configured to cover the first electrode STS1, channel unit STA1, and second electrode STD1 of the reset transistor ST1. The third electrode STG1 of the reset transistor ST1 is disposed on the fourth insulating layer 40. In an embodiment, the third electrode STG1 may be part of a metal pattern. The third electrode STG1 of the reset transistor ST1 may overlap with the channel unit STA1 of the reset transistor ST1.

[0188] In one implementation, for example, the reset transistor ST1 may be disposed in the same layer as the third transistor T3 (or directly disposed on the same layer as the third transistor T3). In another implementation, the first electrode STS1, channel unit STA1, and second electrode STD1 of the reset transistor ST1 may be provided in the same process as the first electrode S3, channel unit A3, and second electrode D3 of the third transistor T3. The third electrode STG1 of the reset transistor ST1 may also be provided in the same process as the third electrode G3 of the third transistor T3.

[0189] Although not shown separately, the second sensor drive circuit O_SD2 (see...) Figure 6B The amplifying transistor ST2 (see) Figure 6B The first and second electrodes of the transistor and the output transistor ST3 (see...) Figure 6B The first and second electrodes of the first transistor T1 can be provided in the same process as the first electrode S1 and the second electrode D1 of the first transistor T1. The reset transistor ST1 and the third transistor T3 can be provided in the same process on the same layer (or directly on the same layer) without performing additional processes for providing the reset transistor ST1. Therefore, process efficiency can be improved and costs can be reduced. The second sensor drive circuit O_SD2 (see...) Figure 6B The amplifying transistor ST2 (see) Figure 6B This can be referred to as the second amplifying transistor (see...). Figure 6BThe second sensor driving circuit O_SD2 (see...) Figure 6B The output transistor ST3 (see) Figure 6B This can be referred to as the second output transistor (see...). Figure 6B ).

[0190] The element layer DP_ED may also include a second sensing element OPD2.

[0191] The second sensing element OPD2 may include an anode AE2, a semiconductor layer RL22, and a cathode CE2.

[0192] The anode AE2 of the second sensing element OPD2 can be disposed in the same layer as the anode AE ​​of the light-emitting element ED (or directly disposed on the same layer as the anode AE ​​of the light-emitting element ED). In an embodiment, the anode AE2 can be disposed on the circuit layer DP_CL and provided simultaneously in the same process as the anode AE ​​of the light-emitting element ED. The anode AE2 can be electrically connected via wiring separate from the reset transistor ST1. In an embodiment, the anode AE2 can be electrically connected to the second sensor driving circuit O_SD2 (see...). Figure 6A The anode AE2 can be referred to as the first electrode.

[0193] The pixel limiting layer (PDL) can be set on the circuit layer (DP_CL).

[0194] The first film opening PDL-OP1 and the second film opening PDL-OP2 can be disposed in the pixel defining layer PDL. The first film opening PDL-OP1 exposes at least a portion of the anode AE ​​of the light-emitting element ED.

[0195] The second film opening PDL-OP2 of the pixel defining layer PDL exposes at least a portion of the anode AE2 of the second sensing element OPD2. A semiconductor layer RL22 is disposed on the portion of the anode AE2 exposed by the second film opening PDL-OP2. The semiconductor layer RL22 may comprise an organic optical sensing material. The semiconductor layer RL22 may be provided simultaneously with the light-emitting layer EL of the light-emitting element ED in the same process.

[0196] A cathode CE2 can be disposed on the semiconductor layer RL22. Each of the anode AE2 and cathode CE2 can receive an electrical signal. The anode AE2 and cathode CE2 can each receive different signals. Therefore, a specified electric field can be provided between the anode AE2 and cathode CE2. The semiconductor layer RL22 can generate an electrical signal corresponding to the light incident on the sensor.

[0197] The cathode CE2 of the second sensing element OPD2 can be provided simultaneously with the cathode CE of the light-emitting element ED using the same process. In one embodiment, for example, the cathode CE2 of the second sensing element OPD2 can be integrally formed with the cathode CE of the light-emitting element ED as a single, inseparable part. In such an embodiment, the light-emitting element ED can be electrically connected to the cathode CE2 of the second sensing element OPD2. The cathode CE2 can be referred to as the second electrode.

[0198] The charge generated in the semiconductor layer RL22 alters the electric field between the anode AE2 and the cathode CE2. The amount of charge generated in the semiconductor layer RL22 can be varied based on whether light is incident on the second sensing element OPD2, and the amount and intensity of the light incident on the second sensing element OPD2. Therefore, the electric field provided between the anode AE2 and the cathode CE2 can be changed. According to an embodiment of the present invention, the second sensing element OPD2 can acquire information, including user fingerprint information, by changing the electric field between the anode AE2 and the cathode CE2.

[0199] In the implementation method, such as Figure 6B As shown, the display panel DP may include a sensing region SA and a non-sensing region NSA adjacent to the sensing region SA. The non-sensing region NSA may surround the sensing region SA. In an embodiment, the sensing region SA is defined as the region corresponding to the portion of the anode AE2 exposed by the second membrane opening PDL-OP2.

[0200] An anti-reflective layer RPL can be disposed on the sensor layer SL. The anti-reflective layer RPL may include a black matrix layer BM and a color filter layer CF.

[0201] The first opening BM-OP1 and the second opening BM-OP2 can be defined within the black matrix layer BM. The first opening BM-OP1 can overlap with the light-emitting layer EL. The second opening BM-OP2 can overlap with the semiconductor layer RL22. Light can be supplied from the outside to the second sensor FX2 via the second opening BM-OP2.

[0202] The color filter layer CF can be placed on the black matrix layer BM and the sensor layer SL. The color filter layer CF can transmit light provided by the light-emitting layer EL that overlaps with the color filter layer CF.

[0203] Figure 6B This is an equivalent circuit diagram of the pixel and the second sensor according to an embodiment of the present invention. In the description... Figure 5B When implementing the method, for Figure 6B The same elements shown are given the same reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0204] Figure 4 It showsFigure 6A An exemplary equivalent circuit diagram of one of the multiple second sensors FX2 shown is provided, namely, second sensor FX2dj. Since each of the multiple second sensors FX2 has the same circuit structure as the others, the circuit structure of second sensor FX2dj will be described in detail, and descriptions of the remaining second sensors FX2 will be omitted.

[0205] refer to Figure 6B and Figure 5B In this embodiment, the second sensor FX2dj includes a second sensing element OPD2 and a second sensor driving circuit O_SD2. The second sensor driving circuit O_SD2 can be substantially the same as the first sensor driving circuit O_SD1 (see...). Figure 5B )same.

[0206] The second sensor FX2dj is connected to the d-th readout line RLd, the j-th write scan line SWLj (or output control line), and the reset control line RCL among the readout lines RL1 to RLh.

[0207] The second electrode of the reset transistor ST1 can be electrically connected to the second sensing element OPD2.

[0208] The reset transistor ST1 can reset the potential of the first sensing node SN1 to the first reset voltage Vrst1 in response to the reset control signal RST. The reset control signal RST can be a signal provided through the reset control line RCL.

[0209] Amplifying transistor ST2 includes a first electrode receiving a sensing drive voltage SLVD, a second electrode connected to a second sensing node SN2, and a third electrode connected to a first sensing node SN1. Amplifying transistor ST2 can be turned on in response to the potential of the first sensing node SN1 to apply the sensing drive voltage SLVD to the second sensing node SN2. In embodiments, for example, the sensing drive voltage SLVD can be one of a first drive voltage ELVDD and a first initialization voltage VINT1 and a second initialization voltage VINT2. In an embodiment where the sensing drive voltage SLVD is the first drive voltage ELVDD, the first electrode of amplifying transistor ST2 can be electrically connected to a first drive voltage line VL1. In an embodiment where the sensing drive voltage SLVD is the first initialization voltage VINT1, the first electrode of amplifying transistor ST2 can be electrically connected to a first initialization voltage line VL3. In an embodiment where the sensing drive voltage SLVD is the second initialization voltage VINT2, the first electrode of amplifying transistor ST2 can be electrically connected to a second initialization voltage line VL4.

[0210] Output transistor ST3 includes a first electrode connected to the second sensing node SN2, a second electrode connected to the d-th readout line RLd, and a third electrode for receiving the output control signal. Output transistor ST3 can transmit the readout signal FSd to the d-th readout line RLd in response to the output control signal. The output control signal can be the j-th write scan signal SWj (or j-th output control signal) provided through the j-th write scan line SWLj. In other words, output transistor ST3 can receive the j-th write scan signal SWj provided from the j-th write scan line SWLj as the output control signal.

[0211] The reset period can be defined as the rise period (i.e., the high-level period) of the reset control line RCL. In an embodiment, the reset transistor ST1 is turned on when a high-level reset control signal RST is provided through the reset control line RCL. In an embodiment where the reset transistor ST1 is a PMOS transistor, a low-level reset control signal RST can be provided to the reset control line RCL during the reset period. During the reset period, the first sensing node SN1 can be reset to a potential corresponding to the first reset voltage Vrst1. In an embodiment, for example, the first reset voltage Vrst1 may have a voltage level lower than the second drive voltage ELVSS.

[0212] The second sensing element OPD2 of the second sensor FX2dj can be exposed to light during the emission cycle of the light-emitting element ED. Alternatively, the second sensing element OPD2 of the second sensor FX2dj can be exposed to external light. The voltage of the first sensing node SN1 is maintained at the first reset voltage Vrst1 during the reset cycle, and because the second sensing element OPD2 is exposed to light, the voltage of the first sensing node SN1 can be gradually shifted to the second drive voltage ELVSS. The amplifying transistor ST2 can be a source follower amplifier configured to generate a source-drain current proportional to the amount of charge input from the first sensing node SN1 to the third electrode.

[0213] Output transistor ST3 can receive a low-level j-th write scan signal SWj via the j-th write scan line SWLj during the output cycle. When output transistor ST3 is turned on in response to the low-level j-th write scan signal SWj, the read signal FSd corresponding to the current flowing through amplifier transistor ST2 can be output to the d-th read line RLd.

[0214] The noise signal of the second sensor driving circuit O_SD2 can also be included in the readout signal FSd. The noise signal NSd of the second sensor driving circuit O_SD2 (see...) Figure 3 It can be similar to the noise signal NSd of the first sensor drive circuit O_SD1.

[0215] Readout circuit 500 (see) Figure 3 It can receive the readout signal FSd, process the readout signal FSd to generate the processed sensing signal S_FS, and provide the processed sensing signal S_FS to the drive controller 100 (see...). Figure 5A ).

[0216] According to an embodiment of this utility model, the reset transistor ST1 (see...) Figure 5A The second electrode can be connected to the first sensing element OPD1 (see...). Figure 5B Electrical disconnection (or electrical disconnection connection). Therefore, the first sensor FX1dj (see...) can be used. Figure 5A To measure the first sensing element OPD1 (see...) Figure 5B The noise signal NSd generated unrelated to the first sensor drive circuit O_SD1 (see...) Figure 6B In addition, reset transistor ST1 (see...) Figure 3 The second electrode of the sensor can be electrically connected to the second sensing element OPD2. Therefore, the readout signal FSd, which includes the noise signal of the second sensor drive circuit O_SD2, can be measured. Readout circuit 500 (see...) Figure 5B It can receive noise signals NSd (see...) Figure 5B ) and readout signal FSd, process noise signal NSd (see Figure 3 Each of the readout signals FSd is used to generate a noise-processed signal S_NS (see...). Figure 3 ) and the processed sensing signal S_FS (see Figure 3 The noise is processed by the signal S_NS (see...). Figure 3 ) and the processed sensing signal S_FS (see Figure 3 ) is provided to drive controller 100 (see Figure 3 Drive controller 100 (see) Figure 7 A noise-reduced signal can be generated based on the difference between the noise-processed signal S_NS and the processed sensing signal S_FS (e.g., by subtracting the noise-processed signal S_NS from the processed sensing signal S_FS). Therefore, a display device DD with improved sensing reliability can be provided.

[0217] Figure 4 According to another embodiment of this utility model, along Figure 7 A cross-sectional view of the display device taken by line I-I'. In the description Figure 5A When implementing the method, for Figure 5A The same elements shown are given the same reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0218] refer to Figure 7 andFigure 5B The implementation of the display device DD-1 may include a display panel DP, a sensor layer SL, and an anti-reflective layer RPL-1. The anti-reflective layer RPL-1 may be disposed on the sensor layer SL. The anti-reflective layer RPL-1 may include a black matrix layer BM-1 and a color filter layer CF.

[0219] The first opening BM-OP1 and the third opening BM-OP3 can be defined within the black matrix layer BM-1. The first opening BM-OP1 can overlap with the light-emitting layer EL. The third opening BM-OP3 can overlap with the semiconductor layer RL11. In such an embodiment, the third opening BM-OP3 can overlap with the first sensing element OPD1.

[0220] The color filter layer CF can be disposed on the black matrix layer BM-1 and the sensor layer SL. The color filter layer CF can transmit light provided by the light-emitting layer EL that overlaps with the color filter layer CF.

[0221] According to an embodiment of the present invention, the semiconductor layer RL11 that receives light to generate an electrical signal can be electrically disconnected from the anode AE1 of the first sensing element OPD1. In such an embodiment, the noise signal NSd (see [reference]) provided by the d-th readout line RLd Figure 5B This can be included only in the first sensor drive circuit O_SD1 (see...) Figure 3 Noise generated in the process. Readout circuit 500 (see...) Figure 5B The noise signal NSd can be used (see Figure 6B To easily remove from the signal measured by the second sensor FX2 in the second sensor drive circuit O_SD2 (see...) Figure 8 Noise generated in the process. Therefore, a display device DD-1 with improved sensing reliability can be provided.

[0222] Figure 8 This is a plan view of the display area of ​​a display panel according to an embodiment of the present invention. In the description... Figure 3 When implementing the method, for Figure 8 The same elements shown are given the same reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0223] refer to Figure 9A In this embodiment, the display area DA-1 may include a first area AR1a and a second area AR2. When viewed in a plan view or on a third-direction DR3, the base layer BL may overlap with the display area DA-1. The display area DA-1 may be defined within the base layer BL. The first area AR1a and the second area AR2 may be defined within the base layer BL. The first area AR1a may include a first-first-area AR1-1 and a second-first-area AR1-2.

[0224] Each of the second region AR2 and the second-first region AR1-2 can be configured as multiple. One of the multiple second regions AR2 can be located adjacent to one of the multiple second-first regions AR1-2 in a direction opposite to the second direction DR2. Another of the multiple second regions AR2 can be located adjacent to another of the multiple second-first regions AR1-2 in the second direction DR2. The multiple second-first regions AR1-2 can be located between the multiple second regions AR2.

[0225] One of the plurality of second-first regions AR1-2 can be located adjacent to the first-first region AR1-1 in a direction opposite to the second direction DR2. Another of the plurality of second-first regions AR1-2 can be located adjacent to the first-first region AR1-1 in the second direction DR2.

[0226] Multiple pixel PX and multiple second sensor FX2 can be arranged in the first region AR1a. The display device DD-2 in the first region AR1-1 (see...) Figure 6A It can have the same as Figure 9A The display device DD shown has the same stacked structure as the one shown.

[0227] Multiple pixel PXs and multiple first sensors FX1s can be set in the second region AR2. The display device DD-2 in the second region AR2 (see...) Figure 5A It can have the same as Figure 9A The display device DD shown has the same stacked structure as the one shown.

[0228] Figure 8 It is according to the embodiments of this utility model along Figure 9A A cross-sectional view of the display device taken by line III-III'. In the description Figure 6A When implementing the method, for Figure 9A The same elements shown are given the same reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0229] refer to Figure 9B The implementation of the display device DD-2 may include a display panel DP, a sensor layer SL, and an anti-reflective layer RPL-2. The anti-reflective layer RPL-2 may be disposed on the sensor layer SL. The anti-reflective layer RPL-2 may include a black matrix layer BM-2 and a color filter layer CF.

[0230] The opening BM-OP can be defined within the black matrix layer BM-2. The opening BM-OP can overlap with the light-emitting layer EL. The black matrix layer BM-2 can be configured to overlap with the second sensing element OPD2. When viewed in a planar view or on a third-direction DR3, the black matrix layer BM-2 can cover the second sensing element OPD2.

[0231] The color filter layer CF can be disposed on the black matrix layer BM-2 and the sensor layer SL. The color filter layer CF can transmit light provided by the light-emitting layer EL that overlaps with the color filter layer CF.

[0232] The display panel (DP) may also include a non-sensing area (NSA). The NSA can be an area in which external input is not sensed.

[0233] Figure 9B This is an equivalent circuit diagram of the pixel and the second sensor according to an embodiment of the present invention. In the description... Figure 5B When implementing the method, for Figure 6B and Figure 9B The same elements shown are given the same reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0234] Figure 8 The setting is shown Figure 9B An exemplary equivalent circuit diagram of a second sensor FX2dj, one of the plurality of second sensors FX2 in the second-first region AR1-2 shown. Since each of the plurality of second sensors FX2 disposed in the second-first region AR1-2 has the same circuit structure as each other, the circuit structure of the second sensor FX2dj will be described in detail, and the description of the remaining second sensors FX2 will be omitted.

[0235] refer to Figure 3 The second sensor FX2dj includes a second sensing element OPD2 and a second sensor driving circuit O_SD2.

[0236] The second sensor drive circuit O_SD2 includes three transistors ST1, ST2, and ST3. These three transistors ST1, ST2, and ST3 can be the reset transistor ST1, the amplification transistor ST2, and the output transistor ST3, respectively.

[0237] Output transistor ST3 can transmit the second noise signal NS2d to the d-th read line RLd in response to the output control signal. The output control signal can be the j-th write scan signal SWj (or the j-th output control signal) provided by the j-th write scan line SWLj. In other words, output transistor ST3 can receive the j-th write scan signal SWj provided from the j-th write scan line SWLj as the output control signal.

[0238] The second noise signal NS2d may include electrical noise generated in the second sensing element OPD2. Due to the black matrix layer BM-2, external light may not be supplied to the second sensing element OPD2. The second noise signal NS2d may be caused by dark current generated in the second sensing element OPD2.

[0239] Readout circuit 500 (see) Figure 3 It can receive a second noise signal NS2d, process the second noise signal NS2d to generate a noise-processed signal S_NS (see...). Figure 3 The noise is processed and the signal S_NS is provided to the drive controller 100 (see [link]). Figure 8 ).

[0240] According to an embodiment of this utility model, in the second region AR2 (see...) Figure 5A The reset transistor ST1 in ) (see Figure 5A The second electrode can be connected to the first sensing element OPD1 (see...). Figure 5A Electrically disconnected (or electrically disconnected). Therefore, measurements can be taken with the first sensing element OPD1 (see...). Figure 5B The noise signal NSd generated unrelated to the first sensor drive circuit O_SD1 (see...) Figure 8 Furthermore, the second electrode of the reset transistor ST1 in the second-first region AR1-2 can be electrically connected to the second sensing element OPD2, and when viewed in a planar view, the black matrix layer BM-2 can cover the second sensing element OPD2. Therefore, the second noise signal NS2d of the second sensing element OPD2 can be measured. Additionally, in the first-first region AR1-1 (see...) Figure 6B The second electrode of the reset transistor ST1 in the sensor can be electrically connected to the second sensing element OPD2. Therefore, the readout signal FSd (see [reference needed]) can be measured, including the noise signal from the second sensing element OPD2 and the noise signal from the second sensor drive circuit O_SD2. Figure 3 ).

[0241] In this embodiment of the present invention, the readout circuit 500 (see...) Figure 5B It can receive noise signals NSd (see...) Figure 6B The second noise signal NS2d and the readout signal FSd (see...) Figure 5B ), processing noise signals NSd (see Figure 6B The second noise signal NS2d and the readout signal FSd (see...) Figure 3 Each of the following is used to generate a noise-processed signal S_NS (see Figure 3 ) and the processed sensing signal S_FS (see Figure 3This process transforms the noise into a processed signal S_NS (see...). Figure 3 The processed sensing signal S_FS is provided to the drive controller 100 (see...). Figure 9A The drive controller 100 can subtract the noise-processed signal S_NS from the processed sensing signal S_FS to obtain a noise-reduced signal. Therefore, a display device DD-2 with improved sensing reliability can be provided (see [link to relevant documentation]). Figure 10 ).

[0242] Figure 10 This is a plan view of the display area of ​​a display panel according to an embodiment of the present invention. In the description... Figure 4 When implementing the method, for Figure 10 The same elements shown are given the same reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0243] refer to Figure 11 The display area DA-2 may include a first area AR1, a second area AR2, and a third area AR3. When viewed in a plan view, the base layer BL may overlap with the display area DA-2. The display area DA-2 may be confined within the base layer BL. The first area AR1, the second area AR2, and the third area AR3 may be confined within the base layer BL.

[0244] The third region AR3 can be located adjacent to multiple second regions AR2 and the first region AR1 in a direction opposite to the first direction DR1. Only a plurality of pixels PX can be set in the third region AR3. In other words, each of the first sensor FX1 and the second sensor FX2 can be spaced apart from the third region AR3.

[0245] Figure 11 This is an equivalent circuit diagram of the pixel and the first sensor according to an embodiment of the present invention. In the description... Figure 5B When implementing the method, for Figure 5A The same elements shown are given the same reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0246] refer to Figure 11 and Figure 6B In the implementation, the first sensor FX1dj-1 includes a first sensing element OPD1 and a first sensor driving circuit O_SD1-1.

[0247] The first sensor driving circuit O_SD1-1 includes three transistors ST1-1, ST2, and ST3. The three transistors ST1-1, ST2, and ST3 can be the reset transistor ST1-1, the amplification transistor ST2, and the output transistor ST3, respectively.

[0248] The reset transistor ST1-1 includes a first electrode connected to a third initialization voltage line VL5-1 that receives the second reset voltage Vrst2, a second electrode connected to a first sensing node SN1, and a third electrode that receives the reset control signal RST. The third electrode may be referred to as the gate electrode.

[0249] The second electrode of the reset transistor ST1-1 may not be electrically connected to the first sensing element OPD1. The pixel defining layer PDL may be disposed between the anode AE1 of the first sensing element OPD1 and the semiconductor layer RL11 of the first sensing element OPD1 connected to the reset transistor ST1-1. Therefore, the reset transistor ST1-1 and the first sensing element OPD1 may be electrically disconnected or electrically disconnected from each other.

[0250] Reset transistor ST1-1 can reset the potential of the first sensing node SN1 to a value equal to the first reset voltage Vrst1 (see reset control signal RST) in response to the reset control signal RST. Figure 3 A second reset voltage Vrst2 with different voltage levels. The reset control signal RST can be a signal provided through the reset control line RCL.

[0251] When the reset transistor ST1-1, the amplification transistor ST2, and the output transistor ST3 are driven, a noise signal NSd-1 can be generated.

[0252] The noise signal NSd-1 may include electrical noise generated from the amplifying transistor ST2.

[0253] The readout circuit 500, which has received the noise signal NSd-1, (see...) Figure 3 It can process noise signals NSd-1, generating noise processed signals S_NS (see...). Figure 3 The noise-processed signal S_NS is then provided to the drive controller 100 (see [link]). Figure 4 ).

[0254] According to an embodiment of the present invention, it has a function of applying to the first region AR1 (see...) Figure 6B The reset transistor ST1 in ) (see Figure 6B The first reset voltage Vrst1 (see) Figure 4 A second reset voltage Vrst2 of different voltage levels can be applied to the second region AR2 (see...). Figure 6B The reset transistor ST1-1 in the first sensor drive circuit O_SD1-1 can be configured to operate in conjunction with the second sensor drive circuit O_SD2 (see [link]). A second reset voltage Vrst2 can be applied to the first sensor drive circuit O_SD1-1 to provide the reset voltage. Figure 3 The noise signal NSd-1 generated in the noise is described in the readout circuit 500 (see [link]). Figure 6BThe noise signal NSd-1 can be easily obtained from the second sensor FX2dj (see [link]). Figure 6B The measured readout signal FSd (see...) Figure 6B Remove from the second sensor drive circuit O_SD2 (see) Figure 3 Noise generated in the process. Therefore, a display device with improved sensing reliability can be provided (see DD). Figure 12 ).

[0255] Figure 12 This is an equivalent circuit diagram of the pixel and the first sensor according to an embodiment of the present invention. In the description... Figure 5B When implementing the method, regarding Figure 5A The same elements shown are given the same reference numerals, and any repeated detailed descriptions thereof will be omitted.

[0256] refer to Figure 12 and Figure 6B In the implementation, the first sensor FX1dj-2 includes a first sensing element OPD1 and a first sensor driving circuit O_SD1-2.

[0257] The first sensor driving circuit O_SD1-2 includes two transistors ST2-1 and ST3. The two transistors ST2-1 and ST3 can be the amplification transistor ST2-1 and the output transistor ST3, respectively.

[0258] The amplifying transistor ST2-1 includes a first electrode receiving a sensing drive voltage SLVD, a second electrode connected to a second sensing node SN2, and a gate electrode connected to a first sensing node SN1. The first sensing node SN1 can be connected to a third initialization voltage line VL5-1 that receives a second reset voltage Vrst2. In an embodiment, for example, the gate electrode of the amplifying transistor ST2-1 can be directly connected to the third initialization voltage line VL5-1. The second reset voltage Vrst2 can have the same characteristics as the first reset voltage Vrst1 (see...). Figure 3 Different voltage levels.

[0259] Amplifying transistor ST2-1 can be turned on in response to the potential of the first sensing node SN1 to apply a sensing drive voltage SLVD to the second sensing node SN2. In some embodiments, for example, the sensing drive voltage SLVD can be one of a first drive voltage ELVDD and a first initialization voltage VINT1 and a second initialization voltage VINT2. In an embodiment where the sensing drive voltage SLVD is the first drive voltage ELVDD, the first electrode of amplifying transistor ST2-1 can be electrically connected to the first drive voltage line VL1. In an embodiment where the sensing drive voltage SLVD is the first initialization voltage VINT1, the first electrode of amplifying transistor ST2-1 can be electrically connected to the first initialization voltage line VL3. In an embodiment where the sensing drive voltage SLVD is the second initialization voltage VINT2, the first electrode of amplifying transistor ST2-1 can be electrically connected to the second initialization voltage line VL4.

[0260] The gate electrode of the amplifying transistor ST2-1 may not be electrically connected to the first sensing element OPD1. The pixel defining layer PDL may be disposed between the anode AE1 of the first sensing element OPD1 and the semiconductor layer RL11 of the first sensing element OPD1 connected to the amplifying transistor ST2-1. Therefore, the amplifying transistor ST2-1 and the first sensing element OPD1 may be electrically disconnected or electrically disconnected from each other.

[0261] Output transistor ST3 includes a first electrode connected to the second sensing node SN2, a second electrode connected to the d-th readout line RLd, and a third electrode for receiving the output control signal. Output transistor ST3 can transmit the noise signal NSd-2 to the d-th readout line RLd in response to the output control signal. The output control signal can be the j-th write scan signal SWj (or j-th output control signal) provided through the j-th write scan line SWLj. In other words, output transistor ST3 can receive the j-th write scan signal SWj provided from the j-th write scan line SWLj as the output control signal.

[0262] When the amplifying transistor ST2-1 and the output transistor ST3 are driven, a noise signal NSd-2 can be generated. The noise signal NSd-2 may include electrical noise generated by the amplifying transistor ST2-1.

[0263] Readout circuit 500 (see) Figure 3 It can receive noise signal NSd-2, process noise signal NSd-2 to generate noise processed signal S_NS (see...). Figure 3 The noise-processed signal S_NS is then provided to the drive controller 100 (see [link]). Figure 6B ).

[0264] According to an embodiment of this invention, regardless of the reset control signal applied to the reset transistor, the second reset voltage Vrst2 can be directly applied to the gate electrode of the amplifying transistor ST2-1. It can be provided that is configured to work in conjunction with the second sensor drive circuit O_SD2 (see...). Figure 3 The noise signal NSd-2 generated in the noise is described in the readout circuit 500 (see [link]). Figure 6B The noise signal NSd-2 can be easily obtained from the second sensor FX2dj (see [link]). Figure 6B The measured readout signal FSd (see...) Figure 6B Remove from the second sensor drive circuit O_SD2 (see) Figure 3 Noise generated in the process. Therefore, a display device with improved sensing reliability can be provided (see DD). ​ ).

[0265] According to an embodiment of this invention, as described herein, the semiconductor layer that receives light to generate an electrical signal can be electrically disconnected or electrically disconnected from the anode of the first sensing element. In such an embodiment, a black matrix layer disposed on the semiconductor layer can cover the semiconductor layer to block light from the outside. Therefore, only the noise signal generated from the first sensor driving circuit can be measured. The readout circuit can easily remove the noise generated by the second sensor driving circuit from the signal measured by the second sensor using this noise signal. Therefore, a display device with improved sensing reliability can be provided.

[0266] This invention should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of this invention to those skilled in the art.

[0267] Although the present invention has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A display device, characterized in that, include: Display panel, including the display area defined therein. The display panel includes: Pixels, including pixel driving circuits and light-emitting elements; and The first sensor includes a first sensor driving circuit and a first sensing element. The first sensing element includes a first electrode electrically connected to the first sensor driving circuit, a semiconductor layer electrically disconnected from the first electrode, and a second electrode electrically connected to the semiconductor layer. The light-emitting element is electrically connected to the pixel driving circuit and the second electrode.

2. The display device according to claim 1, characterized in that, The display panel further includes a second sensor, which includes a second sensor driving circuit and a second sensing element different from the first sensing element. The display area is defined by a first region and a second region adjacent to the first region. The second sensor is disposed in the first area. The second sensing element includes a first electrode electrically connected to the second sensor driving circuit, a semiconductor layer electrically connected to the first electrode of the second sensing element, and a second electrode electrically connected to the semiconductor layer of the second sensing element. The first sensor is located in the second region.

3. The display device according to claim 2, characterized in that, The second sensor driving circuit includes: The second reset transistor includes a gate electrode that receives a reset control signal, a first electrode that receives a first reset voltage, and a second electrode connected to a first sensing node therein. The second amplifying transistor includes a first electrode for receiving a sensor drive voltage, a second electrode connected thereto to a second sensing node, and a gate electrode connected thereto to the first sensing node; and The second output transistor includes a first electrode connected to the second sensing node therein, a second electrode connected to the readout line, and a gate electrode for receiving an output control signal.

4. The display device according to claim 3, characterized in that, The first sensor driving circuit includes: The first reset transistor includes a gate electrode for receiving the reset control signal, a first electrode, and a second electrode connected thereto to the first sensing node; A first amplifying transistor includes a first electrode receiving the sensor drive voltage, a second electrode connected thereto to a second sensing node, and a gate electrode connected thereto to the first sensing node; and The first output transistor includes a first electrode connected to the second sensing node therein, a second electrode connected to the readout line, and a gate electrode for receiving the output control signal.

5. The display device according to claim 4, characterized in that, The first reset voltage is provided to the first electrode of the first reset transistor, or A second reset voltage having a voltage level different from the first reset voltage is provided to the first electrode of the first reset transistor.

6. The display device according to claim 3, characterized in that, The first sensor driving circuit includes: A first amplifying transistor includes a first electrode receiving the sensor drive voltage, a second electrode connected thereto to the second sensing node, and a gate electrode receiving a second reset voltage having a voltage level different from the first reset voltage; and The first output transistor includes a first electrode connected to the second sensing node therein, a second electrode connected to the readout line, and a gate electrode for receiving the output control signal.

7. The display device according to claim 2, characterized in that, Also includes: An anti-reflective layer is provided on the display panel. The anti-reflective layer includes: A black matrix layer having a first opening that overlaps with the light-emitting element therein when viewed in a plan view; and A color filter layer is disposed on the first opening.

8. The display device according to claim 7, characterized in that, When viewed in the plan view, a second opening overlapping the second sensing element is defined in the black matrix layer, and When viewed in the plan view, a third opening is defined in the black matrix layer that overlaps with the first sensing element.

9. The display device according to claim 7, characterized in that, When viewed in the plan view, the black matrix layer overlaps with the first sensing element. The first region includes a first-first region and a second-first region disposed between the first-first region and the second region. A second opening overlapping the second sensing element is defined in the black matrix layer within the first-first region, and The black matrix layer overlaps with the second sensing element in the second-first region.

10. The display device according to claim 2, characterized in that, A third region is defined within the display area, adjacent to the first region and the second region. Each of the first and second sensors is spaced apart from the third region.

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