Display panel and display device

Abstract

The utility model provides a display panel and a display device, and belongs to the technical field of display. The display panel is provided with a display area and a non-display area surrounding the display area. The display area is divided into at least two sub-areas; the display panel comprises a substrate, a plurality of sub-pixels and a plurality of first electrode leads, wherein the sub-pixels and the first electrode leads are arranged on the substrate; the cathodes of the sub-pixels in the same sub-region are connected into an integrated structure and are marked as sub-electrodes; the sub-electrodes in different sub-regions are arranged at intervals; different sub-electrodes are electrically connected with different first electrode leads, and the first electrode leads are used for transmitting cathode voltage signals to the sub-electrodes electrically connected with the first electrode leads; the cathode voltage signals are determined based on gray-scale values of the sub-pixels located in the same sub-region.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, the application of display panels is more and more common, and the performance requirements of users for display panels are also higher and higher. For example, in terms of power consumption, users hope that the display product can save power consumption while normally displaying, so as to prolong the service life of the product. Therefore, how to reduce power consumption is an important problem to be solved in the display field. CONTENT OF THE UTILITY MODEL

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a display panel and a display device.

[0004] In a first aspect, a technical solution adopted to solve the technical problems of the present disclosure is a display panel, which has a display area and a non-display area surrounding the display area; the display area is divided into at least two sub-areas; the display panel comprises a substrate, a plurality of sub-pixels and a plurality of first electrode leads arranged on the substrate.

[0005] The cathodes of the sub-pixels located in the same sub-area are connected as an integral structure, which is denoted as a sub-electrode; the sub-electrodes located in different sub-areas are arranged at intervals.

[0006] Different sub-electrodes are electrically connected to different first electrode leads, and the first electrode leads are used to transmit a cathode voltage signal to the sub-electrodes electrically connected thereto; the cathode voltage signal is determined based on the gray scale value of the sub-pixel located in the same sub-area.

[0007] In some embodiments, the display panel further has a binding area located on the side of the non-display area away from the display area; the display panel further comprises a driving chip located in the binding area; the first electrode leads are electrically connected to the driving chip.

[0008] The driving chip is configured to obtain a pre-set target correlation relationship; the target correlation relationship comprises a corresponding relationship between each gray scale value and a target voltage; a maximum gray scale value is selected from the gray scale values of each sub-pixel in the sub-area; according to the target correlation relationship, a target voltage corresponding to the maximum gray scale value is determined; according to the target voltage, the cathode voltage signals of each sub-pixel in the sub-area are determined.

[0009] In some embodiments, the target voltage is a compensation voltage; the target correlation is a pre-set correspondence between each gray scale value and the compensation voltage; and the driving chip is configured to determine the cathode voltage signal of each of the sub-pixels in the sub-region according to the target voltage, specifically by determining the cathode voltage signal of each of the sub-pixels in the sub-region according to the pre-stored initial cathode voltage and the compensation voltage.

[0010] In some embodiments, the display panel further comprises a pixel driving circuit for driving the sub-pixels; and the pixel driving circuit at least comprises a driving transistor.

[0011] The initial cathode voltage is a knee voltage of the driving transistor under 255 gray scale driving; the knee point is an intersection point of a tangent line of a linear region and a saturation region of a working characteristic curve of the driving transistor; a first voltage corresponding to the saturation region is less than the knee voltage, and a second voltage corresponding to the linear region is greater than the knee voltage; and a driving current of the driving transistor in the saturation region is constant.

[0012] In some embodiments, the target voltage is a knee voltage of the driving transistor under the maximum gray scale value; and the target correlation is a pre-set correspondence between each gray scale value and the knee voltage.

[0013] The driving chip is configured to determine the cathode voltage signal of each of the sub-pixels in the sub-region according to the target voltage, specifically by taking the knee voltage corresponding to the maximum gray scale value as the cathode voltage signal of each of the sub-pixels in the sub-region; the knee point is an intersection point of a tangent line of a linear region and a saturation region of a working characteristic curve of the driving transistor, a first voltage corresponding to the saturation region is less than the knee voltage, and a second voltage corresponding to the linear region is greater than the knee voltage.

[0014] In some embodiments, the display panel comprises four sub-electrodes; the four sub-electrodes are divided into two groups of sub-electrodes arranged side by side along a first direction, each group of sub-electrodes comprising two sub-electrodes arranged side by side along a second direction; and the first direction and the second direction are arranged crosswise.

[0015] The display panel further comprises a binding area located on a side of the non-display area away from the display area.

[0016] The sub-circuit extends from the display area to the non-display area and is electrically connected with the first electrode lead; and in the second direction, the first electrode lead extends from the non-display area to the binding area and is electrically connected with the driving chip located in the binding area.

[0017] In some embodiments, the first electrode lead to which the two sub-electrodes in the sub-electrode group are respectively electrically connected has a projection on the substrate that at least partially overlaps.

[0018] In some embodiments, the two sub-electrodes in the sub-electrode group are respectively denoted as a first sub-electrode and a second sub-electrode, the first sub-electrode is farther away from the binding area than the second sub-electrode, the first electrode lead electrically connected to the first sub-electrode is denoted as a first sub-lead, and the first electrode lead electrically connected to the second sub-electrode is denoted as a second sub-lead.

[0019] The first length of the first sub-lead in the second direction is greater than the second length of the second sub-lead in the second direction, and the first width of the first sub-lead in the first direction is equal to the second width of the second sub-lead in the first direction.

[0020] In some embodiments, the projection of the first sub-lead on the substrate is a first pattern, the projection of the second sub-lead on the substrate is a second pattern, the first pattern passes through the second pattern in the second direction, and the part of the first pattern that passes through the second pattern completely overlaps the second pattern.

[0021] In some embodiments, in the first direction, the first sub-electrode away from the first side of the display area is aligned with the second sub-lead away from the second side of the display area, and in the first direction, the second sub-electrode away from the third side of the display area is aligned with the second sub-lead away from the fourth side of the display area.

[0022] In some embodiments, the sub-area includes a first area located in the display area and a second area located in a non-display area.

[0023] The first sub-electrode located in the first area and the second sub-electrode located in the first area are disposed in the same layer.

[0024] The first sub-electrode located in the second area is multiplexed as part of the first sub-lead, and the display panel further includes an insulating layer disposed on a side of the first sub-lead away from the substrate, and the second sub-lead is disposed on a side of the insulating layer away from the first sub-lead.

[0025] The second sub-electrode located in the second area is multiplexed as part of the second sub-lead.

[0026] In some embodiments, the sub-area includes a first area located in the display area and a second area located in a non-display area.

[0027] The first sub-electrode located in the first area and the second sub-electrode located in the first area are arranged in the same layer;

[0028] The first sub-electrode located in the second area is overlapped on the surface of the first sub-lead away from the substrate substrate;

[0029] The display panel further comprises an insulating layer arranged on the side of the first sub-lead away from the substrate substrate, and the second sub-lead is arranged on the side of the insulating layer away from the first sub-electrode;

[0030] The second sub-electrode located in the second area is overlapped on the surface of the second sub-lead away from the substrate substrate.

[0031] In a second aspect, the embodiments of the present disclosure further provide a display device, comprising the display panel of any one of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A plan view of the display panel under Example 1 provided by the embodiments of the present disclosure;

[0033] Figure 2 A control system schematic diagram of the display panel provided by the embodiments of the present disclosure;

[0034] Figure 3 A circuit diagram of the pixel driving circuit provided by the embodiments of the present disclosure;

[0035] Figure 4a A working characteristic curve diagram of the driving transistor under 240 gray scale driving provided by the embodiments of the present disclosure;

[0036] Figure 4b A working characteristic curve diagram of the driving transistor under 186 gray scale driving provided by the embodiments of the present disclosure;

[0037] Figure 4c A working characteristic curve diagram of the driving transistor under 128 gray scale driving provided by the embodiments of the present disclosure;

[0038] Figure 5 A side view of the first sub-lead and the second sub-lead under an example provided by the embodiments of the present disclosure;

[0039] Figure 6 A plan view of the display panel under Example 2 provided by the embodiments of the present disclosure;

[0040] Figure 7 A schematic diagram of the sub-electrode and the sub-lead under an example provided by the embodiments of the present disclosure;

[0041] Figure 8aA plane view of the first sub-wire and the first sub-electrode provided by an embodiment of the present disclosure;

[0042] Figure 8b A plane view of the second sub-wire and the second sub-electrode provided by an embodiment of the present disclosure;

[0043] Figure 8c A plane view of the sub-electrode and the sub-wire provided by an embodiment of the present disclosure; Figure 7 A cross-sectional view of the structure A-A' shown in the figure;

[0044] Figure 9 A plane view of the sub-electrode and the sub-wire provided by an embodiment of the present disclosure;

[0045] Figure 10a A side view of the structure shown in the figure; Figure 9 A cross-sectional view of the structure B-B' shown in the figure;

[0046] Figure 10b A cross-sectional view of the structure B-B' shown in the figure; Figure 9 A cross-sectional view of the structure B-B' shown in the figure;

[0047] Figure 11 A partial film layer structure diagram of the display panel provided by an embodiment of the present disclosure;

[0048] Figure 12 A flow chart of the display control method provided by an embodiment of the present disclosure;

[0049] Figure 13 A curve diagram of the interpolated cathode voltage corresponding to different gray scales provided by an embodiment of the present disclosure;

[0050] Figure 14 A structure schematic diagram of a computer device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the accompanying drawings of the embodiments of the present disclosure to make a clear and complete description of the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. The components of the embodiments of the present disclosure described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed present disclosure, but only represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0052] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by a person having ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" do not denote a quantity of any number, but mean the existence of at least one. The terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and equivalents thereof, and do not exclude other elements or objects. The terms "connected" or "linked" do not mean only physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0053] In the present disclosure, "a plurality of or several" means two or more. The term "and / or" describes an associated relationship between associated objects, and means that three relationships can exist, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally means that the associated objects before and after it are in an "or" relationship.

[0054] It should be noted that in the present disclosure, the first direction X, the second direction Y, and the third direction Z are perpendicular to each other in pairs, and in the present disclosure, the first direction X and the second direction Y are perpendicular to each other in the plane of the substrate, the first direction X is a horizontal direction, the second direction Y is a vertical direction, and the third direction Z is a vertical direction, which is perpendicular to the plane of the substrate. It is illustrated as an example, but does not limit the present disclosure.

[0055] It should be noted that the transistors used in the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, the source and drain are not distinguished. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. When a P-type transistor is used, the source and drain are turned on when a low-level signal is input to the gate; when an N-type transistor is used, the source and drain are turned on when a high-level signal is input to the gate. In the embodiments of the present disclosure, the data writing transistor T1 and the driving transistor T2 are both taken as examples of P-type transistors for specific description.

[0056] Organic light-emitting diodes (OLEDs) are light-emitting devices that use organic solid-state semiconductors as light-emitting materials. Due to their advantages such as simple fabrication process, low cost, low power consumption, high brightness, and wide operating temperature range, they have broad application prospects. For an OLED display panel, its structure mainly includes a substrate and multiple light-emitting devices (or sub-pixels) disposed on the substrate. There are three types of light-emitting devices: red, green, and blue. Each light-emitting device includes a light-emitting functional layer, an anode, and a cathode. The anode and cathode are located on opposite sides of the light-emitting functional layer along its thickness direction. Power consumption is related to voltage and current, i.e., P = U × I, where P represents power consumption, U represents voltage, and I represents current. Specifically, the power consumption of the light-emitting device is P = (VDD - VSS) × Id, where VDD represents the power supply voltage, VSS is the cathode voltage, and Id is the driving current. However, in existing technologies, because the cathodes of all light-emitting devices in the plane are uniformly laid out in a single layer, the cathode voltages are all equal. Therefore, it is impossible to dynamically adjust the cathode voltage of each sub-pixel, and they can only be driven according to the initial cathode voltage (e.g., -5V or -5.2V). However, as the grayscale decreases, the gate-source voltage Vgs of the actual light-emitting device decreases, and the inflection points of the linear and saturation regions of the TFT operating curve shift towards the origin, meaning the inflection point voltage increases. If all pixels at this point provide the same initial cathode voltage (-5.2V), the power consumption of low-grayscale light-emitting devices will be higher than that of high-grayscale light-emitting devices with the same cathode, thus affecting device lifespan.

[0057] Therefore, embodiments of this disclosure provide a display panel, Figure 1 This is a plan view of the display panel provided in Example 1 of the embodiments of this disclosure, as shown below. Figure 1 As shown, the display panel has a display area AA and a non-display area BB surrounding the display area AA; the display area AA is divided into at least two sub-regions 01; the display panel includes a substrate 10, a plurality of sub-pixels 5 disposed on the substrate 10, and a plurality of first electrode leads 1. Figure 11 As shown, sub-pixels 5 include a light-emitting functional layer 51, an anode 52, and a cathode 53. The anode 52 and cathode 53 are located on opposite sides of the light-emitting functional layer 51 along its thickness direction (Z direction). The light-emitting functional layer 51 emits light under the drive of cathode and anode voltages. Multiple sub-pixels 5 are located in the display area AA, and the first electrode lead 1 is at least partially located in the non-display area BB. Optionally, as... Figure 1As shown, the first electrode lead 1 is located in the non-display area BB, and the sub-electrode 2 extends from the display area AA to the non-display area BB and is electrically connected with the first electrode lead 1 located in the non-display area BB. Alternatively, the sub-electrode 2 is located in the display area AA, and the first electrode lead 1 extends from the non-display area BB to the display area AA and is electrically connected with the sub-electrode 2.

[0058] In the embodiment of the present disclosure, the cathodes of the sub-pixels 5 located in the same sub-region 01 are connected as an integrated structure, denoted as a sub-electrode 2; the sub-electrodes 2 located in different sub-regions 01 are arranged at intervals; different sub-electrodes 2 are electrically connected with different first electrode leads 1, and the first electrode lead 1 is used to transmit a cathode voltage signal to the sub-electrode 2 electrically connected therewith; the cathode voltage signal is determined based on the gray scale value of the sub-pixel 5 located in the same sub-region 01.

[0059] Alternatively, the sub-electrodes 2 are arranged in one-to-one correspondence with the first electrode leads 1. Different sub-electrodes 2 are electrically connected with different first electrode leads 1, and different first electrode leads 1 independently provide a cathode voltage signal to the sub-electrode 2 electrically connected therewith. The cathode voltage signals provided by different first electrode leads 1 can be the same or different, mainly because the cathode voltage signal is determined based on the gray scale value of the sub-pixel 5 located in the same sub-region 01, and the gray scale values of the sub-pixels 5 in different sub-regions 01 are different, so the cathode voltage signals of the sub-regions 01 finally determined can also be different.

[0060] Alternatively, the orthographic projections of the sub-electrodes 2 on the substrate 10 do not overlap.

[0061] Alternatively, the sub-electrodes 2 of each sub-region 01 can be located in the same layer. Specifically, the sub-electrodes 2 located in each sub-region 01 can be formed by a one-time mask plate process. For example, the cathode material is first deposited, and then exposed, developed and etched by a mask plate process to form each sub-electrode 2 arranged at intervals.

[0062] Alternatively, at least part of the plurality of sub-electrodes 2 are located in different layers. Specifically, the display panel includes a plurality of layers of superimposed cathode layers, and an insulating layer is used to insulate the superimposed cathode layers of adjacent two layers. For a single layer of cathode layer, at least two sub-electrodes 2 therein can be formed by a one-time mask plate process. For example, the cathode material is first deposited, and then exposed, developed and etched by a mask plate process to form each sub-electrode 2 arranged at intervals. Different layers of cathode layers can be formed by different times of mask plate processes.

[0063] In the embodiment of the present disclosure, a plurality of sub-regions 01 are divided, and the cathode sub-circuits located in different sub-regions 01 independently receive cathode voltage signals, which are reasonably determined based on the gray scale values of the sub-pixels 5 located in the same sub-region 01. In this way, the most appropriate cathode voltage signals can be configured for the sub-pixels 5 in different sub-regions 01 to reduce the overall power consumption of the display panel.

[0064] In some embodiments, as shown in Figure 1 the display panel also has a binding area CC located on the side of the non-display area BB away from the display area AA; the display panel further includes a driving chip 3 (IC) located in the binding area CC; the driving chip 3 will be bent to the back light side of the display panel for fixation before product packaging. The first electrode lead 1 extends to the binding area CC and is electrically connected with the driving chip 3. Different first electrode leads 1 are electrically connected with different pins on the driving chip 3, and the driving chip 3 outputs the cathode voltage signal corresponding to the sub-region 01 to the first electrode lead 1 corresponding to the sub-region 01 through the corresponding pin, so as to provide the corresponding sub-electrode 2.

[0065] Figure 2 The control system schematic diagram of the display panel provided by the embodiments of the present disclosure is shown in Figure 2 the driving chip 3 is configured to obtain a target correlation relationship set in advance; the target correlation relationship includes a corresponding relationship between each gray scale value and a target voltage; the maximum gray scale value is selected from the gray scale values of each sub-pixel 5 in the sub-region 01; the target voltage corresponding to the maximum gray scale value is determined according to the target correlation relationship; and the cathode voltage signal of each sub-pixel 5 in the sub-region 01 is determined according to the target voltage.

[0066] The target correlation relationship can be stored in the form of table data (LUT) in the memory, and each gray scale value has a target voltage corresponding thereto. The target voltage can be a cathode voltage measured in advance, or a compensation voltage, which can be set according to the actual application scenario, and the embodiments of the present disclosure are not limited.

[0067] Optionally, the target voltage can be the inflection point voltage of the driving transistor T2 under the driving of the gray scale value; at this time, the target correlation relationship is the corresponding relationship between each gray scale value and the inflection point voltage set in advance. Therefore, the target voltage can be directly used as the cathode voltage signal of each sub-pixel 5 in the sub-region 01. The display panel includes a pixel driving circuit 4, and the pixel driving circuit 4 is used to provide a driving current for the light emitting device OLED, Figure 3 The circuit diagram of the pixel driving circuit provided by the embodiments of the present disclosure is shown in Figure 3As shown, taking the simplest 2T1C (two transistors and one capacitor) pixel driving circuit 4 as an example, the pixel driving circuit 4 includes a data writing transistor T1, a driving transistor T2 and a storage capacitor Cst. The source of the data writing transistor T1 is electrically connected to a data line in the display panel, the source of the data writing transistor T1 is electrically connected to the gate of the driving transistor T2, and the gate of the data writing transistor T1 is electrically connected to a gate line Gate in the display panel. The source of the driving transistor T2 is electrically connected to a first power supply line (VDD line), and the drain of the driving transistor T2 is electrically connected to the anode of the light emitting device OLED. As the input gray scale of the light emitting device OLED decreases, that is, the input data voltage signal Vdata decreases, the gate-source voltage Vgs of the driving transistor T2 decreases, and the inflection point moves towards the origin. Figure 4a a working characteristic curve of the driving transistor under 240 gray scale driving provided by the embodiment of the present disclosure, Figure 4b a working characteristic curve of the driving transistor under 186 gray scale driving provided by the embodiment of the present disclosure, Figure 4c a working characteristic curve of the driving transistor under 128 gray scale driving provided by the embodiment of the present disclosure, as Figures 4a-4c As shown, the horizontal axis represents the cathode voltage of the light emitting device OLED, and the vertical axis represents the brightness (which can represent the change of the driving current Id of the light emitting device OLED); the inflection point is the intersection point of the tangent line of the linear region and the saturation region of the working characteristic curve of the driving transistor T2. The first voltage corresponding to the saturation region is less than the inflection point voltage, and the second voltage corresponding to the linear region is greater than the inflection point voltage. Among them, the part of the curve in the saturation region remains unchanged as the first voltage increases, according to the brightness change; the part of the curve in the linear region decreases as the second voltage increases, according to the brightness change. As Figure 4a As shown, it is the working characteristic curve of the driving transistor T2 under 240 gray scale, and the inflection point voltage is -4.9V. As Figure 4b As shown, it is the working characteristic curve of the driving transistor T2 under 186 gray scale, and the inflection point voltage is -4V. As Figure 4cAs shown, it is the working characteristic curve of the driving transistor T2 under 128 gray scale, and the inflection point voltage is -3V. It means that the inflection point voltage of different gray scales is different, the lower the gray scale is, the greater the inflection point voltage is; on the contrary, the higher the gray scale is, the smaller the inflection point voltage is. It is known that the corresponding inflection point voltage of the driving transistor T2 under the highest gray scale 255 is -5.2V, therefore, the greater the adjustable voltage range of the low gray scale is compared with the high gray scale, for example, the adjustable voltage range of the low gray scale 128 is -5.2V~ -3V, and the voltage between -5.2V~ -3V belongs to the adjustable voltage in the saturation region, because the driving current Id of the driving transistor T2 is unchanged in the adjustable voltage range -5.2V~ -3V. It is known from the light emitting device OLED power consumption P=(VDD-VSS)×Id that, in the case of unchanged Id, the higher the cathode voltage VSS is, the lower the power consumption P of the light emitting device OLED is. That is to say, compared with selecting -5.2V as the cathode voltage, the driving transistor T2 selects the inflection point voltage -3V in the adjustable voltage range -5.2V~ -3V as the cathode voltage, and the power consumption P of the light emitting device OLED is lower. Therefore, when the target association relationship is established, the cathode voltage is set based on the inflection point voltage in the embodiment of the disclosure, and the power consumption of each sub-pixel 5 under the maximum gray scale value can be saved.

[0068] The first voltage in the saturation region is the adjustable cathode voltage range, and the first voltage in the range is less than the inflection point voltage. As shown in FIG. 2, the first voltage is greater (or the absolute value is smaller), and the power consumption P=(VDD-VSS)×Id is smaller. Figures 4a-4c As shown, the greater the first voltage is (or the absolute value is smaller), the smaller the power consumption P=(VDD-VSS)×Id is. The inflection point voltage of the driving transistor T2 under 255 gray scale driving is smaller than the inflection point voltage corresponding to 0~254 gray scale respectively, as shown in Table 1, in the case of the power supply voltage VDD being 3V, the inflection point voltage corresponding to 240 gray scale is -4.9V, the inflection point voltage corresponding to 186 gray scale is -4V, the inflection point voltage corresponding to 128 gray scale is -3V, and the inflection point voltage corresponding to 64 gray scale is -2.7V. Therefore, the lower the gray scale is, the greater the inflection point voltage is, and the greater the adjustable cathode voltage range is, for example, the adjustable cathode voltage range of 64 gray scale is between -5.2V~ -2.7V; the adjustable cathode voltage range of 128 gray scale is between -5.2V~ -3V; the adjustable cathode voltage range of 186 gray scale is between -5.2V~ -4V; and the adjustable cathode voltage range of 240 gray scale is between -5.2V~ -4.9V. It is known that the greater the adjustable cathode voltage range is, the greater the cathode voltage is (the absolute value is smaller), and the more power consumption can be saved, therefore, compared with the high gray scale 240, the low gray scale 64 can adjust the cathode voltage to -2.7V, so the power consumption P of the low gray scale 64 is smaller than the power consumption P of the high gray scale 240.

[0069] Table 1

[0070] Grey scale Inflection voltage (V) 255 -5.2V 240 -4.9V 186 -4V 128 -3V 64 -2.7V

[0071] It should be noted that according to the above analysis, the lower the gray scale, the greater the actual cathode voltage signal (the smaller the absolute value); on the contrary, the higher the gray scale, the fewer the cathode voltage signals that meet the saturation region condition, and the smaller the cathode voltage signal (the greater the absolute value). The maximum gray scale value in the sub-region 01 is selected in the present disclosure in order to avoid the cathode voltage signal of part of the sub-pixels 5 (the sub-pixels 5 with a gray scale value less than the maximum gray scale value) in the sub-region 01 being greater than the inflection point voltage corresponding to the maximum gray scale value, so as to enter the linear region. Because entering the linear region means that a slight fluctuation in voltage will cause a large change in current and brightness. By way of reductio ad absurdum, as shown in FIGS. 16 and 17, for example, there are sub-pixels 5 with a gray scale of 240 gray scales and 186 gray scales in the sub-region 01. It is known that the inflection point voltages of 240 gray scales and 186 gray scales are -4.9V and -4V, respectively. If the inflection point voltage of the low gray scale is selected as the target voltage, that is, -4V, then the cathode voltage of the sub-pixel 5 with a high gray scale (240 gray scales) will inevitably enter the linear region, which cannot meet the constant driving current Id condition. Therefore, the present disclosure selects the inflection point voltage of the maximum gray scale value in the sub-region 01 as the cathode voltage signal of each sub-pixel 5 in the sub-region 01. Figure 4a and Figure 4b As shown in FIGS. 16 and 17, for example, there are sub-pixels 5 with a gray scale of 240 gray scales and 186 gray scales in the sub-region 01. It is known that the inflection point voltages of 240 gray scales and 186 gray scales are -4.9V and -4V, respectively. If the inflection point voltage of the low gray scale is selected as the target voltage, that is, -4V, then the cathode voltage of the sub-pixel 5 with a high gray scale (240 gray scales) will inevitably enter the linear region, which cannot meet the constant driving current Id condition. Therefore, the present disclosure selects the inflection point voltage of the maximum gray scale value in the sub-region 01 as the cathode voltage signal of each sub-pixel 5 in the sub-region 01.

[0072] Optionally, the target voltage is a compensation voltage; the target correlation is a pre-set corresponding relationship between each gray scale value and the compensation voltage; and the driving chip 3 determines the cathode voltage signal of each sub-pixel 5 in the sub-region 01 according to the target voltage, and is specifically configured to determine the cathode voltage signal of each sub-pixel 5 in the sub-region 01 according to the pre-stored initial cathode voltage and the compensation voltage. The initial cathode voltage is the inflection point voltage of the driving transistor T2 under the driving of 255 gray scales.

[0073] Here, the compensation voltage corresponding to each gray scale value is calculated according to the inflection point voltage corresponding to each gray scale value and the known initial cathode voltage, that is, ofs = m-n, where ofs represents the compensation voltage, m represents the initial cathode voltage, and n represents the inflection point voltage. The calculation process of the inflection point voltage corresponding to each gray scale value can be referred to the display control method described below. The specific calculation process of the cathode voltage signal of the sub-region 01 can be referred to the formula: y = x + ofs, where x represents the input initial cathode voltage; ofs represents the compensation voltage to be compensated corresponding to the maximum gray scale value; and y represents the cathode voltage signal of each sub-pixel 5 in the sub-region 01. As shown in Table 2, it is each voltage parameter in the compensation process.

[0074] Table 2 is the cathode voltage before and after compensation

[0075] Grey scale Initial cathode voltage Inflection voltage Compensation voltage Cathode voltage 255 -5.2V -5.2V 0V -5.2V 240 -5.2V -4.9V -0.3V -4.9V 186 -5.2V -4V -1.2V -4V 128 -5.2V -3V -2.2V -3V 64 -5.2V -2.7V -2.5V -2.7V

[0076] In some embodiments, as shown in FIG. 1, the display panel includes four sub-electrodes 2; the four sub-electrodes 2 are divided into two groups of sub-electrodes 20 arranged side by side along a first direction X, each group of sub-electrodes 20 includes two sub-electrodes 2 arranged side by side along a second direction Y; the first direction X and the second direction Y are arranged crosswise, for example, the first direction X and the second direction Y are arranged perpendicularly. Here, the orthographic projection of the four sub-electrodes 2 on the substrate 10 is arranged in a rectangular array, that is, 2x2 sub-electrodes 2. Figure 1 As shown in FIG. 1, the display panel further includes a binding area CC located away from the display area AA on one side of the non-display area BB; the sub-circuit extends from the display area AA to the non-display area BB and is electrically connected with the first electrode lead 1; in the second direction Y, the first electrode lead 1 extends from the non-display area BB to the binding area CC and is electrically connected with the driving chip 3 located in the binding area CC.

[0077] Figure 1 Optionally, the orthographic projection of the first electrode lead 1 electrically connected with the two sub-electrodes 2 in the group of sub-electrodes 20 on the substrate 10 at least partially overlaps, so that the frame width of the display panel can be reduced, which is conducive to realizing narrow frame.

[0078] The first electrode lead 1 extends along the second direction Y. Optionally, as shown in FIG. 1, the two sub-electrodes 2 in the group of sub-electrodes 20 are respectively marked as a first sub-electrode 21 and a second sub-electrode 22, the first sub-electrode 21 is farther away from the binding area CC than the second sub-electrode 22, the first electrode lead 1 electrically connected with the first sub-electrode 21 is marked as a first sub-lead 11, and the first electrode lead 1 electrically connected with the second sub-electrode 22 is marked as a second sub-lead 12.

[0079] For a first sub-lead and a second sub-lead under an example provided by the embodiments of the present disclosure, as shown in FIG. 2, a first length of the first sub-lead 11 in the second direction Y is greater than a second length of the second sub-lead 12 in the second direction Y. The difference between the first length and the second length is at least greater than the size of the first sub-electrode 21 in the second direction Y. Figure 1 Figure 5 Optionally, as shown in FIG. 1, the width (that is, the size in the first direction X) of the first sub-lead 11 is equal to the width (that is, the size in the first direction X) of the second sub-lead 12. Optionally, the orthographic projection of the first sub-lead 11 on the substrate 10 is a first pattern; the orthographic projection of the second sub-lead 12 on the substrate 10 is a second pattern. The first pattern passes through the second pattern in the second direction Y, and the part of the first pattern passing through the second pattern completely overlaps the second pattern, so that the frame width of the display panel can be reduced, which is conducive to realizing narrow frame. Figure 5

[0080] Optionally, as shown in FIG. 1, the width (that is, the size in the first direction X) of the first sub-lead 11 is equal to the width (that is, the size in the first direction X) of the second sub-lead 12. Optionally, the orthographic projection of the first sub-lead 11 on the substrate 10 is a first pattern; the orthographic projection of the second sub-lead 12 on the substrate 10 is a second pattern. The first pattern passes through the second pattern in the second direction Y, and the part of the first pattern passing through the second pattern completely overlaps the second pattern, so that the frame width of the display panel can be reduced, which is conducive to realizing narrow frame. Figure 1 ​​​​

[0081] Optionally, Figure 6 This is a plan view of the display panel in Example 2 provided in the embodiments of this disclosure, as shown below. Figure 6 As shown, in the first direction X, the first side L1 of the first sub-electrode 21 away from the display area AA is aligned with the second side L2 of the first sub-lead 11 away from the display area AA; in the first direction X, the third side L3 of the second sub-electrode 22 away from the display area AA is aligned with the fourth side L4 of the second sub-lead 12 away from the display area AA, which is beneficial for achieving a narrow bezel.

[0082] Optionally, the display panel can be configured with two electrode layers to connect the sub-electrode 2 to the first electrode lead 1, which helps to reduce the panel thickness. Specifically, Figure 7 This is a schematic diagram of a sub-electrode and sub-lead provided in an embodiment of this disclosure, as shown below. Figure 7 As shown, sub-region 01 includes a first region 011 located in display area AA and a second region 012 located in non-display area BB; wherein, the first sub-electrode 21 and the second sub-electrode 22 located in the first region 011 are disposed on the same layer; the first sub-electrode 21 located in the second region 012 is multiplexed as part of the first sub-lead 11. Figure 5 As shown, the display panel also includes an insulating layer 13 disposed on the side of the first sub-lead 11 facing away from the substrate 10, and a second sub-lead 12 disposed on the side of the insulating layer 13 facing away from the first sub-lead 11. Figure 7 As shown, the second sub-electrode 22 located in the second region 012 is reused as part of the second sub-lead 12.

[0083] like Figure 5 As shown, the insulating layer 13 extends from the second region 012 to the first transition region BB1 on the non-display region BB side (e.g., Figure 1 As shown), it is flush with the surface of the first sub-lead 11 located in the first transition region BB1 near the bonding region CC.

[0084] Figure 8a This is a planar schematic diagram of the first sub-lead and the first sub-electrode provided in an embodiment of this disclosure. Figure 8b This is a planar schematic diagram of the second sub-lead and the second sub-electrode provided in an embodiment of this disclosure. Figure 8c for Figure 7 The cross-sectional view of the structure shown in the A-A' direction is as follows. Figure 8a and Figure 8c As shown, the first sub-lead 11 and the first sub-electrode 21 are connected as a single structure, and are shared by both in the second region 012. Figure 8b and Figure 8c As shown, the second sub-lead 12 and the second sub-electrode 22 are connected as a single structure and are shared by both in the second region 012. The insulating layer 13 wraps around the side of the first sub-lead 11 near the first region 011.

[0085] As Figure 5 shown, the first sub-lead 11 and the second sub-lead 12 are spaced apart by the insulating layer 13.

[0086] Regarding the manufacturing process: first, a pattern including the first sub-lead 11 and the first sub-electrode 21 can be formed by a one-time patterning process. Then, a pattern including the insulating layer 13 is formed by a one-time patterning process, at this time, the insulating layer 13 is located in the second area 012, thus exposing the underlying structure of the first area 011. Finally, a pattern including the second sub-lead 12 and the second sub-electrode 22 is formed by a one-time patterning process, at this time, the second sub-lead 12 is located in the second area 012, falling on the surface of the insulating layer 13 away from the substrate 10, and the second sub-electrode 22 of the first area 011 is in the same layer as the first sub-electrode 21 of the first area 011.

[0087] Alternatively, the display panel deploys four layers of electrode layers to realize the connection of the sub-electrode 2 and the first electrode lead 1, which is convenient for preparation. Specifically, Figure 9 Another schematic diagram of the sub-electrode and the sub-lead provided by the embodiment of the present disclosure under another example is shown in Figure 9 , the sub-area 01 includes the first area 011 located in the display area AA and the second area 012 located in the non-display area BB; the first sub-electrode 21 located in the first area 011 and the second sub-electrode 22 located in the first area 011 are arranged in the same layer. The first sub-electrode 21 located in the second area 012 is overlapped on the surface of the first sub-lead 11 away from the substrate 10; the second sub-electrode 22 located in the second area 012 is overlapped on the surface of the second sub-lead 12 away from the substrate 10. Figure 10a A side view of the structure shown in Figure 9 , a cross-sectional view in the direction of B-B' of the structure shown in Figure 10b , a cross-sectional view in the direction of B-B' of the structure shown in Figure 9 , a cross-sectional view in the direction of B-B' of the structure shown in Figure 10a , and Figure 10b , the display panel further includes the insulating layer 13 arranged on the side of the first sub-lead 11 away from the substrate 10, and the second sub-lead 12 is arranged on the side of the insulating layer 13 away from the first sub-lead 11. The insulating layer 13 wraps the side of the first sub-lead 11 close to the first area 011.

[0088] Regarding the manufacturing process: the first sub-lead 11 and the first sub-electrode 21 are formed by two patterning processes. First, a pattern including the first sub-lead 11 is formed by a first patterning process, and a part of the first sub-lead 11 is located in the second area 012. Then, a pattern including the first sub-electrode 21 is formed on the side of the first sub-lead 11 away from the substrate 10 by a second patterning process, and the first sub-electrode 21 located in the second area 012 is overlapped on the surface of the first sub-lead 11 away from the substrate 10, and the first sub-electrode 21 located in the first area 011 is in the same layer as the first sub-lead 11. Then, a pattern including the insulating layer 13 is formed on the side of the first sub-electrode 21 located in the first area 011 away from the substrate 10 by a third patterning process, and the insulating layer 13 is located in the second area 012, thus exposing the underlying structure of the first area 011. The second sub-lead 12 and the second sub-electrode 22 are also formed by two patterning processes. First, a pattern including the second sub-lead 12 is formed by a first patterning process, and a part of the first sub-lead 11 is located in the second area 012. Then, a pattern including the second sub-electrode 22 is formed on the side of the second sub-lead 12 away from the substrate 10 by a second patterning process, and the second sub-electrode 22 located in the second area 012 is overlapped on the surface of the second sub-lead 12 away from the substrate 10, and the second sub-electrode 22 located in the first area 011 is in the same layer as the first sub-electrode 21.

[0089] In some embodiments, Figure 11 A partial film layer structure diagram of the display panel provided by the embodiments of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the display panel further includes a pixel definition layer PDL disposed on the side of the pixel driving circuit 4 away from the substrate 10; the pixel definition layer PDL is provided with a pixel opening V for defining a sub-pixel 5. Figure 11 The sub-pixel 5 includes a light-emitting functional layer 51 disposed on the side of the cathode 53 close to the substrate 10, and an anode 52 disposed on the side of the light-emitting functional layer 51 away from the cathode 53; the anodes 52 of the respective sub-pixels 5 are disposed in intervals.

[0090] In some embodiments, as shown in FIG. 2, the display panel further includes a second electrode lead 6 electrically connected to the respective anodes 52 (not shown in the figure) of the sub-pixels 5; the second electrode lead 6 has no overlap with the orthographic projection of the first electrode lead 1 on the substrate 10. Figure 1 Figure 1 In some embodiments, as shown in FIG. 2, the display panel further includes a second electrode lead 6 electrically connected to the respective anodes 52 (not shown in the figure) of the sub-pixels 5; the second electrode lead 6 has no overlap with the orthographic projection of the first electrode lead 1 on the substrate 10.

[0091] In some embodiments, as shown in FIG. 2, the display panel further includes a second electrode lead 6 electrically connected to the respective anodes 52 (not shown in the figure) of the sub-pixels 5; the second electrode lead 6 has no overlap with the orthographic projection of the first electrode lead 1 on the substrate 10. Figure 1 ​As shown, the display panel further includes a binding area CC located on the side of the non-display area BB away from the display area AA; the non-display area BB further includes a first transition area BB1 located on the side close to the binding area CC; the anode 52 is electrically connected with the second electrode lead 6 from the display area AA to the first transition area BB1; in the second direction Y, the second electrode lead 6 extends from the first transition area BB1 to the binding area CC.

[0092] It should be noted that the number of sub-regions 01 of the display area AA of the display panel provided by the embodiments of the present disclosure can be set according to actual conditions, and the four-part design can meet the design requirements of thin and light design and can also realize the design requirements of narrow frame. Of course, 2-part design, 6-part design, 8-part design, etc. can also be performed, and can be adjusted in combination with actual applications, and the embodiments of the present disclosure will not be repeated.

[0093] The above is the full description of the display panel structure provided by the embodiments of the present disclosure.

[0094] In addition, the embodiments of the present disclosure also provide a display control method, Figure 12 The flowchart of the display control method provided by the embodiments of the present disclosure is shown as Figure 12 As shown, the method includes steps S11-S13.

[0095] S11, obtaining a target correlation relationship set in advance.

[0096] The target correlation relationship includes the correspondence between each gray scale value and the target voltage.

[0097] The target correlation relationship can be stored in the form of table data (LUT) in the memory, and each gray scale value has a target voltage corresponding thereto. The target voltage can be a pre-measured cathode voltage, or a compensation voltage, which can be set according to the actual application scenario, and the embodiments of the present disclosure are not limited.

[0098] Optionally, the target voltage can be the inflection point voltage of the driving transistor under the driving of the gray scale value A.

[0099] Optionally, the target voltage can be the compensation voltage determined by the inflection point voltage of the driving transistor under the driving of the gray scale value B and the initial cathode voltage, for example, formula 1: ofs=m-n, ofs represents the compensation voltage, m represents the initial cathode voltage, and n represents the inflection point voltage. Wherein, the initial cathode voltage is the inflection point voltage of the driving transistor under the driving of 255 gray scale; the inflection point refers to the intersection point of the tangent line of the linear region and the saturation region of the driving transistor working curve; the inflection point voltage refers to the voltage corresponding to the inflection point on the driving transistor working characteristic curve; the first voltage corresponding to the saturation region is less than the inflection point voltage, and the second voltage corresponding to the linear region is greater than the inflection point voltage; the driving current of the driving transistor in the saturation region is constant.

[0100] S12, screening a maximum gray scale value from the gray scale values of each sub-pixel in the sub-region.

[0101] After the gray scale values of each sub-pixel are known, the gray scale values of all sub-pixels in the sub-region can be traversed to find the maximum gray scale value.

[0102] S13, determining a target voltage corresponding to the maximum gray scale value according to the target correlation.

[0103] The table data (LUT) includes the target voltage corresponding to each gray scale value, so that the target voltage corresponding to the maximum gray scale value can be obtained by looking up the table.

[0104] S14, determining the cathode voltage signal of each sub-pixel in the sub-region according to the target voltage.

[0105] Optionally, when the target voltage is the inflection point voltage, the target voltage can be directly used as the cathode voltage signal of each sub-pixel in the sub-region.

[0106] Optionally, when the target voltage is the compensation voltage, the pre-stored initial cathode voltage also needs to be obtained, and the compensation voltage is compensated on the basis of the initial cathode voltage, so that the cathode voltage signal of each sub-pixel in the sub-region can be obtained.

[0107] Taking the target voltage as the inflection point voltage as an example, the table data (LUT) can be prepared in advance, which includes the inflection point voltage of the driving transistor under each gray scale and is used as the most power-saving cathode voltage. For the sub-pixels in the entire sub-region, the cathode voltage under the maximum gray scale value is used for driving, so that the sub-pixels in the entire sub-region are ensured to be in the power-saving state, thereby saving the power consumption of the entire display panel.

[0108] Taking the target voltage as the compensation voltage as an example, the table data (LUT) can be prepared in advance, which includes the compensation voltage corresponding to each gray scale, and the result of compensating the initial cathode voltage by the compensation voltage is the most power-saving cathode voltage under the gray scale. For the sub-pixels in the entire sub-region, the cathode voltage under the maximum gray scale value is used for driving, so that the sub-pixels in the entire sub-region are ensured to be in the power-saving state, thereby saving the power consumption of the entire display panel.

[0109] In some embodiments, taking the target voltage as the compensation voltage as an example, the target correlation refers to the correspondence between the pre-set gray scale values and the compensation voltage.

[0110] Regarding step S14 above, the cathode voltage signal of each sub-pixel in the sub-region can be determined based on the pre-stored initial cathode voltage and compensation voltage. Specifically, refer to Formula 2: y = x + ofs, where x represents the input initial cathode voltage; ofs represents the compensation voltage to be compensated corresponding to the maximum grayscale value; and y represents the cathode voltage signal of each sub-pixel in the sub-region.

[0111] Optionally, the steps for determining the target association include S21 to S25.

[0112] S21. Write a pre-set target grayscale value into the pixel driving circuit to detect the inflection point voltage of the driving transistor in the pixel driving circuit.

[0113] Here, the "target grayscale value" can be any value between 0 and 255.

[0114] S22. Obtain the inflection point voltages corresponding to multiple target grayscale values.

[0115] Here, multiple target grayscale values ​​can be some or all of the values ​​from 0 to 255. To save workload and improve efficiency, a portion of the grayscale values ​​from 0 to 255 can be selected as target grayscale values, such as 5 groups, 8 groups, 16 groups of data, etc. For example, 64 grayscale, 128 grayscale, 186 grayscale, 240 grayscale, and 255 grayscale can be selected to detect their corresponding inflection point voltages.

[0116] S23. Interpolate the inflection point voltages corresponding to multiple target grayscale values ​​to obtain the inflection point voltages corresponding to each grayscale value from 0 to 255.

[0117] Using step S21, the inflection point voltages of the driving transistors under 64, 128, 186, 240, and 255 grayscale driving conditions are detected; Figure 13 As shown, using gray levels 64, 128, 186, 240, and 255 and their corresponding inflection point voltages of -2.7V, -3V, -4V, -4.9V, and -5.2V, an interpolation algorithm is used to obtain the inflection point voltages corresponding to gray levels 0–63, 65–127, 129–185, 187–239, and 241–255.

[0118] S24. For any gray level value, determine the compensation voltage corresponding to the gray level value based on the initial cathode voltage and the inflection point voltage corresponding to the gray level value.

[0119] For any gray level value, such as 64 gray level, based on the initial cathode voltage of -5.2V and the inflection point voltage of -2.7V corresponding to gray level 64, the compensation voltage corresponding to gray level 64 is determined to be -5.2V - (-2.7V) = -2.5V using Formula 1.

[0120] S25, establish the association between each gray scale value under 0-255 gray scale and the corresponding compensation voltage, and determine the target association.

[0121] The process of establishing the association, i.e. the process of establishing the table data (LUT), converts the curve shown in FIG. 2 into table data (LUT) and stores it. Figure 13

[0122] In some embodiments, the target association refers to the preset corresponding relationship between each gray scale value and the inflection voltage of the driving transistor at the maximum gray scale value.

[0123] For the above step S14, the inflection voltage corresponding to the maximum gray scale value can be directly used as the cathode voltage signal of each sub-pixel in the sub-region.

[0124] Optionally, the step of determining the target association includes S31-S34.

[0125] S31, write a target gray scale value preset in the pixel driving circuit to detect the inflection voltage of the driving transistor in the pixel driving circuit.

[0126] Here, the "target gray scale value" can be any one of 0-255.

[0127] S32, obtain the inflection voltage corresponding to a plurality of target gray scale values.

[0128] Here, the plurality of target gray scale values can be part or all of 0-255. In order to save work and improve work efficiency, part of the gray scale values in 0-255 can be selected as the target gray scale values, for example, 64 gray scale, 128 gray scale, 186 gray scale, 240 gray scale and 255 gray scale are selected to detect the corresponding inflection voltages.

[0129] S33, interpolate the inflection voltages corresponding to the plurality of target gray scale values to obtain the inflection voltages corresponding to each gray scale value under 0-255 gray scale.

[0130] Using step S31, the inflection voltages of the driving transistor under the driving of 64 gray scale, 128 gray scale, 186 gray scale, 240 gray scale and 255 gray scale are detected; using 64 gray scale, 128 gray scale, 186 gray scale, 240 gray scale and 255 gray scale and their respective corresponding inflection voltages -2.7V, -3V, -4V, -4.9V and -5.2V, the interpolation algorithm is used to interpolate to obtain the inflection voltages corresponding to 0-63 gray scale, 65-127 gray scale, 129-185 gray scale, 187-239 gray scale and 241-255 gray scale.

[0131] ​S34. Establish the correlation between each gray level value in the gray scale from 0 to 255 and the corresponding inflection point voltage to obtain the target correlation relationship.

[0132] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0133] In addition, this disclosure also provides a display device, which includes the display panel described in any of the above embodiments.

[0134] For example, the display device can be any product with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of the display device are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0135] The display device includes a driver chip configured to perform the steps of the display control method as described above. Since the principle by which the device solves the problem in the embodiments of this disclosure is similar to the display control method described above in the embodiments of this disclosure, the implementation of the device can be referred to the implementation of the method, and repeated details will not be described again.

[0136] In addition, this disclosure also provides a computer device. Figure 14 This is a schematic diagram of the structure of a computer device provided in an embodiment of this disclosure. Figure 14 As shown, this disclosure provides a computer device including: one or more processors 1401, a memory 1402, and one or more I / O interfaces 1403. The memory 1402 stores one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement any of the display control methods described in the above embodiments; the one or more I / O interfaces 1403 are connected between the processor and the memory, configured to enable information interaction between the processor and the memory.

[0137] The processor 1401 is a device with data processing capability, including but not limited to a central processing unit (CPU) and the like; the memory 1402 is a device with data storage capability, including but not limited to a random access memory (RAM, more specifically SDRAM, DDR, etc.), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (FLASH), and the like; the I / O interface (read-write interface) 1403 is connected between the processor 1401 and the memory 1402, and can realize information interaction between the processor 1401 and the memory 1402, including but not limited to a data bus (Bus) and the like.

[0138] In some embodiments, the processor 1401, the memory 1402 and the I / O interface 1403 are connected with each other through the bus 1404, and further connected with other components of the computing device.

[0139] According to an embodiment of the present disclosure, a computer non-transient readable storage medium is also provided. The computer non-transient readable storage medium stores a computer program, wherein the program is executed by a processor to implement the steps in the display control method of any of the above embodiments.

[0140] In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product comprising a computer program carried on a machine-readable medium, the computer program comprising program code for executing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network by a communication part, and / or installed from a detachable medium. When the computer program is executed by a central processing unit (CPU), the above-mentioned functions defined in the system of the present disclosure are executed.

[0141] It should be noted that the computer non-transitory readable medium shown in the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium may, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus. In the present disclosure, the computer readable signal medium can include a data signal carried in a baseband or as a part of a carrier wave, which carries computer readable program code. Such a propagated data signal can take many forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination of the above. The computer readable signal medium can also be any computer non-transitory readable medium that can send, propagate or transmit a program for use by or in connection with an instruction execution system, device or apparatus. The program code contained on the computer non-transitory readable medium can be transmitted by any suitable medium, including but not limited to wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0142] The flow and block diagrams in the drawings represent possible architectural, functional, and operational architectures of apparatuses, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow and block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations thereof, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or combinations of hardware and computer instructions.

[0143] It is to be understood that the above-described embodiments are merely exemplary of the principles of the present disclosure and that various modifications can be made by those skilled in the art without departing from the spirit and scope of the disclosure. Such modifications are intended to be within the scope of the present disclosure.

Claims

1. A display panel, characterized by, The display panel has a display area and a non-display area surrounding the display area; the display area is divided into at least two sub-areas; the display panel comprises a substrate, a plurality of sub-pixels arranged on the substrate, and a plurality of first electrode leads; The cathodes of the sub-pixels in the same sub-area are connected as a unit structure, denoted as a sub-electrode; the sub-electrodes in different sub-areas are arranged at intervals; Different sub-electrodes are electrically connected to different first electrode leads, and the first electrode leads are used to transmit a cathode voltage signal to the sub-electrodes electrically connected thereto; the cathode voltage signal is determined based on the gray scale value of the sub-pixels in the same sub-area.

2. The display panel of claim 1, wherein, The display panel also has a binding area located away from the display area on one side of the non-display area; the display panel further comprises a driving chip located in the binding area; the first electrode leads are electrically connected to the driving chip; The driving chip is configured to obtain a pre-set target correlation; the target correlation comprises a corresponding relationship between each gray scale value and a target voltage; the maximum gray scale value is selected from the gray scale values of each sub-pixel in the sub-area; According to the target correlation, the target voltage corresponding to the maximum gray scale value is determined; and according to the target voltage, the cathode voltage signal of each sub-pixel in the sub-area is determined.

3. The display panel of claim 2, wherein, The target voltage is a compensation voltage; the target correlation is a pre-set corresponding relationship between each gray scale value and the compensation voltage; and the driving chip determines the cathode voltage signal of each sub-pixel in the sub-area according to the target voltage, specifically configured to determine the cathode voltage signal of each sub-pixel in the sub-area according to the pre-stored initial cathode voltage and the compensation voltage.

4. The display panel of claim 3, wherein, The display panel further comprises a pixel driving circuit for driving the sub-pixels; the pixel driving circuit at least comprises a driving transistor; The initial cathode voltage is the inflection point voltage of the driving transistor under 255 gray scale driving; the inflection point refers to the intersection point of the tangent lines of the linear region and the saturation region of the working characteristic curve of the driving transistor; the first voltage corresponding to the saturation region is less than the inflection point voltage, and the second voltage corresponding to the linear region is greater than the inflection point voltage; the driving current of the driving transistor in the saturation region is constant.

5. The display panel of claim 2, wherein, The target voltage is the inflection point voltage of the driving transistor under the maximum gray scale value; the target correlation is a pre-set corresponding relationship between each gray scale value and the inflection point voltage; The driving chip determines the cathode voltage signal of each sub-pixel in the sub-area according to the target voltage, specifically configured to take the inflection point voltage corresponding to the maximum gray scale value as the cathode voltage signal of each sub-pixel in the sub-area; the inflection point refers to the intersection point of the tangent lines of the linear region and the saturation region of the working characteristic curve of the driving transistor, the first voltage corresponding to the saturation region is less than the inflection point voltage, and the second voltage corresponding to the linear region is greater than the inflection point voltage.

6. The display panel of any one of claims 1-5, wherein, The display panel comprises four sub-electrodes; the four sub-electrodes are divided into two groups of sub-electrodes arranged side by side along a first direction, each group of sub-electrodes comprises two sub-electrodes arranged side by side along a second direction; the first direction and the second direction are arranged crossly; The display panel further comprises a binding area located on the side of the non-display area away from the display area; The sub-electrodes extend from the display area to the non-display area and are electrically connected with the first electrode lead; in the second direction, the first electrode lead extends from the non-display area to the binding area and is electrically connected with the driving chip located in the binding area.

7. The display panel of claim 6, wherein, The first electrode lead to which the two sub-electrodes in the sub-electrode group are respectively electrically connected has a projection on the substrate which at least partially overlaps.

8. The display panel of claim 7, wherein, The two sub-electrodes in the sub-electrode group are respectively marked as first sub-electrode and second sub-electrode, the first sub-electrode is farther away from the binding area than the second sub-electrode, the first electrode lead electrically connected with the first sub-electrode is marked as first sub-lead, and the first electrode lead electrically connected with the second sub-electrode is marked as second sub-lead; The first length of the first sub-lead in the second direction is greater than the second length of the second sub-lead in the second direction; the first width of the first sub-lead in the first direction is equal to the second width of the second sub-lead in the first direction.

9. The display panel of claim 8, wherein, The projection of the first sub-lead on the substrate is a first pattern; the projection of the second sub-lead on the substrate is a second pattern; the first pattern passes through the second pattern in the second direction, and the part of the first pattern passing through the second pattern completely overlaps the second pattern.

10. The display panel of claim 8, wherein, In the first direction, the first side edge of the first sub-electrode away from the display area is aligned with the second side edge of the first sub-lead away from the display area; in the first direction, the third side edge of the second sub-electrode away from the display area is aligned with the fourth side edge of the second sub-lead away from the display area.

11. The display panel of claim 8, wherein, The sub-area comprises a first area located in the display area and a second area located in the non-display area; The first sub-electrode located in the first area and the second sub-electrode located in the first area are arranged in the same layer; The first sub-electrode located in the second area is multiplexed as part of the first sub-lead; the display panel further comprises an insulating layer arranged on the side of the first sub-lead away from the substrate; the second sub-lead is arranged on the side of the insulating layer away from the first sub-lead; The second sub-electrode located in the second area is multiplexed as part of the second sub-lead.

12. The display panel of claim 8, wherein, The sub-area comprises a first area located in the display area and a second area located in the non-display area; The first sub-electrode located in the first area and the second sub-electrode located in the first area are arranged in the same layer; The first sub-electrode located in the second area is overlapped on the surface of the first sub-lead away from the substrate; The display panel further comprises an insulating layer disposed on a side of the first sub-lead wire away from the substrate substrate, and the second sub-lead wire is disposed on a side of the insulating layer away from the first sub-electrode; The second sub-electrode located in the second area is overlapped on the surface of the second sub-lead wire away from the substrate substrate.

13. A display device comprising: The display panel as claimed in any one of claims 1-12.

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