Display device

Abstract

A display device includes: a first via pattern and a second via pattern over a substrate, the first via pattern and the second via pattern being spaced apart; a passivation layer over the first via pattern and the second via pattern; a first light emitting element over the passivation layer and overlapping the first via pattern; a second light emitting element over the passivation layer and overlapping the second via pattern; a first bank over the substrate between the first via pattern and the second via pattern; and a second bank above the first bank and protruding beyond a side of the first bank.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0050725, filed on April 16, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to display devices. Background Technology

[0004] With the development of the information age, the demand for display devices for displaying images has increased in various forms. For example, display devices are already used in various electronic devices, such as smartphones, digital cameras, laptops, navigators, and smart TVs. Display devices can be flat panel display devices, such as liquid crystal displays, field emission displays, and organic light-emitting displays. In flat panel display devices, the light-emitting display element includes a self-emissive light-emitting element in each pixel of the display panel, thereby displaying images even without a backlight unit that supplies light to the display panel.

[0005] Recently, display devices have been applied to eyeglasses that provide virtual and augmented reality. For eyeglasses applications, the display devices are implemented in a very small size, approximately 2 inches or less, but they can appropriately have a high pixel density, allowing for high resolution. For example, the display device can have a high pixel density of approximately 400 pixels per inch (PPI) or greater. Utility Model Content

[0006] This disclosure provides a display device in which light-emitting elements or common electrodes for each light-emitting area can be formed without a mask process.

[0007] This disclosure provides a display device in which moisture absorption or moisture penetration of the underlying organic layer of the light-emitting element is reduced to enhance durability.

[0008] The aspects of this disclosure are not limited to those described above, and other aspects of this disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description of this disclosure.

[0009] According to one or more embodiments of the display device, an organic layer or organic pattern positioned below the light-emitting element is covered with a passivation layer, and thus can be robust against moisture absorption or moisture penetration.

[0010] According to some embodiments of the present disclosure, a display device includes: a first via pattern and a second via pattern spaced apart above a substrate; a passivation layer above the first via pattern and the second via pattern; a first light-emitting element above the passivation layer and overlapping the first via pattern; a second light-emitting element above the passivation layer and overlapping the second via pattern; a first dam above the substrate between the first via pattern and the second via pattern; and a second dam above the first dam and protruding beyond the side of the first dam.

[0011] The passivation layer can cover the upper surface and side surface of the first through-hole pattern as well as the upper surface and side surface of the second through-hole pattern.

[0012] The passivation layer can define the contact hole through which the first pixel electrode of the first light-emitting element passes.

[0013] The passivation layer may include a first portion at a first height from the substrate, a second portion at a second height from the substrate, and a third portion at a third height from the substrate, wherein the third height is greater than the first height and the second height, and the second height is greater than the first height.

[0014] The passivation layer may include one or more of silicon nitride, silicon oxide nitride, and silicon oxide.

[0015] The angle between the lower surface and the side surface of the first through-hole pattern can be less than approximately 90°.

[0016] The first through-hole pattern and the second through-hole pattern may include one or more of polyimide resin, acrylic resin, epoxy resin, phenolic resin and polyamide resin.

[0017] The display device may further include a pixel defining layer between the passivation layer and the first dike and including a side protruding beyond the side of the first dike.

[0018] The display device may also include a residual pattern at the edge of the first pixel electrode of the first light-emitting element below the pixel defining layer.

[0019] The first light-emitting element may include a first pixel electrode above the passivation layer, a first light-emitting layer above the first pixel electrode, and a first common electrode above the first light-emitting layer, wherein the second light-emitting element includes a second pixel electrode above the passivation layer, a second light-emitting layer above the second pixel electrode, and a second common electrode above the second light-emitting layer and spaced apart from the first common electrode.

[0020] The first common electrode and the second common electrode can contact the first dike.

[0021] The display device may further include a first inorganic pattern above the first light-emitting element and a second inorganic pattern above the second light-emitting element and spaced apart from the first inorganic pattern.

[0022] A portion of the first inorganic pattern may be located below the lower surface of the second embankment.

[0023] According to some embodiments of the present disclosure, the display device includes: a first through-hole pattern and a second through-hole pattern spaced apart above a substrate; a first light-emitting element above the first through-hole pattern; a second light-emitting element above the second through-hole pattern; a first dam above the substrate defining a first opening overlapping the first light-emitting element and a second opening overlapping the region between the first light-emitting element and the second light-emitting element; and a second dam above the first dam and protruding beyond the side of the first dam.

[0024] The second dike may define a third opening that overlaps with the first opening of the first dike and a fourth opening that overlaps with the second opening of the first dike, wherein a first side of the second dike pointing to the third opening protrudes beyond a first side of the first dike pointing to the first opening, and wherein a second side of the second dike pointing to the fourth opening protrudes beyond a second side of the first dike pointing to the second opening.

[0025] The display device may also include a thin-film transistor between the substrate and the first dike and overlapping with a second opening of the first dike.

[0026] The display device may further include: a passivation layer between the first via pattern and the first light-emitting element, and between the substrate and the first barrier; and a pixel defining layer between the passivation layer and the first barrier.

[0027] The second opening of the first dike can overlap with the passivation layer.

[0028] At least a portion of the second opening of the first embankment may not overlap with the pixel-defined layer.

[0029] The thickness of the pixel-defining layer adjacent to the first dike can be greater than the thickness of the pixel-defining layer adjacent to the center of the second opening of the first dike.

[0030] The aspects of embodiments according to this disclosure are not limited to those described above, and many more different aspects are included in the following description of this disclosure. Attached Figure Description

[0031] The above and other aspects of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0032] Figure 1 This is a perspective view showing a display device according to one or more embodiments;

[0033] Figure 2 It shows the fold and is viewed from the front. Figure 1 A plan view of the display device;

[0034] Figure 3 It shows the fold and is viewed from the side. Figure 1 A cross-sectional view of the display device;

[0035] Figure 4 It is shown Figure 2 An enlarged plan view of region B;

[0036] Figure 5 It is a cross-sectional view showing a portion of a display device according to one or more embodiments;

[0037] Figure 6 It is shown Figure 5 An enlarged sectional view of region A1;

[0038] Figure 7 It is a cross-sectional view showing a portion of a display device according to one or more embodiments;

[0039] Figure 8 It is shown Figure 7 An enlarged sectional view of region A1';

[0040] Figure 9 and Figure 10 It is an enlarged cross-sectional view showing a portion of a display device according to one or more embodiments; and

[0041] Figure 11 It is shown Figure 10 An enlarged sectional view of region A2. Detailed Implementation

[0042] Some aspects of this disclosure and methods of implementing it can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments or unnecessary for those skilled in the art to fully understand aspects of this disclosure may be omitted. Unless otherwise stated, similar reference numerals, characters, or combinations thereof denote similar elements throughout the drawings and written description, and therefore, repeated descriptions thereof may be omitted.

[0043] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The terms "can," "may," or "may not" are used in the description of one or more embodiments to correspond to one or more embodiments of this disclosure.

[0044] In view of the overall content of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable way.

[0045] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, this disclosure is not limited thereto because the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for ease of description. Furthermore, the use of crosshairs and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, scale, commonalities between the elements shown, and / or any other characteristics, properties, or characteristics of the elements.

[0046] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of implementations and / or intermediate structures. Therefore, variations in the shapes illustrated should be expected due to factors such as manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are merely exemplary for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes of the elements, layers, or regions shown, but should include deviations in shape due to factors such as manufacturing processes.

[0047] For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient in implantation concentration, rather than a binary change from the implantation region to the non-implantation region. Similarly, the implantation region formed by implantation may result in some implantation in the region between the implantation region and the surface through which the implantation occurs.

[0048] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “above,” “higher,” “upper side,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another element(s). It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the drawings is flipped, the element described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Thus, the exemplary terms “below” and “below” can encompass both upper and lower orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when a first part is described as being arranged “on” a second part, this means that the first part is arranged on the upper or lower side of the second part, not limited to its upper side based on the direction of gravity.

[0049] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic sectional view" means when viewing a schematic section taken by vertically cutting the portion of the object from the side. The terms "overlap" or "overlapped" mean that the first object may be above or below the second object, or on one side of the second object, and vice versa. Additionally, the term "overlap" can include stacking, face, or facing, extending over, covering, or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "separated from," "separated from," or "offset from," and any other suitable equivalent as will be understood and appreciated by one of ordinary skill in the art. The terms "face" and "facing" can mean that the first object may be directly opposite or indirectly opposite the second object. In the case where a third object is located between the first and second objects, the first and second objects can be understood as indirectly opposite each other, but still facing each other.

[0050] It will be understood that when a component, layer, region, or assembly is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another component, layer, region, or assembly, it can be directly formed on, directly on, directly connected to, or directly coupled to another component, layer, region, or assembly, or it can be indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to another component, layer, region, or assembly, thereby allowing for the presence of one or more intervening components, layers, regions, or assemblies. Furthermore, this can collectively mean direct connection or direct linking or indirect connection or indirect linking, as well as integral connection or integral linking or non-integral connection or non-integral linking. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly coupled to another layer, region, and / or component, or one or more intervening layers, regions, or components may exist. One or more intervening components may include switches, resistors, capacitors, etc. In describing embodiments, unless explicitly described as a direct connection, the expression "connection" indicates an electrical connection, and "directly connected / directly coupled" or "directly on" means that one component is directly connected to or directly coupled to another component or directly on another component, without any intermediate components.

[0051] Furthermore, in this specification, when a portion of a layer, film, region, plate, etc., is formed on another portion, the forming direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, plate, etc., is formed "below" another portion, this includes not only the case where the portion is "directly" "below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing the relationship between components, such as "between," "directly between," or "adjacent to," and "directly adjacent to," can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0052] For the purposes of this disclosure, when expressions such as “at least one of” or “any one of” or “one or more of” follow an element in a column, they modify the entire column and not individual elements within the column. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ) or any variation thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the related listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, when expressions such as “at least one of”, “multiple”, “one of”, and other prepositional phrases follow / before an element in a column, they modify the entire column and not individual elements within the column. When “C to D” is stated, it means C or greater and D or less, unless otherwise indicated.

[0053] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or advantage, and are used only to distinguish one element, component, assembly, area, region, layer, section, or part from another element, component, assembly, area, region, layer, section, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, first assembly, first area, first layer, or first section described below may be referred to as a second element, second assembly, second area, second layer, or second section. Describing an element as a “first” element may not require or imply the presence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0054] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0055] The terminology used herein is for descriptive purposes only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, and the plural forms are intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that the terms “comprises,” “comprising,” “have,” “having,” “includes,” and “including,” when used in this specification, designate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0056] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms and not as terms of degree, and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by those skilled in the art. For example, “substantially” can include a range of + / - 5% of the corresponding value. Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “about” or “approximately” as used herein includes the value and means within an acceptable deviation range for the particular value as determined by those skilled in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. Furthermore, when describing embodiments of this disclosure, the use of “may” means “one or more embodiments of this disclosure.”

[0057] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0058] Figure 1 This is a perspective view showing a display device according to one or more embodiments. Figure 2 It shows the fold and is viewed from the front. Figure 1 A plan view of the display device. Figure 3 It shows the fold and is viewed from the side. Figure 1 A cross-sectional view of the display device.

[0059] refer to Figure 1The display device 10 according to one or more embodiments is a device for displaying moving or still images, and can be used as a display screen for various products such as televisions, laptops, monitors, billboards and devices for the Internet of Things (IoT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic diaries, e-books, portable multimedia players (PMPs), navigators and ultra-mobile PCs (UMPCs).

[0060] The display device 10 according to one or more embodiments may be a light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, and a micro or nano light-emitting display device including micro or nano light-emitting diodes (micro or nano LEDs). The following description will be based on the premise that the display device 10 is an organic light-emitting display device, but this disclosure is not limited thereto.

[0061] The display device 10 according to one or more embodiments may include a display panel 100, a display driver 200, and a circuit board 300.

[0062] The display panel 100 can be formed as a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet can be formed as a right angle or can be rounded to have curvature. The planar shape of the display panel 100 is not limited to a rectangular shape, and can also be formed as another polygon, circle, or ellipse.

[0063] The display panel 100 can be formed as flat, but is not limited thereto. For example, the display panel 100 may include curved portions with constant or variable curvature formed at the left and right ends. Furthermore, the display panel 100 can be flexibly formed to be curved, twisted, bent, folded, or rolled.

[0064] The display panel 100 may include a main area MA and a sub-area SBA.

[0065] The main region MA can include a display region DA used to display images and a non-display region NDA not used to display images.

[0066] The display area DA can occupy most of the display panel 100. The display area DA can be located in the center of the display panel 100. Pixels, each comprising multiple light-emitting areas, can be located in the display area DA to display images. Figure 2 Region B can be part of the display region DA.

[0067] The non-display area NDA can be adjacent to the display area DA. The non-display area NDA can be an outer area of ​​the display area DA and can (e.g., in a plan view) surround the display area DA. The non-display area NDA can be an edge area of ​​the display panel 100.

[0068] A sub-region SBA can be a region extending from one side of a main region MA. The sub-region SBA can include a flexible material capable of withstanding bending, folding, curling, etc. For example, when the sub-region SBA is bent, it can overlap with the main region MA in the thickness direction (third direction DR3). The sub-region SBA can include a display driver 200 and pad areas connected to the circuit board 300. In one or more other embodiments, the sub-region SBA may be omitted, and the display driver 200 and pad areas may be located within a non-display area NDA.

[0069] refer to Figure 1 The sub-region SBA may include display pads, display driver 200, and circuit board 300.

[0070] The display pads can be located on one edge of the display panel 100. For example, the display pads can be located on the lower edge of the display panel 100. The display pads can be connected to the display driver 200 and the circuit board 300.

[0071] The display driver 200 can generate and output signals and voltages for driving the display panel 100. Specifically, the display driver 200 can generate and output data voltages, power supply voltages, scan timing signals, etc. The display driver 200 can provide power supply voltages to the power lines and can provide gate control signals to the gate driver.

[0072] The display driver 200 can be located in the non-display area NDA between the display pads and the display area DA. The display driver 200 can be attached to the non-display area NDA of the display panel 100 using a chip-on-glass (COG) method. Alternatively, the display driver 200 can be attached to the circuit board 300 using a chip-on-plastic (COP) method.

[0073] The circuit board 300 may be located on one edge of the display panel 100 and may be located on the display pads. The circuit board 300 may be attached to the display pads using conductive adhesive members such as anisotropic conductive film and anisotropic conductive adhesive. Therefore, the circuit board 300 may be electrically connected to the signal lines of the display panel 100. The circuit board 300 may be a flexible printed circuit board or a flexible film such as chip-on-film.

[0074] Figure 3 It shows the fold and is viewed from the side. Figure 1 A cross-sectional view of the display device.

[0075] refer to Figure 3 The display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, a light-emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0076] The substrate SUB can be a base substrate or a base component. The substrate SUB can be a flexible substrate capable of withstanding bending, folding, rolling, etc. For example, the substrate SUB can include, but is not limited to, a polymer resin such as polyimide (PI). In one or more other embodiments, the substrate SUB can include a glass material or a metallic material.

[0077] The thin-film transistor layer (TFTL) can be located on the substrate SUB. The TFTL can include multiple thin-film transistors constituting pixel circuitry. The TFTL can also include scan lines, data lines, power lines, scan control lines, fan-out lines connecting the display driver 200 to the data lines, and leads connecting the display driver 200 to the pad area. Each of the thin-film transistors can include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver can include a thin-film transistor.

[0078] The thin-film transistor layer (TFTL) can be located in the display area (DA), the non-display area (NDA), and the sub-area (SBA). The thin-film transistors, scan lines, data lines, and power lines of the TFTL can be located in the display area (DA). The scan control lines and fan-out lines of the TFTL can be located in the non-display area (NDA). The leads of the TFTL can be located in the sub-area (SBA).

[0079] The light-emitting element layer (EML) can be located on the thin-film transistor layer (TFTL). The EML can include multiple light-emitting elements and a pixel-defining layer defining pixels. The multiple light-emitting elements include a first electrode, a second electrode, and a light-emitting layer to emit light. The multiple light-emitting elements of the EML can be located in the display area (DA).

[0080] In one or more embodiments, the light-emitting layer may be an organic light-emitting layer comprising organic materials. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin-film transistor of the thin-film transistor layer (TFTL), and when the second electrode receives a cathode voltage, holes and electrons can move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and can combine with each other in the organic light-emitting layer to emit light.

[0081] In one or more other embodiments, the light-emitting element may include a quantum dot light-emitting diode containing a quantum dot light-emitting layer, an inorganic light-emitting diode containing an inorganic semiconductor, or a micro light-emitting diode.

[0082] The thin-film encapsulation layer TFEL can cover the top surface and sides of the light-emitting element layer EML and can protect the light-emitting element layer EML. The thin-film encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer designed to encapsulate the light-emitting element layer EML.

[0083] A color filter layer (CFL) may be located on a thin-film encapsulation layer (TFEL). The CFL may include multiple color filters, each corresponding to a plurality of light-emitting regions. Each color filter selectively transmits light of a corresponding wavelength and may block or absorb light of another wavelength. The CFL may absorb a portion of the light incident from the outside of the display device 10 to reduce reflected light caused by external light. Therefore, the CFL can reduce or prevent color distortion caused by external light reflection.

[0084] Because the color filter layer CFL is located directly on the thin-film encapsulation layer TFEL, the display device 10 does not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be relatively small.

[0085] In some embodiments, the display device 10 may further include optical devices. The optical devices may emit or receive light in the infrared, ultraviolet, or visible wavelength range. For example, the optical devices may be optical sensors for sensing light incident on the display device 10, such as proximity sensors, illuminance sensors, camera sensors, fingerprint sensors, or image sensors. In some embodiments, the circuit board 300 may be connected to other circuit elements via connector 400.

[0086] Figure 4 This is a part of a display device according to one or more embodiments. Figure 2 Enlarged plan view of region B). Figure 4 It can be a top view of the light-emitting areas EA1, EA2 and EA3 in the display area DA, as well as the through-hole patterns VP1, VP2 and VP3, as viewed from the top side of the display device 10.

[0087] although Figure 4 The diagram shows that the luminous regions EA1, EA2, and EA3 have a circular shape, but these luminous regions EA1, EA2, and EA3 can also be polygons such as triangles, squares, or hexagons. Multiple luminous regions EA1, EA2, and EA3 can be arranged in a circular shape. Type (e.g., diamond) Type) Positioning ( (This is a registered trademark of Samsung Display Co., Ltd., South Korea). For example, the first light-emitting region EA1 and the third light-emitting region EA3 may be spaced apart from each other in the first direction DR1 and may be alternately located in the first direction DR1 and the second direction DR2. The second light-emitting region EA2 may be spaced apart from another adjacent second light-emitting region EA2 in the first direction DR1 and the second direction DR2. The second light-emitting region EA2 and the first light-emitting region EA1, or the second light-emitting region EA2 and the third light-emitting region EA3, may be alternately located in the plane defined by the first direction DR1 and the second direction DR2 along any direction. The shape and arrangement of the plurality of light-emitting regions EA1, EA2 and EA3 are not limited to... Figure 4 .

[0088] The first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 can have different sizes. For example, the size of the first light-emitting area EA1 can be larger than the size of the second light-emitting area EA2, and the size of the second light-emitting area EA2 can be smaller than the size of the third light-emitting area EA3. The intensity of the light emitted from the corresponding light-emitting areas EA1, EA2, and EA3 can vary according to their sizes, and the color of the image displayed by the display device 10 can be controlled by adjusting the sizes of the light-emitting areas EA1, EA2, and EA3.

[0089] In the display device 10, a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3 that are adjacent to each other can form a pixel group. A pixel group may include light-emitting regions EA1, EA2, and EA3 that emit light of different colors to represent white grayscale levels, but this disclosure is not limited thereto. Depending on the arrangement of the light-emitting regions EA1, EA2, and EA3, the color of the light emitted from the light-emitting regions EA1, EA2, and EA3, etc., the combination of the light-emitting regions EA1, EA2, and EA3 constituting a pixel group can be modified in various ways.

[0090] Multiple through-hole patterns VP1, VP2, and VP3 can be configured, and each of these patterns can correspond to one of multiple light-emitting regions EA1, EA2, and EA3. The central portions of the through-hole patterns VP1, VP2, and VP3 can overlap with the light-emitting regions EA1, EA2, and EA3, while the edge portions can be separate from them. The edge portions of the through-hole patterns VP1, VP2, and VP3 can be exposed and not covered by the light-emitting regions EA1, EA2, and EA3. The through-hole patterns VP1, VP2, and VP3 can have dimensions larger than the corresponding light-emitting regions EA1, EA2, and EA3.

[0091] Figure 5 This is a cross-sectional view showing a portion of a display device according to one or more embodiments. In detail, Figure 5 It is along Figure 4 The image taken along line I-I' shows a cross-sectional view of the substrate SUB, thin film transistor layer TFTL, light-emitting element layer EML, thin film encapsulation layer TFEL, and color filter layer CFL.

[0092] The thin-film transistor layer (TFTL) may include a first buffer layer (BF1), a second buffer layer (BF2), a thin-film transistor (TFT), a gate insulating layer (GI), a first interlayer insulating layer (ILD1), a capacitor electrode (CPE), a second interlayer insulating layer (ILD2), a first connection electrode (CNE1), a first passivation layer (PAS1), via patterns (VP1, VP2, and VP3), and a passivation layer (PSV).

[0093] The first buffer layer BF1 may be located on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of reducing or preventing the penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic layers stacked alternately.

[0094] The lower metal layer BML can be located on the first buffer layer BF1. For example, the lower metal layer BML can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0095] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of reducing or preventing the penetration of air or moisture. For example, the second buffer layer BF2 may include multiple inorganic layers stacked alternately.

[0096] The thin-film transistor (TFT) can be located on the second buffer layer BF2 and can constitute the pixel circuit of each of a plurality of pixels. For example, the TFT can be a driving transistor or a switching transistor of the pixel circuit. The TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0097] The semiconductor layer ACT can be located on the second buffer layer BF2. The semiconductor layer ACT can overlap with the gate electrode GE in the thickness direction DR3 and can be insulated from the gate electrode GE through the gate insulating layer GI. By making the material of the semiconductor layer ACT conductive, a portion of the semiconductor layer ACT can form the source electrode SE and the drain electrode DE.

[0098] The gate electrode GE can be located on the gate insulating layer GI. The gate electrode GE can overlap with the semiconductor layer ACT in the thickness direction DR3, and the gate insulating layer GI is interposed between the gate electrode GE and the semiconductor layer ACT.

[0099] The gate insulating layer GI can be located on the semiconductor layer ACT. For example, the gate insulating layer GI can cover the semiconductor layer ACT and the second buffer layer BF2, and can insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0100] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0101] The capacitor electrode CPE can be located on the first interlayer insulating layer ILD1. The capacitor electrode CPE can overlap with the gate electrode GE in the thickness direction DR3. The capacitor electrode CPE and the gate electrode GE can form a capacitor.

[0102] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may connect to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0103] The first connection electrode CNE1 can be located on the second interlayer insulating layer ILD2. The first connection electrode CNE1 can electrically connect the drain electrode DE of the thin-film transistor TFT to the pixel electrodes AE1, AE2, and AE3. The first connection electrode CNE1 can be inserted into a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin-film transistor TFT.

[0104] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin-film transistor (TFT). The first passivation layer PAS1 may include contact holes through which pixel electrodes AE1, AE2, and AE3 pass. In one or more embodiments, the first passivation layer PAS1 may be formed of an organic layer comprising an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. Optionally, the first passivation layer PAS1 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxide nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). Optionally, the first passivation layer PAS1 may be formed of multiple layers of the aforementioned organic or inorganic materials.

[0105] Figure 6 The diagram shows in detail the first through-hole pattern VP1 and the first light-emitting area EA1. Figure 5 An enlarged cross-sectional view of region A1. In the following text, the through-hole patterns VP1, VP2, and VP3 will be described using the first through-hole pattern VP1 and the first light-emitting region EA1 as examples.

[0106] refer to Figure 5 and Figure 6 The via patterns VP1, VP2, and VP3 can be located on the first passivation layer PAS1. The first passivation layer PAS1 can have a flat upper surface while filling the step difference of the thin-film transistor TFT below it. The via patterns VP1, VP2, and VP3 can include a first via pattern VP1, a second via pattern VP2, and a third via pattern VP3. The first via pattern VP1, the second via pattern VP2, and the third via pattern VP3 can be spaced apart from each other. Each of the via patterns VP1, VP2, and VP3 can overlap with one of a plurality of light-emitting regions EA1, EA2, and EA3. The via patterns VP1, VP2, and VP3 can be island patterns. The cross-sections of the via patterns VP1, VP2, and VP3 in a planar view can be circular or polygons such as triangles and squares.

[0107] When cut along the thickness direction DR3, the via patterns VP1, VP2, and VP3 can have a forward tapered shape. The via patterns VP1, VP2, and VP3 can include side surfaces that slope towards the substrate SUB. The angle θ formed by the lower surface and side surfaces of the via patterns VP1, VP2, and VP3 can be less than approximately 90°.

[0108] The through-hole patterns VP1, VP2, and VP3 may comprise organic materials. In one or more embodiments, the through-hole patterns VP1, VP2, and VP3 may comprise polyimide resin, acrylic resin, epoxy resin, phenolic resin, polyamide resin, etc. In one or more embodiments, the through-hole patterns VP1, VP2, and VP3 may be formed by optical patterning.

[0109] Simultaneously, the inorganic patterns IP1, IP2, and IP3, described later, and the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3, and the common electrodes CE1, CE2, and CE3, can be formed sequentially for each color. After the material of the first light-emitting layer EL1, the first common electrode CE1, and the first inorganic pattern IP1 of the first color is deposited or coated on the entire surface, the first light-emitting layer EL1, the first common electrode CE1, and the first inorganic pattern IP1 are patterned so that they remain only in the first light-emitting region EA1 and its surrounding area. Then, the same process can be repeated for the second light-emitting layer EL2, the second common electrode CE2, and the second inorganic pattern IP2 of the second color, thereby forming the second light-emitting layer EL2, the second common electrode CE2, and the second inorganic pattern IP2. A wet etching process or a cleaning process can be performed during the patterning process of the second color. When the via patterns VP1, VP2, and VP3, or the via layers with organic material formed on their entire surface, are exposed to the solution of the wet etching process or the cleaning process, the via layers or the via patterns VP1, VP2, and VP3 of the organic layers can absorb moisture. Because the first light-emitting layer EL1 comprises organic materials, it may be difficult to dry the moisture in the via layers or via patterns VP1, VP2, and VP3 during the patterning of the second color using high-temperature baking. Residual moisture may reduce the reliability of the display device 10 when it is driven.

[0110] Apart from Figure 5 In addition, refer to Figure 6 The passivation layer PSV can cover the via patterns VP1, VP2, and VP3, as well as the first passivation layer PAS1. The passivation layer PSV may include contact holes through which pixel electrodes AE1, AE2, and AE3 pass. The contact holes of the passivation layer PSV can be connected to the contact holes of the first passivation layer PAS1.

[0111] The upper and side surfaces of the through-hole patterns VP1, VP2 and VP3 are covered by a passivation layer PSV, and the lower surfaces of the through-hole patterns VP1, VP2 and VP3 are covered by a first passivation layer PAS1, thereby reducing or preventing moisture penetration into the through-hole patterns VP1, VP2 and VP3.

[0112] The passivation layer PSV may include a first portion located at a first height from the substrate SUB, a second portion located at a second height from the substrate SUB, and a third portion located at a third height from the substrate SUB. The third height may be greater than the first and second heights, and the second height may be greater than the first height. The first, second, and third portions of the passivation layer PSV may be sequentially located in the longitudinal direction of the substrate SUB. In other words, the second portion of the passivation layer PSV may be located between the first and third portions in the longitudinal direction of the substrate SUB. The height of the passivation layer PSV refers to the vertical distance between the upper surface of the substrate SUB and the lower surface of the corresponding portion of the passivation layer PSV.

[0113] The passivation layer PSV can be retained without being removed by wet etching and cleaning processes. The passivation layer PSV may comprise inorganic materials. In one or more embodiments, the passivation layer PSV may comprise silicon nitride, silicon oxide nitride, silicon oxide, titanium oxide, aluminum oxide, or combinations thereof.

[0114] The light-emitting element layer (EML) can be located on the thin-film transistor layer (TFTL). The EML may include light-emitting elements (ED), pixel limiting layers (PDL), and dam structures (BNS). The light-emitting elements (ED) may include pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

[0115] refer to Figure 5 and Figure 6 The display device 10 may include a plurality of light-emitting regions EA1, EA2, and EA3 located in the display area DA, and a non-light-emitting region NEA located between the light-emitting regions EA1, EA2, and EA3. The light-emitting regions EA1, EA2, and EA3 may be defined as the areas where pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3 overlap each other in the thickness direction DR3 of the substrate SUB. The light-emitting regions EA1, EA2, and EA3 may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3, which are spaced apart from each other and emit light of the same or different colors. In one or more embodiments, the first light-emitting region EA1 may emit light of a first color, the second light-emitting region EA2 may emit light of a second color, and the third light-emitting region EA3 may emit light of a third color.

[0116] The display device 10 may include a plurality of light-emitting elements ED1, ED2 and ED3 located in different light-emitting regions EA1, EA2 and EA3. The light-emitting elements ED1, ED2 and ED3 may include a first light-emitting element ED1 located in the first light-emitting region EA1, a second light-emitting element ED2 located in the second light-emitting region EA2 and a third light-emitting element ED3 located in the third light-emitting region EA3.

[0117] The light-emitting elements ED1, ED2, and ED3 may each include pixel electrodes AE1, AE2, and AE3, light-emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3. Located in different light-emitting regions EA1, EA2, and EA3, the light-emitting elements ED1, ED2, and ED3 may emit different colors of light depending on the materials of the light-emitting layers EL1, EL2, and EL3. For example, the first light-emitting element ED1 located in the first light-emitting region EA1 may emit red light with a peak wavelength in the range of approximately 610 nm to approximately 650 nm; the second light-emitting element ED2 located in the second light-emitting region EA2 may emit green light with a peak wavelength in the range of approximately 510 nm to approximately 550 nm; and the third light-emitting element ED3 located in the third light-emitting region EA3 may emit blue light with a peak wavelength in the range of approximately 440 nm to approximately 480 nm. The first emitting region EA1, the second emitting region EA2, and the third emitting region EA3 constituting a pixel may include light-emitting elements ED1, ED2, and ED3 for emitting light of different colors to represent a white grayscale level. Optionally, since the emitting layers EL1, EL2, and EL3 may include two or more materials for emitting different colors of light, a single emitting layer may emit mixed light. For example, the emitting layers EL1, EL2, and EL3 may simultaneously include materials for emitting red light and materials for emitting green light to emit yellow light, or may include all of the materials for emitting red light, materials for emitting green light, and materials for emitting blue light to emit white light.

[0118] Pixel electrodes AE1, AE2, and AE3 may be located on the passivation layer PSV. Pixel electrodes AE1, AE2, and AE3 may be located in multiple light-emitting regions EA1, EA2, and EA3, and may overlap with multiple via patterns VP1, VP2, and VP3, respectively. Pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 located in a first light-emitting region EA1, a second pixel electrode AE2 located in a second light-emitting region EA2, and a third pixel electrode AE3 located in a third light-emitting region EA3. The first pixel electrode AE1 may overlap with a first via pattern VP1, the second pixel electrode AE2 may overlap with a second via pattern VP2, and the third pixel electrode AE3 may overlap with a third via pattern VP3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart from each other on the passivation layer PSV. A portion of pixel electrodes AE1, AE2, and AE3 may overlap with via patterns VP1, VP2, and VP3, while another portion of pixel electrodes AE1, AE2, and AE3 may not overlap with via patterns VP1, VP2, and VP3.

[0119] Pixel electrodes AE1, AE2, and AE3 can be electrically connected to the drain electrode DE of the thin-film transistor (TFT) via the first connection electrode CNE1. The edges of the spaced-apart pixel electrodes AE1, AE2, and AE3 can be covered by the pixel defining layer PDL, so that the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 can be insulated from each other.

[0120] Pixel electrodes AE1, AE2, and AE3 may comprise transparent electrode materials and / or conductive metal materials, and may have a single-layer or multi-layer structure. The metal material may be one or more of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti), and titanium nitride (TiN). The transparent electrode material may be one or more of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). In one or more embodiments, pixel electrodes AE1, AE2, and AE3 may have a multi-layer structure comprising a metal material layer and a transparent electrode material layer.

[0121] The light-emitting layers EL1, EL2, and EL3 can be located on the pixel electrodes AE1, AE2, and AE3. The light-emitting layers EL1, EL2, and EL3 can be organic light-emitting layers made of organic materials and can be formed on the pixel electrodes AE1, AE2, and AE3 by a deposition process. The light-emitting layers EL1, EL2, and EL3 can have a multilayer structure, and each of the hole injection material, hole transport material, light-emitting material, electron transport material, and electron injection material can constitute one layer. When the thin-film transistor (TFT) applies a voltage (e.g., a predetermined voltage) to the pixel electrodes AE1, AE2, and AE3 of the light-emitting elements ED1, ED2, and ED3, and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons can be injected and transported and can combine with each other in the light-emitting layers EL1, EL2, and EL3 to emit light.

[0122] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, respectively located in different light-emitting regions EA1, EA2, and EA3. The first light-emitting layer EL1 may be located on a first pixel electrode AE1 in the first light-emitting region EA1, the second light-emitting layer EL2 may be located on a second pixel electrode AE2 in the second light-emitting region EA2, and the third light-emitting layer EL3 may be located on a third pixel electrode AE3 in the third light-emitting region EA3. The first light-emitting layer EL1 may overlap with a first via pattern VP1, the second light-emitting layer EL2 may overlap with a second via pattern VP2, and the third light-emitting layer EL3 may overlap with a third via pattern VP3. The multiple light-emitting layers EL1, EL2, and EL3 may each emit light of different colors, or one of the light-emitting layers EL1, EL2, and EL3 may emit mixed light. In one or more embodiments, the first light-emitting layer EL1 may emit red light, the second light-emitting layer EL2 may emit green light, and the third light-emitting layer EL3 may emit blue light.

[0123] The light-emitting layers EL1, EL2, and EL3 may be located on the upper surface of the pixel defining layer PDL. In one or more embodiments, the side surfaces of the residual pattern RP may be more recessed than the side surfaces of the pixel defining layer PDL, and a portion of the light-emitting layers EL1, EL2, and EL3 may be located in the space between the pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL. In one or more embodiments, the light-emitting layers EL1, EL2, and EL3 may contact the pixel defining layer PDL, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3.

[0124] Common electrodes CE1, CE2, and CE3 can be located on the light-emitting layers EL1, EL2, and EL3. Common electrodes CE1, CE2, and CE3 can comprise transparent conductive materials, thereby emitting light generated from the light-emitting layers EL1, EL2, and EL3. Common electrodes CE1, CE2, and CE3 can receive a common voltage or a low-potential voltage. When pixel electrodes AE1, AE2, and AE3 receive a voltage corresponding to the data voltage while common electrodes CE1, CE2, and CE3 receive a low-potential voltage, a potential difference can be formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3, thereby allowing the light-emitting layers EL1, EL2, and EL3 to emit light.

[0125] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3, respectively located in different light-emitting regions EA1, EA2, and EA3. The first common electrode CE1 may be located on the first light-emitting layer EL1 in the first light-emitting region EA1, the second common electrode CE2 may be located on the second light-emitting layer EL2 in the second light-emitting region EA2, and the third common electrode CE3 may be located on the third light-emitting layer EL3 in the third light-emitting region EA3. The first common electrode CE1 may overlap with the first via pattern VP1, the second common electrode CE2 may overlap with the second via pattern VP2, and the third common electrode CE3 may overlap with the third via pattern VP3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be spaced apart from each other.

[0126] In one or more embodiments, a capping layer may be selectively located on the common electrodes CE1, CE2, and CE3. The capping layer may comprise organic or inorganic insulating materials to cover the patterns located on the light-emitting elements ED1, ED2, and ED3. The capping layer may reduce or prevent damage to the light-emitting elements ED1, ED2, and ED3 due to external air. In one or more embodiments, the capping layer may comprise organic materials such as a-NPD, NPB, TPD, m-MTDATA, Alq3, LiF, and / or CuPc, or inorganic materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon nitride.

[0127] The capping layer may include a first capping layer, a second capping layer, and a third capping layer located in different light-emitting regions EA1, EA2, and EA3, respectively. The first to third capping layers may be spaced apart from each other.

[0128] The pixel defining layer (PDL) can be located on the passivation layer (PSV) to expose the upper surfaces of the pixel electrodes AE1, AE2, and AE3. The pixel defining layer (PDL) can have sides for defining the light-emitting regions EA1, EA2, and EA3.

[0129] The pixel-defining layer (PDL) may include an inorganic insulating material. The PDL may include, but is not limited to, at least one of the following: a silicon nitride layer, a silicon oxide nitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, a tantalum oxide layer, a hafnium oxide layer, a zinc oxide layer, and an amorphous silicon layer.

[0130] According to one or more embodiments, the pixel defining layer PDL is located on the edges of pixel electrodes AE1, AE2, and AE3, and may be spaced apart from the upper surfaces of pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may not directly contact the upper surfaces of pixel electrodes AE1, AE2, and AE3, while partially overlapping the upper surfaces of pixel electrodes AE1, AE2, and AE3 in the thickness direction DR3 of the substrate SUB, and the residual pattern RP may be located between the pixel defining layer PDL and the pixel electrodes AE1, AE2, and AE3. However, the pixel defining layer PDL may directly contact the sides of pixel electrodes AE1, AE2, and AE3. The sides of the pixel defining layer PDL may (e.g., in a plan view) protrude towards the light-emitting regions EA1, EA2, and EA3 to a greater extent than the sides of the second embankment BN2.

[0131] The residual pattern RP can be located on the edge of each of the pixel electrodes AE1, AE2, and AE3. Due to the residual pattern RP, the pixel defining layer PDL does not need to directly contact the upper surfaces of the pixel electrodes AE1, AE2, and AE3. In the manufacturing process of the display device 10, a portion of the sacrificial layer located on the pixel electrodes AE1, AE2, and AE3 can be removed, thereby forming the residual pattern RP. The residual pattern RP can comprise a metal or oxide semiconductor material. In the figures, the sides of the residual pattern RP pointing towards the light-emitting regions EA1, EA2, and EA3 are only shown as being more recessed than the sides of the pixel defining layer PDL, but this disclosure is not limited thereto. The sides of the residual pattern RP can protrude towards the light-emitting regions EA1, EA2, and EA3 to a greater extent than the sides of the pixel defining layer PDL, or they can be aligned with the sides of the pixel defining layer PDL.

[0132] The display device 10 may include a dam structure BNS located on the pixel defining layer PDL. The dam structure BNS may have a structure comprising dams BN1 and BN2 stacked sequentially, each made of a different material, and may include or define a plurality of openings overlapping with light-emitting regions EA1, EA2, and EA3. The dam structure BNS may overlap with a non-light-emitting region NEA located between the light-emitting regions EA1, EA2, and EA3, and may overlap with light-blocking regions of color filters CF1, CF2, and CF3, which will be described later. The dam structure BNS may be located between via patterns VP1, VP2, and VP3, and may overlap with the gaps between the via patterns VP1, VP2, and VP3.

[0133] The first dam BN1 may be located on the pixel-defining layer PDL. In the direction opposite to the direction pointing to the light-emitting regions EA1, EA2, and EA3, the side surface of the first dam BN1 may be more concave than the side surface of the pixel-defining layer PDL. In the direction opposite to the direction pointing to the light-emitting regions EA1, EA2, and EA3, the side surface of the first dam BN1 may be more concave than the side surface of the second dam BN2, which will be described later.

[0134] According to one or more embodiments, the first dam BN1 may include a metallic material. In one or more embodiments, the first dam BN1 may include aluminum (Al), an oxide of aluminum (Al), or an alloy of aluminum (Al).

[0135] The common electrodes CE1, CE2, and CE3 can directly contact the side surface of the first dam BN1. The ends of the common electrodes CE1, CE2, and CE3 can contact the side surface of the first dam BN1. The common electrodes CE1, CE2, and CE3 of the spaced light-emitting elements ED1, ED2, and ED3 can directly contact the first dam BN1, and the first dam BN1 can include a conductive material so that the common electrodes CE1, CE2, and CE3 can be electrically connected to each other through the first dam BN1.

[0136] According to one or more embodiments, the light-emitting layers EL1, EL2, and EL3 can directly contact the side surface of the first dam BN1. The area where the common electrodes CE1, CE2, and CE3 contact the side surface of the first dam BN1 can be larger than the area where the light-emitting layers EL1, EL2, and EL3 contact the side surface of the first dam BN1. The common electrodes CE1, CE2, and CE3 can be positioned on the side surface of the first dam BN1 to reach an area larger than the light-emitting layers EL1, EL2, and EL3, or to a higher position on the side surface of the first dam BN1. Because the common electrodes CE1, CE2, and CE3 of the different light-emitting elements ED1, ED2, and ED3 are electrically connected to each other through the first dam BN1, it may be suitable for the common electrodes CE1, CE2, and CE3 to contact the first dam BN1 in a larger area.

[0137] The first dam BN1 may have an upper surface at a position higher than the common electrodes CE1, CE2, and CE3. The height from the substrate SUB to the upper surface of the first dam BN1 may be greater than the height from the substrate SUB to the common electrodes CE1, CE2, and CE3.

[0138] The second embankment BN2 may be located on the first embankment BN1. The second embankment BN2 may include / define openings that overlap with the light-emitting regions EA1, EA2, and EA3, respectively, and each of the openings may include a side surface. The second embankment BN2 may include a tip or ridge that (e.g., in a plan view) protrudes beyond the area extended by the first embankment BN1. The side surfaces of the second embankment BN2 may protrude toward the light-emitting regions EA1, EA2, and EA3 to a greater extent than the side surfaces of the first embankment BN1.

[0139] Since the side of the second dam BN2 has (for example, in a plan view) a shape that protrudes further toward the light-emitting areas EA1, EA2 and EA3 than the side of the first dam BN1, the undercut structure of the first dam BN1 can be formed below the tip TIP of the second dam BN2.

[0140] In the display device 10 according to one or more embodiments, the dam structure BNS may include (e.g., in a plan view) pointed tips protruding toward the light-emitting regions EA1, EA2, and EA3, thereby forming spaced-apart light-emitting layers EL1, EL2, and EL3 and common electrodes CE1, CE2, and CE3 by deposition and etching processes, as opposed to masking processes. Furthermore, even by deposition processes, different layers can be formed individually in the different light-emitting regions EA1, EA2, and EA3. For example, although the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3 are formed by deposition processes without using a mask, the deposited material can be disconnected from the dam structure BNS inserted therebetween by the pointed tips of the second dam BN2, without being connected between the light-emitting regions EA1, EA2, and EA3. After the material for forming the respective layers is formed on the entire surface of the display device 10, different layers can be formed individually in the different light-emitting regions EA1, EA2, and EA3 by etching to remove layers formed in unwanted areas. In the display device 10, different light-emitting elements ED1, ED2 and ED3 can be formed for the light-emitting areas EA1, EA2 and EA3 respectively by deposition and etching processes without using mask processes. This can eliminate unnecessary components in the display device 10 and reduce or minimize the size of the non-display area NDA.

[0141] The second seam BN2 may comprise a metallic material different from that of the first seam BN1. The metallic material of the second seam BN2 is removed along with the metallic material of the first seam BN1 by dry etching; however, for wet etching, the metallic material of the second seam BN2 may be any material having an etching rate slower (e.g., significantly slower) than that of the first seam BN1, or may not be etched at all. In one or more embodiments, the first seam BN1 may comprise aluminum (Al), aluminum (Al) oxides, or aluminum (Al) alloys, and the second seam BN2 may comprise titanium (Ti), titanium (Ti) oxides, or titanium (Ti) alloys.

[0142] The tip TIP of the second dam BN2 can overlap with the common electrodes CE1, CE2, and CE3, the light-emitting layers EL1, EL2, and EL3, and the pixel defining layer PDL in a direction DR3 perpendicular to the substrate SUB. The common electrodes CE1, CE2, and CE3 can be formed below the lower surface of the tip TIP of the second dam BN2. One end and the other end of each of the common electrodes CE1, CE2, and CE3 can overlap with the second dam BN2 in the thickness direction DR3 of the substrate.

[0143] Figure 7 This is a cross-sectional view showing a portion of a display device according to one or more embodiments, and Figure 8 It is shown Figure 7 An enlarged sectional view of region A1'.

[0144] refer to Figure 7 The thin-film encapsulation layer TFEL can be located on the light-emitting elements ED1, ED2, and ED3 and the dam structure BNS', and can cover multiple light-emitting elements ED1, ED2, and ED3 and the dam structure BNS'. The thin-film encapsulation layer TFEL may include at least one inorganic layer to reduce or prevent oxygen or moisture from penetrating into the light-emitting element layer EML. The thin-film encapsulation layer TFEL may also include at least one organic layer to protect the light-emitting element layer EML from particles such as dust.

[0145] In one or more embodiments, the thin-film encapsulation layer TFEL may include a lower inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and an upper inorganic encapsulation layer TFE3 stacked sequentially.

[0146] Each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating material may be any one of silicon oxide, silicon nitride, and silicon nitride oxide, and may be, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide.

[0147] The organic encapsulation layer TFE2 may include polymer-based materials. Polymer-based materials may include acrylic resins, epoxy-based resins, polyimides, and polyethylene. For example, the organic encapsulation layer TFE2 may include acrylic resins such as polymethyl methacrylate, polyacrylic acid, etc. The organic encapsulation layer TFE2 can be formed by curing monomers or coating polymers.

[0148] The lower inorganic encapsulation layer TFE1 can be located on the light-emitting elements ED1, ED2, and ED3 and the embankment structure BNS'. The lower inorganic encapsulation layer TFE1 may include a first inorganic pattern IP1, a second inorganic pattern IP2, and a third inorganic pattern IP3 corresponding to different light-emitting regions EA1, EA2, and EA3, respectively. Each of the first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3 may include an inorganic insulating material to cover the light-emitting elements ED1, ED2, and ED3. The first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3 can reduce or prevent damage to the light-emitting elements ED1, ED2, and ED3 due to external air.

[0149] The lower inorganic encapsulation layers TFE1 (IP1, IP2, and IP3) can be formed using chemical vapor deposition (CVD), and therefore can be formed along the step difference of the deposited layers. For example, due to the tip TIP of the dam structure BNS', the first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3 can be formed even below the undercut. The lower inorganic encapsulation layers IP1, IP2, and IP3 can be positioned along (e.g., adjacent to) the upper surface, side surface, and lower surface of the second dam BN2', the side surface of the first dam BN1', and the upper surface of the common electrodes CE1, CE2, and CE3, respectively. For example, the lower inorganic encapsulation layers IP1, IP2, and IP3 can contact the lower surface of the second dam BN2' to reduce or prevent moisture penetration from external air.

[0150] The first inorganic pattern IP1 does not overlap with the second light-emitting element ED2 and the third light-emitting element ED3, and may be located only on the first light-emitting element ED1 and the embankment structure BNS' near the first light-emitting element ED1. The second inorganic pattern IP2 does not overlap with the first light-emitting element ED1 and the third light-emitting element ED3, and may be located only on the second light-emitting element ED2 and the embankment structure BNS' near the second light-emitting element ED2. The third inorganic pattern IP3 does not overlap with the first light-emitting element ED1 and the second light-emitting element ED2, and may be located only on the third light-emitting element ED3 and the embankment structure BNS' near the third light-emitting element ED3.

[0151] The first inorganic pattern IP1 can be formed after the first common electrode CE1 is formed, the second inorganic pattern IP2 can be formed after the second common electrode CE2 is formed, and the third inorganic pattern IP3 can be formed after the third common electrode CE3 is formed. The first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3 can be spaced apart from each other on the embankment structure BNS'.

[0152] The lower inorganic encapsulation layers IP1, IP2, and IP3 are located on the upper surfaces of the light-emitting elements ED1, ED2, and ED3, and on the lower surface of the second dam BN2' near the light-emitting elements ED1, ED2, and ED3, respectively, and can be spaced apart from the upper surface of the second dam BN2'. That is, the lower inorganic encapsulation layers IP1, IP2, and IP3 can have an undercut structure on the second dam BN2'. The space between the lower inorganic encapsulation layers IP1, IP2, and IP3 and the upper surface of the second dam BN2' can be a space for removing material from the light-emitting layers EL1, EL2, and EL3 deposited across the entire surface, as well as the common electrodes CE1, CE2, and CE3.

[0153] The organic encapsulation layer TFE2 is located on the dam structure BN2' and the lower inorganic encapsulation layers IP1, IP2, and IP3. A portion of the organic encapsulation layer TFE2 may be located in the space between the lower inorganic encapsulation layers IP1, IP2, and IP3 and the upper surface of the second dam BN2'. In the region where the second dam BN2' overlaps with the lower inorganic encapsulation layers IP1, IP2, and IP3, the second dam BN2', the organic encapsulation layer TFE2, and the lower inorganic encapsulation layers IP1, IP2, and IP3 may be sequentially positioned. In the tip TIP region, the organic encapsulation layer TFE2 and the lower inorganic encapsulation layers IP1, IP2, and IP3 may be sequentially located on the second dam BN2', and the organic encapsulation layer TFE2 may again be located on the lower inorganic encapsulation layers IP1, IP2, and IP3. In other words, a portion of the organic encapsulation layer TFE2 may be located between the upper surface of the second dike BN2' and the lower inorganic encapsulation layers IP1, IP2 and IP3 on the tip TIP of the second dike BN2', and another portion of it may be located on the lower inorganic encapsulation layers IP1, IP2 and IP3.

[0154] In one or more embodiments, the entire upper surface of the second dike BN2' may contact the organic encapsulation layer TFE2. The first lower surfaces of the lower inorganic encapsulation layers IP1, IP2, and IP3 may be surfaces facing the upper surface of the second dike BN2', and the first lower surfaces of the lower inorganic encapsulation layers IP1, IP2, and IP3 may contact the organic encapsulation layer TFE2. The organic encapsulation layer TFE2 may contact the side surfaces of the second dike BN2'.

[0155] The upper inorganic encapsulation layer TFE3 can be located on the organic encapsulation layer TFE2. The upper inorganic encapsulation layer TFE3 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon nitride.

[0156] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 located in the light-emitting regions EA1, EA2, and EA3. Each of the plurality of color filters CF1, CF2, and CF3 may include a filter pattern region and a light-blocking region. The filter pattern region may be formed to overlap with the openings of the light-emitting regions EA1, EA2, and EA3 or the dam structure BNS', and may form an emission region through which light emitted from the light-emitting regions EA1, EA2, and EA3 is emitted. The light-blocking region is an area in which the plurality of color filters CF1, CF2, and CF3 are stacked such that light cannot pass through, and may overlap with the non-light-emitting region NEA.

[0157] Color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3, respectively, corresponding to different emitting regions EA1, EA2, and EA3. Color filters CF1, CF2, and CF3 may include colorants, such as dyes or pigments for absorbing light in a wavelength band other than their corresponding wavelength bands, and color filters CF1, CF2, and CF3 may correspond to the color of light emitted from emitting regions EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter overlapping the first emitting region EA1, for transmitting only red first light. The second color filter CF2 may be a green color filter overlapping the second emitting region EA2, for transmitting only green second light. The third color filter CF3 may be a blue color filter overlapping the third emitting region EA3, for transmitting only blue third light.

[0158] When color filters CF1, CF2, and CF3 overlap, the display device 10 can reduce the intensity of reflected light caused by external light. Furthermore, the display device 10 can control the color perception of reflected light caused by external light by adjusting the layout, shape, and area of ​​the color filters CF1, CF2, and CF3 on a plan view.

[0159] The outer coating OC can be located on color filters CF1, CF2, and CF3 to flatten the upper ends of color filters CF1, CF2, and CF3. The outer coating OC can be a colorless, transparent layer without a visible light band. For example, the outer coating OC can comprise a colorless, transparent organic material such as acrylic resin.

[0160] Figure 7 and Figure 8 The levee structure BNS' can have a higher degree of... Figure 5 and Figure 6The dam structure BNS has a narrow width. When the via patterns VP1, VP2, and VP3 are removed from a portion of the non-light-emitting region NEA, the dam structure, including the metal, may become close to the thin-film transistor TFTs or metal lines of the thin-film transistor layer TFTL, and the capacitance of the capacitors may change. To reduce or prevent this possibility, the width of the dam structure can be narrowed.

[0161] The dam structure BNS' may include / define an opening in the non-light-emitting region NEA. The opening of the dam structure BNS' may overlap with the thin-film transistor TFT. The second dam BN2' may include not only the pointed tip in the region pointing towards the light-emitting regions EA1, EA2, and EA3, but also the pointed tip in the region pointing towards the center of the non-light-emitting region NEA. The second dam BN2' may include (e.g., in a plan view) a side that protrudes further towards the center of the non-light-emitting region NEA than the first dam BN1'.

[0162] The pixel defining layer (PDL) may be exposed in the opening of the dam structure BNS'. In one or more embodiments, the pixel defining layer (PDL) exposed in the opening may be covered by an organic encapsulation layer (TFE2). In one or more embodiments, the pixel defining layer (PDL) exposed in the opening may be covered by the same material as any one of the first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3 of the lower inorganic encapsulation layer TFE1.

[0163] In addition to the dike structure BNS' Figure 7 and Figure 8 Components and Figure 5 and Figure 6 The components are the same, and therefore their repeated descriptions will be omitted.

[0164] Figure 9 This is an enlarged cross-sectional view showing a portion of a display device according to one or more embodiments.

[0165] Figure 9 Pixel confinement layer PDL' and Figure 8 The difference between the pixel-defining layer (PDL) and the previous one is that the pixel-defining layer (PDL') is removed from a portion of the non-emitting region (NEA). During patterning of the light-emitting elements ED1, ED2, and ED3 for each color, as well as the lower inorganic encapsulation layers IP1, IP2, and IP3, the pixel-defining layer (PDL') exposed by the etchant can be removed, and the passivation layer (PSV) can be exposed. The pixel-defining layer (PDL') can overlap with the second embankment (BN2'), and an opening can be formed in the non-emitting region (NEA).

[0166] At least a portion of the opening in the dam structure BNS' may not overlap with the pixel defining layer PDL', and the passivation layer PSV may be exposed. In one or more embodiments, the passivation layer PSV exposed in the opening may be covered by an organic encapsulation layer TFE2. In one or more embodiments, the passivation layer PSV exposed in the opening may be covered by the same material as any one of the first inorganic pattern IP1, the second inorganic pattern IP2, and the third inorganic pattern IP3 of the lower inorganic encapsulation layer TFE1.

[0167] Figure 10 This is an enlarged cross-sectional view showing a portion of a display device according to one or more embodiments, and Figure 11 It is shown Figure 10 An enlarged sectional view of region A2.

[0168] Figure 10 and Figure 11 "Pixel Confinement Layer (PDL)" and Figure 8 The difference between the pixel-delimited layer (PDL) and the non-light-emitting area (NEA) is that a portion of the thickness is removed. The pixel-delimited layer (PDL) is different from... Figure 9 The pixel-defined layer PDL' is the same as that the pixel-defined layer PDL exposed by the etchant is removed during the patterning of the light-emitting elements ED1, ED2 and ED3 of each color and the lower inorganic encapsulation layers IP1, IP2 and IP3, but in contrast to the total thickness, only a portion of the pixel-defined layer PDL' in the area exposed by the etchant is removed.

[0169] refer to Figure 11 The thickness of the pixel-defined layer (PDL) can vary based on the intermediate side PDL_S1. The thickness T1 of the pixel-defined layer (PDL) adjacent to the embankment structure BNS' can be greater than the thickness T2 of the pixel-defined layer (PDL) adjacent to the center of the non-light-emitting region NEA or the center of the opening of the embankment structure BNS'.

[0170] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that the present disclosure may be implemented in other specific forms without departing from the spirit and essential characteristics of the technology. Therefore, the above embodiments are to be considered illustrative rather than restrictive in all respects.

[0171] It should be understood that the embodiments described herein are to be considered in a descriptive sense and not for limiting purposes. The description of aspects within each embodiment should generally be taken into account for other similar aspects in other embodiments. While one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made herein without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A display device, characterized by comprising: comprising: a first via pattern and a second via pattern over a substrate, the first via pattern and the second via pattern being spaced apart; a passivation layer over the first via pattern and the second via pattern; a first light emitting element over the passivation layer and overlapping the first via pattern; a second light emitting element over the passivation layer and overlapping the second via pattern; a first bank over the substrate between the first via pattern and the second via pattern; and a second bank over the first bank and protruding beyond a side surface of the first bank. The passivation layer covers an upper surface and a side surface of the first via pattern and an upper surface and a side surface of the second via pattern.

2. The display device according to claim 1, wherein The passivation layer defines a contact hole through which a first pixel electrode of the first light emitting element passes.

3. The display device according to claim 1, wherein The passivation layer includes a first portion at a first height from the substrate, a second portion at a second height from the substrate, and a third portion at a third height from the substrate, the third height being greater than the first height and the second height, and the second height being greater than the first height.

4. The display device according to claim 1, wherein An angle between a lower surface and a side surface of the first via pattern is less than 90°.

5. The display device according to claim 1, wherein Further comprising:

6. The display device according to claim 1, wherein a pixel defining layer between the passivation layer and the first bank and including a side surface protruding beyond the side surface of the first bank; and a residual pattern under the pixel defining layer at an edge of a first pixel electrode of the first light emitting element. The first light emitting element includes a first pixel electrode over the passivation layer, a first light emitting layer over the first pixel electrode, and a first common electrode over the first light emitting layer, and wherein the second light emitting element includes a second pixel electrode over the passivation layer, a second light emitting layer over the second pixel electrode, and a second common electrode over the second light emitting layer and spaced apart from the first common electrode, and 7. The display device according to claim 1, wherein wherein the first common electrode and the second common electrode contact the first bank. Further comprising: a first inorganic pattern over the first light emitting element; and 8. The display device according to claim 1, wherein a second inorganic pattern over the second light emitting element and spaced apart from the first inorganic pattern, and wherein a portion of the first inorganic pattern is under a lower surface of the second bank. comprising: a first via pattern and a second via pattern over a substrate, the first via pattern and the second via pattern being spaced apart; a first light emitting element over the first via pattern; 9. A display device, characterized by comprising: a second light emitting element over the second via pattern; a first bank over the substrate defining a first opening overlapping the first light emitting element and defining a second opening overlapping a region between the first light emitting element and the second light emitting element; and a second bank over the first bank and protruding beyond a side surface of the first bank. The second bank defines a third opening overlapping the first opening of the first bank and a fourth opening overlapping the second opening of the first bank, ​ ​ ​ 10. The display device according to claim 9, wherein ​ wherein a first side of the second bank directed towards the third opening protrudes beyond a first side of the first bank directed towards the first opening, and wherein a second side of the second bank directed towards the fourth opening protrudes beyond a second side of the first bank directed towards the second opening.

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