Multistage optical eye detection circuit with carrier control

Abstract

The utility model discloses a multistage optical eye detection circuit with carrier control, comprising a chip U1 used for generating carrier signals with fixed frequency and duty ratio; the pre-stage carrier amplification circuit module is connected with the chip U1 and is used for amplifying a driving carrier signal; the multi-stage infrared emission circuit module is connected with the pre-stage carrier amplification circuit module and is used for simultaneously transmitting the amplified carrier signals in the form of electromagnetic waves through multi-path cascaded infrared emission tubes; and the multi-stage infrared receiving circuit is connected with the chip U1 and is used for receiving infrared signals. According to the utility model, the purpose of detecting the position and the motion state of an object is achieved through the sending and receiving mechanisms of the multi-stage infrared signals, and meanwhile, the circuit is simple to realize and high in stability.

Description

Technical Field

[0001] This disclosure relates to the field of photodetector technology, and in particular to a multi-stage photodetector circuit with carrier control. Background Technology

[0002] Traditional circuits that detect the state of objects by transmitting and receiving infrared signals have advantages such as moderate transmission distance, fast transmission speed and simple circuit implementation. However, when used in environments with electromagnetic interference, the stability of signal transmission will decrease significantly or even result in failure to detect. Furthermore, traditional detection circuits can only detect the presence of objects, but cannot effectively detect their position and motion state, which will seriously affect the expansion of system functions and user experience. Utility Model Content

[0003] This disclosure provides a multi-stage photodetector circuit with carrier control to solve one of the technical problems recognized by the inventors.

[0004] This disclosure provides a multi-level photodetector circuit with carrier control, including a chip U1, which is used to generate a carrier signal with a fixed frequency and duty cycle;

[0005] The pre-amplifier circuit module connected to the chip U1 is used to amplify the drive carrier signal;

[0006] The multi-stage infrared emitting circuit module connected to the pre-stage carrier amplifier circuit module is used to simultaneously propagate the amplified carrier signal in the form of electromagnetic waves through multiple cascaded infrared emitting tubes.

[0007] The multi-level infrared receiving circuit module connected to the chip U1 is used to receive infrared signals.

[0008] Preferably, the chip U1 is an AT32F421C8T7 chip.

[0009] Preferably, the pre-amplifier circuit module includes resistors R6 and R8, transistors Q3 and Q4. One end of resistor R6 is connected to pin 21 of chip U1, and the other end of resistor R6 is connected to the collector of transistor Q3 and the base of transistor Q4. The emitter of transistor Q3 is connected to one end of resistor R8, and the other end of resistor R8 is connected to the emitter of transistor Q4. The base of transistor Q3 is connected to the emitter of transistor Q4, and the collector of transistor Q4 is connected to the multi-stage infrared emitting circuit module.

[0010] Preferably, the multi-stage infrared emitting circuit module includes resistors R7 and R9, and diodes D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, and D14. Resistor R7, diodes D3, D4, D5, D6, D7, and D8 are connected in series, and resistor R9, diodes D9, D10, D11, D12, D13, and D14 are connected in series. Resistor R7 is connected to resistor R9, and diodes D8 and D14 are connected and connected to the collector of transistor Q4.

[0011] Preferably, the multi-stage infrared receiving circuit module includes resistors R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, and diodes D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, and D25. Resistor R10 and diode D15 are connected in series to form a first receiving branch; resistor R11 and diode D16 are connected in series to form a second receiving branch; resistor R12 and diode D17 are connected in series to form a third receiving branch; resistor R13 and diode D18 are connected in series to form a fourth receiving branch; resistor R14 and diode D19 are connected in series to form a fifth receiving branch; and resistor R15 and diode D20 are connected in series to form a sixth receiving branch. The first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh receiving branches are connected in parallel. The first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh receiving branches are respectively connected to pins 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20 of chip U1.

[0012] The main beneficial effects of this disclosure are: this utility model achieves the purpose of detecting the position and motion state of an object through a multi-level infrared signal transmission and reception mechanism, while the circuit implementation is simple and stable.

[0013] It should be understood that both the foregoing general description and the following detailed description are for illustrative purposes and do not necessarily limit the scope of this disclosure. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate the subject matter of this disclosure. Furthermore, the specification and drawings serve to explain the principles of this disclosure. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a multi-stage photodetector circuit according to an embodiment of the present disclosure;

[0016] Figure 2 This is a circuit diagram of chip U1 according to an embodiment of the present disclosure;

[0017] Figure 3 This is a circuit diagram of the pre-amplifier circuit module and the multi-stage infrared emitting circuit module according to an embodiment of the present disclosure;

[0018] Figure 4 This is a circuit diagram of a multi-level infrared receiving circuit module according to an embodiment of the present disclosure; Detailed Implementation

[0019] The technical solutions of this disclosure will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments.

[0020] Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this disclosure.

[0021] In the description of this disclosure, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure based on the specific circumstances.

[0023] Example

[0024] like Figure 1-4 As shown, this embodiment provides a multi-level photodetector circuit with carrier control, including a chip U1. The chip U1 is used to generate a carrier signal with a fixed frequency and duty cycle; the chip U1 is an AT32F421C8T7 chip. The carrier signal generated by the chip U1 and its pin 21 has a frequency of 38KHz, a duty cycle of 1 / 3, a high-level amplitude of +3.3V, and a low-level amplitude of 0V. This carrier signal is output via pin 21 of U1.

[0025] In this embodiment, the chip U1 is connected to a pre-stage carrier amplifier circuit module, which is used to amplify the driving carrier signal.

[0026] Specifically, the pre-amplifier carrier amplifier circuit module includes resistors R6 and R8, and transistors Q3 and Q4. One end of resistor R6 is connected to pin 21 of chip U1, and the other end of resistor R6 is connected to the collector of transistor Q3 and the base of transistor Q4. The emitter of transistor Q3 is connected to one end of resistor R8, and the other end of resistor R8 is connected to the emitter of transistor Q4. The base of transistor Q3 is connected to the emitter of transistor Q4, and the collector of transistor Q4 is connected to the multi-stage infrared emitting circuit module. In this embodiment, the pre-amplifier carrier signal is transmitted to transistors Q3 and Q4 via resistor R6. Resistor R8 is a current-limiting resistor, and the amplified current is determined by the resistance value of resistor R8. When the input voltage to resistor R6 is 0V, transistors Q3 and Q4 are not conducting, and the amplified current is 0mA. When the input voltage to resistor R6 is +3.3V, transistors Q3 and Q4 will conduct, and the amplified current will be 70mA. If the voltage of the preceding carrier amplifier module suddenly fluctuates, causing the current to increase, the current flowing through resistor R8 will also increase. This increases the base voltage of transistor Q3, which in turn lowers its Vce voltage. Consequently, the base voltage of transistor Q4 decreases, reducing the current flowing through resistor R8 and thus the amplified current, creating negative feedback until the circuit is balanced. Conversely, if the voltage of the preceding carrier amplifier module suddenly fluctuates, causing the current to decrease, the current flowing through resistor R8 will also decrease. This decrease in the base voltage of transistor Q3 will increase its Vce voltage, which in turn increases the base voltage of transistor Q4. This further increases the current flowing through resistor R8 and the amplified current, continuing until the circuit is balanced. When the preceding carrier amplifier module is in a balanced state, the amplified current will neither increase nor decrease; it will remain a constant value. The constant current value is equal to the base voltage of transistor Q3 divided by the resistance value of resistor R8, i.e., 0.7 / 10 = 70mA.

[0027] In this embodiment, the pre-stage carrier amplifier circuit module is connected to a multi-stage infrared emitting circuit module, which is used to simultaneously propagate the amplified carrier signal in the form of electromagnetic waves through multiple cascaded infrared emitting tubes.

[0028] Specifically, the multi-stage infrared emitting circuit module includes resistors R7 and R9, and diodes D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, and D14. Resistor R7, diodes D3, D4, D5, D6, D7, and D8 are connected in series, and resistor R9, diodes D9, D10, D11, D12, D13, and D14 are connected in series. Resistor R7 is connected to resistor R9, and diodes D8 and D14 are connected and connected to the collector of transistor Q4. In this embodiment, resistor R7 and diodes D3, D4, D5, D6, D7, and D8 form the first series branch, and resistor R9 and diodes D9, D10, D11, D12, D13, and D14 form the second series branch. The first and second series branches are then connected in parallel. The power supply voltage input to the two branches is +12V, and the current in each branch is 70mA / 2 = 35mA. Resistors R7 and R9 are used to limit the current in their respective branches, and finally, the emission current of each infrared emitting diode is 35mA.

[0029] In this embodiment, the chip U1 is connected to a multi-stage infrared receiving circuit module for receiving infrared signals. Specifically, the multi-stage infrared receiving circuit module includes resistors R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, and diodes D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, and D25. Resistor R10 and diode D15 are connected in series to form a first receiving branch; resistor R11 and diode D16 are connected in series to form a second receiving branch; resistor R12 and diode D17 are connected in series to form a third receiving branch; resistor R13 and diode D18 are connected in series to form a fourth receiving branch; resistor R14 and diode D19 are connected in series to form a fifth receiving branch; and resistor R15 and diode D20 are connected in series to form a sixth receiving branch. The first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh receiving branches are connected in parallel. The first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh receiving branches are respectively connected to pins 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20 of chip U1. In this embodiment, the power supply voltage input to the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh receiving branches is +3.3V. When any receiving support receives an infrared signal, the feed point voltage of the branch is 0V; when any receiving support does not receive an infrared signal, the feed point voltage of the branch is +3.3V. The position and motion state of the object are detected by the signal change states of different branches.

[0030] In this embodiment, chip U1 and its pins 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20 form a multi-level signal feedback circuit. When the feedback voltage of any pin of chip U1 is +3.3V, it is considered a high level; when the feedback voltage is 0V, it is considered a low level. Based on the feedback results, the level of each pin may be the same or different, and they do not interfere with each other. Chip U1 will eventually label the pins in ascending order, and calculate the motion state and position information of the object based on the signal changes of different labels.

[0031] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A multi-stage photodetector circuit with carrier control, characterized in that, include: Chip U1, which is used to generate a carrier signal with a fixed frequency and duty cycle; The pre-amplifier circuit module connected to the chip U1 is used to amplify the drive carrier signal; The multi-stage infrared emitting circuit module connected to the pre-stage carrier amplifier circuit module is used to simultaneously propagate the amplified carrier signal in the form of electromagnetic waves through multiple cascaded infrared emitting tubes. The multi-level infrared receiving circuit module connected to the chip U1 is used to receive infrared signals.

2. The multi-stage photodetector circuit with carrier control according to claim 1, characterized in that, The chip U1 is an AT32F421C8T7 chip.

3. The multi-stage photodetector circuit with carrier control according to claim 2, characterized in that, The pre-amplifier circuit module includes resistors R6 and R8, transistors Q3 and Q4. One end of resistor R6 is connected to pin 21 of chip U1, and the other end of resistor R6 is connected to the collector of transistor Q3 and the base of transistor Q4. The emitter of transistor Q3 is connected to one end of resistor R8, and the other end of resistor R8 is connected to the emitter of transistor Q4. The base of transistor Q3 is connected to the emitter of transistor Q4, and the collector of transistor Q4 is connected to the multi-stage infrared emitting circuit module.

4. The multi-stage photodetector circuit with carrier control according to claim 3, characterized in that, The multi-stage infrared emitting circuit module includes resistors R7 and R9, and diodes D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, and D14. Resistor R7, diodes D3, D4, D5, D6, D7, and D8 are connected in series, and resistor R9, diodes D9, D10, D11, D12, D13, and D14 are connected in series. Resistor R7 is connected to resistor R9, and diodes D8 and D14 are connected and connected to the collector of transistor Q4.

5. The multi-stage photodetector circuit with carrier control according to claim 1, characterized in that, The multi-stage infrared receiving circuit module includes resistors R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, and diodes D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, and D25. Resistor R10 and diode D15 are connected in series to form a first receiving branch; resistor R11 and diode D16 are connected in series to form a second receiving branch; resistor R12 and diode D17 are connected in series to form a third receiving branch; resistor R13 and diode D18 are connected in series to form a fourth receiving branch; resistor R14 and diode D19 are connected in series to form a fifth receiving branch; and resistor R15 and diode D20 are connected in series to form a sixth receiving branch. The resistor R16 and diode D21 are connected in series to form the seventh receiving branch; the resistor R17 and diode D22 are connected in series to form the eighth receiving branch; the resistor R18 and diode D23 are connected in series to form the ninth receiving branch; the resistor R19 and diode D24 are connected in series to form the tenth receiving branch; and the resistor R20 and diode D25 are connected in series to form the eleventh receiving branch. The first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh receiving branches are connected in parallel. The first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh receiving branches are respectively connected to pins 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20 of the chip U1.

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