Multi-interface charging test mainboard

Abstract

The utility model provides a multi-interface charging test mainboard, which is applied to the field of charging test, and comprises a memory slot, a plurality of charging ports and a plurality of charging ports, the CPU slot is connected with the plurality of memory slots; a PCH chip, wherein the PCH chip is connected with the CPU slot; a Super I / O chip, wherein the Super I / O chip is connected with the PCH chip; the charging test circuit comprises a plurality of test interfaces, the input end of the charging test circuit is connected with the output end of the Super I / O chip, and the output end of the charging test circuit is connected with the PCH chip; the first input end of the data transmission circuit is connected with the PCH chip, the second input end of the data transmission circuit is connected with the output end of the Super I / O chip, and the output end of the data transmission circuit is connected with each test interface. The utility model aims to achieve the purpose of testing a plurality of USB PD devices in parallel.

Description

Technical Field

[0001] This utility model relates to the field of charging test technology, and in particular to a multi-interface charging test motherboard. Background Technology

[0002] Currently, a variety of specialized testing equipment can be used to perform performance and compatibility tests on USB Power Delivery (USBPD) devices. Among these, the most common testing equipment includes: protocol analyzers, used to deeply analyze the USB PD communication protocol to ensure the correct implementation of PD functions; trainers, used to simulate the behavior of USB PD devices in different scenarios to verify the device's response mechanism and compatibility; multi-protocol PD power supplies, supporting multiple fast charging protocols and allowing flexible adjustment of output voltage and current to test the performance of USB PD devices under different charging conditions; and portable testers, facilitating rapid testing of USB PD devices in on-site or mobile environments.

[0003] However, traditional testing equipment generally suffers from a limitation: it lacks the ability to test multiple USB PD devices in parallel. Consequently, during testing, each device typically needs to be connected and tested one by one, leading to low testing efficiency. Therefore, how to test multiple USB PD devices in parallel is a technical problem that remains to be solved by those skilled in the art. Utility Model Content

[0004] This application proposes a multi-interface charging test motherboard, which aims to solve the technical problem of how to test multiple USB PD devices in parallel.

[0005] To address the aforementioned problems, this application proposes a multi-interface charging test motherboard, which includes:

[0006] Memory slots;

[0007] CPU socket, which is connected to the plurality of memory slots;

[0008] The PCH chip is connected to the CPU socket.

[0009] A Super I / O chip, which is connected to the PCH chip;

[0010] A charging test circuit, comprising multiple test interfaces, wherein the input terminal of the charging test circuit is connected to the output terminal of the Super I / O chip, and the output terminal of the charging test circuit is connected to the PCH chip;

[0011] The data transmission circuit has a first input terminal connected to the PCH chip, a second input terminal connected to the output terminal of the Super I / O chip, and an output terminal connected to each of the test interfaces in the charging test circuit.

[0012] In one embodiment, the charging test circuit includes:

[0013] The BC1.2 chip has its input terminal connected to the output terminal of the Super I / O chip.

[0014] The first USB interface group is connected to the output terminal of the BC1.2 chip;

[0015] A first monitoring chip, the input terminal of which is connected to the output terminal of the BC1.2 chip, and the output terminal of which is connected to the PCH chip;

[0016] A PD3.0 chip, wherein the input terminal of the PD3.0 chip is connected to the output terminal of the Super I / O chip;

[0017] The second USB interface group is connected to the output terminal of the PD3.0 chip, and the test interface type in the second USB interface group is different from the test interface type in the first USB interface group.

[0018] The second monitoring chip has its input terminal connected to the output terminal of the PD3.0 chip, and its output terminal connected to the PCH chip.

[0019] In one embodiment, the data transmission circuit includes:

[0020] The demultiplexing chipset has a first input terminal connected to the PCH chip, a second input terminal connected to the output terminal of the Super I / O chip, and an output terminal connected to each of the test interfaces in the charging test circuit.

[0021] In one embodiment, the multi-interface charging test motherboard further includes:

[0022] A network interface card (NIC) chipset, wherein the NIC chipset is connected to the PCH chip;

[0023] An RJ45 network port group, wherein the RJ45 network port group is connected to the network card chip group;

[0024] A serial port chip, which is connected to the Super I / O chip;

[0025] DB9 serial port, which is connected to the serial port chip.

[0026] In one embodiment, the multi-interface charging test motherboard further includes:

[0027] An HDMI interface is provided, which is connected to the CPU socket.

[0028] A VGA control chip, wherein the VGA control chip is connected to the CPU socket;

[0029] The VGA interface is connected to the VGA control chip.

[0030] In one embodiment, the multi-interface charging test motherboard further includes:

[0031] An M.2 KEY-M interface, which is connected to the PCH chip;

[0032] An M.2 KEY-E interface, which is connected to the PCH chip;

[0033] A SATA interface is provided, which is connected to the PCH chip.

[0034] In one embodiment, the multi-interface charging test motherboard further includes:

[0035] A sound card chip, wherein the sound card chip is connected to the PCH chip;

[0036] A LINE OUT interface, which is connected to the sound card chip;

[0037] The MIC interface is connected to the sound card chip.

[0038] In one embodiment, the multi-interface charging test motherboard further includes:

[0039] A fan interface, which is connected to the Super I / O chip;

[0040] Front panel headers are connected to the Super I / O chip.

[0041] In one embodiment, the multi-interface charging test motherboard further includes:

[0042] The third USB interface group is connected to the PCH chip.

[0043] In one embodiment, the multi-interface charging test motherboard further includes:

[0044] A PCIe 16x slot group, which is connected to the CPU socket;

[0045] A PCIe 4x slot group, which is connected to the CPU socket.

[0046] This application proposes a multi-interface charging test motherboard comprising: memory slots; a CPU slot connected to multiple memory slots; a PCH chip connected to the CPU slot; a Super I / O chip connected to the PCH chip; a charging test circuit including multiple test interfaces, wherein the input terminal of the charging test circuit is connected to the output terminal of the Super I / O chip, and the output terminal of the charging test circuit is connected to the PCH chip; and a data transmission circuit, wherein the first input terminal of the data transmission circuit is connected to the PCH chip, the second input terminal of the data transmission circuit is connected to the output terminal of the Super I / O chip, and the output terminal of the data transmission circuit is connected to each of the test interfaces in the charging test circuit.

[0047] In this application, the memory slot is used to connect memory modules to provide the data storage capacity required for motherboard operation; the CPU slot is used to connect the CPU, so that the PCH chip, Super I / O chip, and connected CPU on the motherboard can provide the data processing and peripheral management capabilities required for motherboard operation; the charging test circuit provides multiple test interfaces, which can connect and test multiple USB PD devices simultaneously. The data transmission circuit can use multiple demultiplexing chips to realize the reversible insertion function of the test interfaces and dynamically control the data transmission on / off, thereby not only supporting the simultaneous double-sided blind insertion operation of multiple devices, but also improving the motherboard communication stability and interface multiplexing efficiency. Therefore, the multi-interface charging test motherboard proposed in this application achieves the goal of parallel testing of multiple USB PD devices. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0049] Figure 1 A schematic diagram of the module connections for the first embodiment of the multi-interface charging test motherboard of this application;

[0050] Figure 2 A schematic diagram of the module connections for a second embodiment of the multi-interface charging test motherboard of this application;

[0051] Figure 3 A schematic diagram of the module connections for the third embodiment of the multi-interface charging test motherboard of this application;

[0052] Figure 4 A schematic diagram of the module connections for the fourth embodiment of the multi-interface charging test motherboard of this application;

[0053] Figure 5 This is a schematic diagram of the module connection of the fifth embodiment of the multi-interface charging test motherboard of this application.

[0054] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0055] Explanation of icon numbers:

[0056] 10. Memory slot; 20. CPU socket; 30. PCH chip; 40. Super I / O chip; 50. Charging test circuit; 60. Data transmission circuit; 501. BC1.2 chip; 502. First USB interface group; 503. First monitoring chip; 504. PD3.0 chip; 505. Second USB interface group; 506. Second monitoring chip; 601. Demultiplexing chipset; 70. Network card chipset; 80. RJ45 network port group; 90. Serial port chip; 100. DB9 serial port; 110. HDMI interface; 120. VGA control chip; 130. VGA interface; 140. M.2 KEY-M interface; 150. M.2 KEY-E interface; 160. SATA interface; 170. Sound card chip; 180. LINE OUT connector; 190, MIC connector; 200, fan connector; 210, front panel header; 220, third USB port group; 230, PCIe 16x slot group; 240, PCIe 4x slot group; 250, ATX power supply. Detailed Implementation

[0057] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. If the embodiments of the present utility model involve descriptions such as "first" or "second", such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of such features.

[0058] This application proposes a multi-interface charging test motherboard, which aims to solve the technical problem of how to test multiple USB PD devices in parallel.

[0059] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the module connections for the first embodiment of the multi-interface charging test motherboard of this application. Figure 1 As shown, the multi-interface charging test motherboard includes:

[0060] 10 memory slots;

[0061] CPU socket 20, which is connected to a plurality of memory slots 10;

[0062] PCH chip 30, which is connected to the CPU socket 20;

[0063] Super I / O chip 40, which is connected to PCH chip 30;

[0064] A charging test circuit 50 includes multiple test interfaces. The input terminal of the charging test circuit 50 is connected to the output terminal of the Super I / O chip 40, and the output terminal of the charging test circuit 50 is connected to the PCH chip 30.

[0065] The data transmission circuit 60 has a first input terminal connected to the PCH chip 30, a second input terminal connected to the output terminal of the Super I / O chip 40, and an output terminal connected to each of the test interfaces in the charging test circuit 50.

[0066] It should be noted that the multi-interface charging test motherboard proposed in this application is mainly used for charging tests of mobile phones. The mobile phone under test can be connected to the multi-interface charging test motherboard through the test interface in the charging test circuit 50. In one feasible implementation, the CPU socket 20 can support Intel 12th to 14th generation Core processors.

[0067] In this embodiment, the CPU socket 20 is connected to the PCH chip 30 via the DMI bus, and the PCH chip 30 is connected to the Super I / O chip 40 via the eSPI bus. To facilitate storage capacity, the CPU socket 20 can also connect to multiple memory slots 10 for connecting memory modules. For example, two SO-DIMM type DDR5 memory slots can be connected to the CPU socket 20. Since the DDR5 memory slots support dual-channel DDR5 memory with a maximum frequency of 4800MHz, the maximum storage capacity of the multi-interface charging test motherboard can be 32*2GB.

[0068] In this embodiment, memory slot 10 is used to connect memory modules to provide the data storage capacity required for motherboard operation; CPU slot 20 is used to connect the CPU, so the PCH chip 30, Super I / O chip 40 on the motherboard, and the connected CPU can provide the data processing and peripheral management capabilities required for motherboard operation; the charging test circuit 50 provides multiple test interfaces, which can connect and test multiple USB PD devices simultaneously; the data transmission circuit 60 can use multiple demultiplexing chips to realize the reversible insertion function of the test interfaces and dynamically control the data transmission on / off, thereby not only supporting the simultaneous double-sided blind insertion operation of multiple devices, but also improving the motherboard communication stability and interface multiplexing efficiency. Therefore, the multi-interface charging test motherboard proposed in this application achieves the goal of parallel testing of multiple USB PD devices.

[0069] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the module connection for the second embodiment of the multi-interface charging test motherboard of this application.

[0070] In this embodiment, the charging test circuit 50 includes:

[0071] BC1.2 chip 501, the input terminal of which is connected to the output terminal of Super I / O chip 40;

[0072] The first USB interface group 502 is connected to the output terminal of the BC1.2 chip 501;

[0073] The first monitoring chip 503 has its input terminal connected to the output terminal of the BC1.2 chip 501, and its output terminal connected to the PCH chip 30.

[0074] PD3.0 chip 504, the input terminal of which is connected to the output terminal of Super I / O chip 40;

[0075] The second USB interface group 505 is connected to the output terminal of the PD3.0 chip 504. The test interface type in the second USB interface group 505 is different from the test interface type in the first USB interface group 502.

[0076] The second monitoring chip 506 has its input terminal connected to the output terminal of the PD3.0 chip 504, and its output terminal connected to the PCH chip 30.

[0077] In one feasible implementation, the data transmission circuit 60 includes:

[0078] The demultiplexing chipset 601 has a first input terminal connected to the PCH chip 30, a second input terminal connected to the output terminal of the Super I / O chip 40, and an output terminal connected to each of the test interfaces in the charging test circuit 50.

[0079] It should be noted that the demultiplexing chipset 601 includes multiple demultiplexing chips, and the number of demultiplexing chips is the same as the total number of test interfaces. In this embodiment, the connection terminal between each demultiplexing chip and the PCH chip 30 is the first input terminal of the demultiplexing chipset 601, and the connection terminal between each demultiplexing chip and the Super I / O chip 40 is the second input terminal of the demultiplexing chipset 601.

[0080] In one feasible implementation, the first USB interface group 502 may include multiple USB 3.0 Type-A interfaces, and the second USB interface group 505 may include multiple USB 3.0 Type-C interfaces. During testing, the USB 3.0 Type-A and USB 3.0 Type-C interfaces are used to connect the mobile phone under test and provide charging and data transfer functions.

[0081] In one feasible implementation, the first USB interface group 502 may include two USB 3.0 Type-A interfaces, and the second USB interface group 505 may include eight USB 3.0 Type-C interfaces. This necessitates two BC1.2 chips 501, two first monitoring chips 503, eight PD3.0 chips 504, eight second monitoring chips 506, and ten demultiplexing chips. During testing, the Super I / O chip 40 connects to the PCH chip 30 via the eSPI bus and outputs signals to the BC1.2 chip 501, PD3.0 chip 504, and demultiplexing chips. Thus, the signals output by the Super I / O chip enable the PD3.0 chip and the BC1.2 chip to operate, thereby achieving independent on / off control of the charging function. The first monitoring chip 503 and the second monitoring chip 506 are connected to the PCH chip 30 via the SMBUS bus. During the charging test, the monitoring chips are used to detect the current output of the two USB 3.0 Type-A ports and the eight USB 3 Type-C ports in real time so that the testers can verify it.

[0082] In addition, in one feasible implementation, besides the PD3.0 protocol, the 8*Type-C interface also supports configuration to be compatible with QC and Apple fast charging protocols to improve charging test compatibility.

[0083] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the module connections for the third embodiment of the multi-interface charging test motherboard of this application.

[0084] In this embodiment, the multi-interface charging test motherboard further includes:

[0085] A network interface card (NIC) chipset 70 is connected to the PCH chip 30.

[0086] RJ45 network port group 80, which is connected to the network card chip group 70;

[0087] A serial port chip 90 is connected to the Super I / O chip 40;

[0088] DB9 serial port 100 is connected to the serial port chip 90.

[0089] In one feasible implementation, the multi-interface charging test motherboard further includes:

[0090] An HDMI interface 110 is connected to the CPU socket 20.

[0091] VGA control chip 120, which is connected to the CPU socket 20;

[0092] VGA interface 130, which is connected to the VGA control chip 120.

[0093] In this embodiment, the network interface card (NIC) chipset 70 may include multiple NIC chips. In one feasible implementation, the NIC chipset 70 may include a first NIC chip and a second NIC chip, and the RJ45 network port group 80 may include a first RJ45 network port and a second RJ45 network port. Thus, the first NIC chip and the second NIC chip can each be connected to the PCH chip 30 via a PCIe 1x signal, and then connected to the first RJ45 network port and the second RJ45 network port, respectively. Both the first and second RJ45 network ports support 2.5 GbE network connectivity, enabling network access. This allows the present application to not only perform large-scale data transmission with other network devices but also to achieve remote control functionality, thereby realizing fully automated unattended testing.

[0094] Furthermore, the connection between the serial port chip 90 and the Super I / O chip 40 in this application enables the conversion from TTL level to RS232 level. Moreover, this application also uses a DB9 interface to connect to the serial port chip 90, providing serial port transmission and reception functionality using the RS232 standard, to enable control or data transmission to other industrial equipment. Additionally, it should be noted that in this embodiment, the RJ45 network port group 80 and the DB9 serial port 100 are used for interconnection with other test equipment, facilitating the transmission of test data or mutual control between devices.

[0095] In this embodiment, the CPU socket 20 is directly connected to the HDMI interface 110 via DDI, and also to the VGA control chip 120 via DDI. The VGA control chip 120 is then connected to the VGA interface 130. Thus, through these connections, this application can achieve video transmission functionality based on the HDMI interface 110 and the VGA interface 130.

[0096] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the module connections for the fourth embodiment of the multi-interface charging test motherboard of this application.

[0097] In one feasible implementation, the multi-interface charging test motherboard further includes:

[0098] M.2 KEY-M interface 140, which is connected to the PCH chip 30;

[0099] M.2 KEY-E interface 150, which is connected to the PCH chip 30;

[0100] SATA interface 160, which is connected to PCH chip 30.

[0101] In one feasible implementation, the multi-interface charging test motherboard further includes:

[0102] Sound card chip 170, which is connected to PCH chip 30;

[0103] LINE OUT interface 180, which is connected to the sound card chip 170;

[0104] MIC interface 190, which is connected to the sound card chip 170.

[0105] In this embodiment, the M.2 KEY-M interface 140 is connected to the PCH chip 30 via PCIe and SATA signals, and is compatible with hard drives using both NVMe and SATA protocols. Therefore, the M.2 KEY-M interface 140 can automatically identify and adapt to the connected storage device, facilitating the installation of the operating system and the storage of programs, files, and data. Furthermore, the M.2 KEY-E interface 150 is connected to the PCH chip 30 via PCIe signals and can also connect to a Wi-Fi expansion module to improve the motherboard's network stability. Additionally, the SATA interface 160 is connected to the PCH chip 30 via SATA signals to provide support for SATA devices, enabling the connection of SATA hard drives.

[0106] In this embodiment, the sound card chip 170 can be connected to the PCH chip 30 via the HDA signal. The LINE OUT interface 180 and the MIC interface 190 are both connected to the sound card chip 170 to provide audio input and output functions for the motherboard.

[0107] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the module connection of the fifth embodiment of the multi-interface charging test motherboard of this application.

[0108] In this embodiment, the multi-interface charging test motherboard further includes:

[0109] Fan interface 200, which is connected to the Super I / O chip 40;

[0110] Front panel pin 210, which is connected to the Super I / O chip 40.

[0111] In one feasible implementation, the multi-interface charging test motherboard further includes:

[0112] The third USB interface group 220 is connected to the PCH chip 30.

[0113] In one feasible implementation, the multi-interface charging test motherboard further includes:

[0114] PCIe 16x slot group 230, which is connected to the CPU socket 20;

[0115] PCIe 4x slot group 240, which is connected to the CPU socket 20.

[0116] In one feasible implementation, an ATX power supply 250 is also provided to power the motherboard for multi-interface charging tests. Furthermore, the ATX power supply 250 interface differs from conventional ones; the CPU power connector is changed to an 8+8 pin configuration, thus providing sufficient current for charging tests.

[0117] In this embodiment, the Super I / O chip 40 is connected to the fan interface 200, enabling power supply and control of the fan; the Super I / O chip 40 is connected to the front panel header 210, providing power on / off, restart buttons and indicator lights on the front panel; the third USB interface group 220 may include multiple USB ports, facilitating the connection of peripheral devices such as keyboards, mice, and USB flash drives, thereby facilitating file transfer; in addition, this application also facilitates the connection of PCIe expansion devices by connecting to the PCIe 16x slot group 230 and the PCIe 4x slot group 240, thereby improving the application's adaptability to various scenarios.

[0118] The above are merely optional embodiments of this utility model and do not limit the patent scope of this utility model. All equivalent structural transformations made based on the contents of this utility model specification and drawings under the utility model concept, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this utility model.

Claims

1. A multi-interface charging test motherboard, characterized in that, The multi-interface charging test motherboard includes: Memory slots; CPU socket, which is connected to the plurality of memory slots; The PCH chip is connected to the CPU socket. A Super I / O chip, which is connected to the PCH chip; A charging test circuit, comprising multiple test interfaces, wherein the input terminal of the charging test circuit is connected to the output terminal of the Super I / O chip, and the output terminal of the charging test circuit is connected to the PCH chip; The data transmission circuit has a first input terminal connected to the PCH chip, a second input terminal connected to the output terminal of the Super I / O chip, and an output terminal connected to each of the test interfaces in the charging test circuit.

2. The multi-interface charging test motherboard as described in claim 1, characterized in that, The charging test circuit includes: The BC1.2 chip has its input terminal connected to the output terminal of the Super I / O chip. The first USB interface group is connected to the output terminal of the BC1.2 chip; A first monitoring chip, the input terminal of which is connected to the output terminal of the BC1.2 chip, and the output terminal of which is connected to the PCH chip; A PD3.0 chip, wherein the input terminal of the PD3.0 chip is connected to the output terminal of the Super I / O chip; The second USB interface group is connected to the output terminal of the PD3.0 chip, and the test interface type in the second USB interface group is different from the test interface type in the first USB interface group. The second monitoring chip has its input terminal connected to the output terminal of the PD3.0 chip, and its output terminal connected to the PCH chip.

3. The multi-interface charging test motherboard as described in claim 1, characterized in that, The data transmission circuit includes: The demultiplexing chipset has a first input terminal connected to the PCH chip, a second input terminal connected to the output terminal of the Super I / O chip, and an output terminal connected to each of the test interfaces in the charging test circuit.

4. The multi-interface charging test motherboard as described in claim 1, characterized in that, The multi-interface charging test motherboard also includes: A network interface card (NIC) chipset, wherein the NIC chipset is connected to the PCH chip; An RJ45 network port group, wherein the RJ45 network port group is connected to the network card chip group; A serial port chip, which is connected to the Super I / O chip; DB9 serial port, which is connected to the serial port chip.

5. The multi-interface charging test motherboard as described in claim 1, characterized in that, The multi-interface charging test motherboard also includes: An HDMI interface is provided, which is connected to the CPU socket. A VGA control chip, wherein the VGA control chip is connected to the CPU socket; The VGA interface is connected to the VGA control chip.

6. The multi-interface charging test motherboard as described in claim 1, characterized in that, The multi-interface charging test motherboard also includes: An M.2 KEY-M interface, which is connected to the PCH chip; An M.2 KEY-E interface, which is connected to the PCH chip; A SATA interface is provided, which is connected to the PCH chip.

7. The multi-interface charging test motherboard as described in claim 1, characterized in that, The multi-interface charging test motherboard also includes: A sound card chip, wherein the sound card chip is connected to the PCH chip; A LINE OUT interface, which is connected to the sound card chip; The MIC interface is connected to the sound card chip.

8. The multi-interface charging test motherboard as described in claim 1, characterized in that, The multi-interface charging test motherboard also includes: A fan interface, which is connected to the Super I / O chip; Front panel headers are connected to the Super I / O chip.

9. The multi-interface charging test motherboard as described in claim 1, characterized in that, The multi-interface charging test motherboard also includes: The third USB interface group is connected to the PCH chip.

10. The multi-interface charging test motherboard as described in claim 1, characterized in that, The multi-interface charging test motherboard also includes: A PCIe 16x slot group, which is connected to the CPU socket; A PCIe 4x slot group, which is connected to the CPU socket.

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