Carrier board compatible with NVIDIA core board

Abstract

The utility model belongs to the technical field of core boards, and relates to a carrier board compatible with an NVIDIA core board. Comprising a direct-current power supply input management circuit, a USB switching circuit, a camera serial interface connector circuit, a direct-current jitter elimination slow start circuit, a core board configuration circuit, a fan interface circuit, a serial port circuit, an M.2 interface monitoring circuit and a POE gigabit Ethernet circuit which are electrically connected, the direct-current power supply input management circuit is used for converting an external direct-current power supply into stable voltage and current to be used by the core board, the USB switching circuit is used for controlling on-off of a USB interface, and the camera serial interface connector circuit is used for being connected with external camera equipment to realize transmission of image data and exchange of control signals. Stable and reliable power supply can be obtained, a user can be allowed to flexibly control opening and closing of the USB interface, power saving is facilitated, and the core board can be protected against connection of unauthorized equipment when necessary.

Description

Technical Field

[0001] This utility model relates to the field of core board technology, and more specifically, to a carrier board compatible with NVIDIA core boards. Background Technology

[0002] NVIDIA, short for Nvidia Corporation, is a leading global manufacturer of graphics processing units (GPUs), whose products are widely used in gaming, artificial intelligence, data centers, and other fields. However, many current motherboards suffer from incompatibility with NVIDIA, posing numerous challenges and drawbacks for users and developers.

[0003] Incompatible carrier boards with NVIDIA core boards may cause system instability. Due to incompatibility between drivers and hardware, users may experience frequent crashes, blue screens, or unresponsive systems. These problems not only affect normal user operation but may also lead to data loss and system corruption.

[0004] Incompatible carrier boards limit the utilization of high-performance GPUs. NVIDIA GPUs are renowned for their exceptional computing and graphics processing capabilities, but on incompatible carrier boards, these capabilities may not be fully realized. This means users may not be able to enjoy the latest graphics technologies and optimizations, thus impacting the overall user experience.

[0005] Incompatibility issues can also lead to wasted hardware resources. Some motherboards may be equipped with high-performance NVIDIA GPUs, but due to driver incompatibility, these hardware resources may not be fully utilized. This not only increases the user's hardware costs but may also lead to a decrease in overall system performance. Utility Model Content

[0006] To address the aforementioned deficiencies in the prior art, this utility model provides a carrier board compatible with NVIDIA core boards, comprising:

[0007] The core board is electrically connected to a DC power input management circuit, a USB switch circuit, a camera serial interface connector circuit, a DC image stabilization soft-start circuit, a core board configuration circuit, a fan interface circuit, a serial port circuit, an M.2 interface monitoring circuit, and a PoE Gigabit Ethernet circuit. The DC power input management circuit converts external DC power into stable voltage and current for the core board. The USB switch circuit controls the on / off state of the USB interface. The camera serial interface connector circuit connects to external camera devices for image data transmission and control signal exchange. The DC image stabilization soft-start circuit provides unidirectional conductivity, protecting the core board from reverse voltage and current surges. The core board configuration circuit enables signal transmission and configuration control between the core board and the carrier board. The fan interface circuit connects to external fans for heat dissipation control. The serial port circuit enables serial communication between the core board and external devices. The M.2 interface monitoring circuit monitors the status and performance of storage devices installed in the M.2 slot. The PoE Gigabit Ethernet circuit enables data transmission and power supply between the core board and network devices.

[0008] Preferably, the DC power input management circuit includes: the source of the field-effect transistor Q25 is connected to one end of capacitor C168, one end of resistor R181, one end of capacitor C171, the cathode of diode D65, one end of resistor R171, one end of diode D64, and one end of DC terminal J16; the other end of diode D64 is grounded; the other end of resistor R171 is connected to one end of capacitor C143; and the other end of capacitor C143, the anode of diode D65, and the other end of capacitor C171 are connected to... All terminals are grounded. The other end of resistor R181 is connected to one end of resistor R182, the other end of capacitor C168, and the gate of MOSFET Q25. The other end of resistor R182 is grounded. The drain of MOSFET Q25 is connected to one end of resistor R260 and one end of resistor R261. The other end of resistor R260 is connected to one end of capacitor C203, and the other end of capacitor C203 is grounded. The other end of resistor R261 is connected to one end of capacitor C204, and the other end of capacitor C204 is grounded.

[0009] Preferably, the USB switch circuit includes: pin 10 of USB switch chip U11 is connected to one end of resistor R450, the other end of resistor R450 is grounded, pin 1 of USB switch chip U11 is connected to one end of resistor R451, pin 2 of USB switch chip U11 is connected to one end of resistor R452, pin 7 of USB switch chip U11 is connected to one end of resistor R453, pin 6 of USB switch chip U11 is connected to one end of resistor R454, pin 8 of USB switch chip U11 is connected to one end of resistor R95, the other end of resistor R95 is grounded, and the other end of resistor R451 is connected to the other ends of resistor R452, resistor R453, and resistor R454 respectively.

[0010] Preferably, the camera serial interface connector circuit includes: pin 1 of FFC&FPC connector J20 connected to one end of capacitor C106; pin 5 of FFC&FPC connector J20 connected to one end of diode D35; pin 6 of FFC&FPC connector J20 connected to one end of diode D34 and pin 4 of single-supply single-buffer gate chip U57 respectively; pin 8 of FFC&FPC connector J20 connected to one end of diode D33; pin 9 of FFC&FPC connector J20 connected to one end of diode D32; and pin 11 of FFC&FPC connector J20 connected to one end of diode D31. For the connection, pin 12 of FFC&FPC connector J20 is connected to one end of diode D30, pin 14 of FFC&FPC connector J20 is connected to one end of diode D29, pin 15 of FFC&FPC connector J20 is connected to one end of diode D28, pin 17 of FFC&FPC connector J20 is connected to one end of diode D27, pin 18 of FFC&FPC connector J20 is connected to one end of diode D26, pin 20 of FFC&FPC connector J20 is connected to one end of diode D25, and pin 6 of FFC&FPC connector J21 is connected to one end of diode D24.

[0011] Preferably, the DC debounce soft-start circuit includes: the drain of the field-effect transistor Q23 is connected to the emitter of the transistor Q24A; the collector of the transistor Q24A is connected to the base of the transistor Q24A, one end of the resistor R179, and the base of the transistor Q24B; the other end of the resistor R179 is connected to one end of the resistor R180 and grounded; the other end of the resistor R180 is connected to the gate of the field-effect transistor Q23 and the collector of the transistor Q24B; and the source of the field-effect transistor Q23 is connected to the emitter of the transistor Q24B.

[0012] Preferably, the core board configuration circuit includes: pin 1 of the serial EEPROM chip U17 is connected to one end of resistor R131 and one end of resistor R132 respectively; pin 2 of the serial EEPROM chip U17 is connected to one end of resistor R129 and one end of resistor R130 respectively; pin 3 of the serial EEPROM chip U17 is connected to one end of resistor R127 and one end of resistor R128 respectively; pin 7 of the serial EEPROM chip U17 is connected to one end of resistor R126; pin 8 of the serial EEPROM chip U17 is connected to one end of capacitor C134; and the other ends of resistors R126, R128, R130, R132 and C134 are all grounded.

[0013] Preferably, the fan interface circuit includes: pin 1 of a single-bit dual-power bus transceiver chip U15 is connected to one end of capacitor C430; pin 3 of the single-bit dual-power bus transceiver chip U15 is connected to one end of resistor R122 and one end of resistor R543 respectively; pin 4 of the single-bit dual-power bus transceiver chip U15 is connected to one end of resistor R119; pin 6 of the single-bit dual-power bus transceiver chip U15 is connected to one end of capacitor C429; the other end of capacitor C429, the other end of resistor R119, and the... The other end of capacitor C430 and the other end of resistor R122 are grounded. The other end of resistor R543 is connected to pin 4 of field-effect transistor chip J13. Pin 2 of field-effect transistor chip J13 is connected to one end of resistor R124 and one end of capacitor C132 respectively. The other end of resistor R124 is connected to pin 3 of field-effect transistor chip J13 and the drain of field-effect transistor Q20 respectively. The gate of field-effect transistor Q20 is connected to one end of resistor R123. The other end of resistor R123 is connected to the source of field-effect transistor Q20.

[0014] Preferably, the serial port circuit includes: pin 1 of level conversion chip U16 is connected to one end of capacitor C129, pin 5 of level conversion chip U16 is connected to one end of resistor R120, pin 7 of level conversion chip U16 is connected to one end of resistor R125, and pin 8 of level conversion chip U16 is connected to one end of capacitor C130 and one end of resistor R125 respectively.

[0015] Preferably, the M.2 interface monitoring circuit includes: pin 4 of buffer chip U56 is connected to one end of resistor R518, pin 5 of buffer chip U56 is connected to one end of capacitor C392, and pin 2 of buffer chip U56 is connected to one end of resistor R497, one end of resistor R512, one end of resistor R513, and one end of resistor R514, respectively.

[0016] Preferably, the PoE Gigabit Ethernet circuit includes: pin 10 of Ethernet connector chip J1 connected to one end of capacitor C37; pin 11 of Ethernet connector chip J1 connected to one end of resistor R36; pin 14 of Ethernet connector chip J1 connected to one end of resistor R37; pin 12 of Ethernet connector chip J1 connected to one end of resistor R146; pin 13 of Ethernet connector chip J1 connected to one end of resistor R147; pin 1 of Ethernet connector chip J1 connected to one end of resistor R35 and one end of capacitor C136 respectively; and the other end of resistor R36 connected to the other end of resistor R37 and the other end of resistor R35 respectively.

[0017] The carrier board compatible with the NVIDIA core board, implementing this utility model, has the following beneficial effects: The DC power input management circuit ensures that the core board receives a stable and reliable power supply, which is crucial for maintaining the continuous and efficient operation of the system; the USB switch circuit allows users to flexibly control the opening and closing of the USB interface, which not only helps save power but also protects the core board from unauthorized device connections when necessary; the introduction of the camera serial interface connector circuit enables the core board to easily connect to various external camera devices, providing strong support for image processing and machine vision applications; the unidirectional conductivity of the DC anti-shake soft-start circuit provides additional protection for the core board, effectively preventing reverse voltage and current surges, further enhancing the stability and security of the system; the core board configuration circuit simplifies signal transmission and configuration control between the core board and the carrier board, providing developers with greater flexibility and convenience; the addition of the fan interface circuit and the circuit with PoE Gigabit Ethernet solves the problems of heat dissipation, data transmission, and power supply, respectively, enabling the core board to maintain excellent stability and scalability even in high-performance application scenarios. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort. The utility model will be further described below in conjunction with the drawings and embodiments. In the drawings:

[0019] Figure 1 This is a schematic diagram of the module structure of the carrier board compatible with the NVIDIA core board of this utility model;

[0020] Figure 2 This is a circuit diagram of the DC power input management circuit in the carrier board of the present invention, which is compatible with the NVIDIA core board;

[0021] Figure 3 This is a circuit diagram of the USB switch circuit in the carrier board of the present invention, which is compatible with the NVIDIA core board.

[0022] Figure 4 This is a circuit diagram of the camera serial interface connector circuit in the carrier board of the present invention, which is compatible with the NVIDIA core board.

[0023] Figure 5 This is a circuit diagram of the DC debouncing soft-start circuit in the carrier board of the present invention, which is compatible with the NVIDIA core board;

[0024] Figure 6 This is a circuit diagram of the core board configuration circuit in the carrier board compatible with the NVIDIA core board of this utility model;

[0025] Figure 7 This is a circuit diagram of the fan interface circuit in the carrier board of the present invention, which is compatible with the NVIDIA core board;

[0026] Figure 8 This is a circuit diagram of the serial port circuit in the carrier board of the NVIDIA core board compatible with this utility model;

[0027] Figure 9 This is a circuit diagram of the M.2 interface monitoring circuit in the carrier board of the NVIDIA core board compatible with this utility model;

[0028] Figure 10 This is a circuit diagram of the PoE Gigabit Ethernet circuit in the carrier board of the NVIDIA core board compatible with this utility model. Detailed Implementation

[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0030] It should be noted that if the embodiments of this utility model involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0031] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0032] Please see Figure 1 This is a schematic diagram of the module structure of the carrier board compatible with the NVIDIA core board of this utility model. Figure 1 As shown, the carrier board compatible with the NVIDIA core board provided in the first embodiment of this utility model includes at least the following electrically connected components: a DC power input management circuit, a USB switch circuit, a camera serial interface connector circuit, a DC de-shake soft-start circuit, a core board configuration circuit, a fan interface circuit, a serial port circuit, an M.2 interface monitoring circuit, and a PoE Gigabit Ethernet circuit. The DC power input management circuit converts external DC power into stable voltage and current for the core board. The USB switch circuit controls the on / off state of the USB interface. The camera serial interface connector circuit connects to external camera devices to transmit image data and exchange control signals. The DC de-shake soft-start circuit provides unidirectional conductivity to protect the core board from reverse voltage and current surges. The core board configuration circuit enables signal transmission and configuration control between the core board and the carrier board. The fan interface circuit connects to external fan devices for heat dissipation control. The serial port circuit enables serial communication between the core board and external devices. The M.2 interface monitoring circuit monitors the status and performance of the storage device installed in the M.2 slot. The PoE Gigabit Ethernet circuit enables data transmission and power supply between the core board and network devices.

[0033] Figure 2 This is a circuit diagram of the DC power input management circuit in the carrier board of this utility model, which is compatible with the NVIDIA core board. Figure 2As shown, the DC power input management circuit includes: the source of the field-effect transistor Q25 is connected to one end of capacitor C168, one end of resistor R181, one end of capacitor C171, the cathode of diode D65, one end of resistor R171, one end of diode D64, and one end of DC terminal J16. The other end of diode D64 is grounded. The other end of resistor R171 is connected to one end of capacitor C143. The other end of capacitor C143, the anode of diode D65, and the other end of capacitor C171 are all... The resistor R181 is grounded. The other end of the resistor R181 is connected to one end of the resistor R182, the other end of the capacitor C168, and the gate of the field-effect transistor Q25. The other end of the resistor R182 is grounded. The drain of the field-effect transistor Q25 is connected to one end of the resistor R260 and one end of the resistor R261. The other end of the resistor R260 is connected to one end of the capacitor C203, and the other end of the capacitor C203 is grounded. The other end of the resistor R261 is connected to one end of the capacitor C204, and the other end of the capacitor C204 is grounded.

[0034] The DC power input management circuit simplifies the task of dynamic power selection, enabling it to select and control the path of power flow to the system, choosing the input source based on the highest voltage or highest priority. The main function of this circuit is to ensure that the system can select the most suitable power source from multiple available power supplies, thereby improving system reliability and stability. Furthermore, it provides redundant power in case of input faults or short circuits, and maintains output power supply during input power loss.

[0035] NVIDIA core boards have stringent power management requirements; therefore, the DC power input management circuitry must meet NVIDIA's power specifications and electrical characteristics. Precise circuit parameter design ensures the stability and accuracy of output voltage and current, thereby meeting the power requirements of the NVIDIA core board and its components.

[0036] Figure 3 This is a circuit diagram of the USB switch circuit in the carrier board of this utility model, which is compatible with the NVIDIA core board. Figure 3 As shown, the USB switch circuit includes: pin 10 of USB switch chip U11 is connected to one end of resistor R450, the other end of resistor R450 is grounded; pin 1 of USB switch chip U11 is connected to one end of resistor R451; pin 2 of USB switch chip U11 is connected to one end of resistor R452; pin 7 of USB switch chip U11 is connected to one end of resistor R453; pin 6 of USB switch chip U11 is connected to one end of resistor R454; pin 8 of USB switch chip U11 is connected to one end of resistor R95, the other end of resistor R95 is grounded; and the other end of resistor R451 is connected to the other ends of resistors R452, R453, and R454 respectively.

[0037] In practical implementation, the USB switch chip U11 can be, but is not limited to, the TS3USB30E. The TS3USB30E is a high-bandwidth 1:2 switch chip with a wide bandwidth of 900MHz, resulting in extremely low edge and phase distortion during signal transmission. Its working principle is to multiplex the differential output of a USB host device to one of two corresponding outputs, or to multiplex the differential outputs of two different hosts to one corresponding output. This bidirectional switch provides almost no attenuation to high-speed signals at the output, thus ensuring high-quality signal transmission.

[0038] Furthermore, the TS3USB30E chip features low bit-to-bit skew and high channel-to-channel noise isolation, making it compatible with various standards such as high-speed USB 2.0 (480Mbps). The chip integrates ESD protection units on all pins and is available in a miniature UQFN package (1.8mm × 1.4mm) or VSSOP package, enhancing its reliability and durability. Its rated operating temperature range is -40°C to 85°C, meeting the application requirements in various environments.

[0039] The USB switching circuit controls the power supply to the USB interface by controlling the on / off state of a switching element. When a USB device is connected to the core board, the switching circuit detects the device's insertion status and turns the power on or off as needed. Furthermore, the USB switching circuit also enables hot-swapping of the USB interface, automatically switching the power state when a device is connected or disconnected to protect the core board from transient voltage or current surges.

[0040] The USB interface on the NVIDIA core board needs to support high-speed data transfer and power management. Therefore, the USB switching circuitry needs to have fast response and low power consumption to ensure stable data transfer and effective power management. Good compatibility with the NVIDIA core board can be achieved by selecting appropriate switching components and optimizing the circuit design.

[0041] Figure 4 This is a circuit diagram of the camera serial interface connector circuit in the carrier board of this utility model, which is compatible with the NVIDIA core board. Figure 4As shown, the camera serial interface connector circuit includes: pin 1 of FFC&FPC connector J20 is connected to one end of capacitor C106; pin 5 of FFC&FPC connector J20 is connected to one end of diode D35; pin 6 of FFC&FPC connector J20 is connected to one end of diode D34 and pin 4 of single-supply single-buffer gate chip U57 respectively; pin 8 of FFC&FPC connector J20 is connected to one end of diode D33; pin 9 of FFC&FPC connector J20 is connected to one end of diode D32; and pin 11 of FFC&FPC connector J20 is connected to one end of diode D31. Pin 12 of FFC&FPC connector J20 is connected to one end of diode D30; pin 14 of FFC&FPC connector J20 is connected to one end of diode D29; pin 15 of FFC&FPC connector J20 is connected to one end of diode D28; pin 17 of FFC&FPC connector J20 is connected to one end of diode D27; pin 18 of FFC&FPC connector J20 is connected to one end of diode D26; pin 20 of FFC&FPC connector J20 is connected to one end of diode D25; and pin 6 of FFC&FPC connector J21 is connected to one end of diode D24.

[0042] The camera serial interface connector circuit is used to connect external camera devices to enable the transmission of image data and the exchange of control signals.

[0043] Camera serial interface connector circuits typically employ serial communication protocols such as UART (Universal Asynchronous Receiver / Transmitter) or SPI (Serial Peripheral Interface). UART transmits data by sending and receiving data frames, while SPI uses clock and data signals for synchronous communication. The camera serial interface connector circuit is responsible for converting signals from external camera devices into a signal format recognizable by the core board and transmitting data and control signals to the core board via the serial communication interface.

[0044] NVIDIA core boards typically support a variety of image processing and video encoding / decoding functions. Therefore, the camera serial interface connector circuitry needs to feature high-speed data transmission and low latency to meet the demands of image processing. By optimizing the circuit design and selecting a suitable communication protocol, good compatibility with NVIDIA core boards can be achieved, fully utilizing their image processing and video encoding / decoding capabilities.

[0045] Figure 5 This is a circuit diagram of the DC debouncing soft-start circuit in the carrier board of this utility model, which is compatible with the NVIDIA core board. Figure 5As shown, the DC debounce soft-start circuit includes: the drain of the field-effect transistor Q23 is connected to the emitter of the transistor Q24A; the collector of the transistor Q24A is connected to the base of the transistor Q24A, one end of the resistor R179, and the base of the transistor Q24B; the other end of the resistor R179 is connected to one end of the resistor R180 and grounded; the other end of the resistor R180 is connected to the gate of the field-effect transistor Q23 and the collector of the transistor Q24B; and the source of the field-effect transistor Q23 is connected to the emitter of the transistor Q24B.

[0046] The DC debounce soft-start circuit is used to achieve unidirectional conductivity and protect the core board from reverse voltage and current surges.

[0047] The DC debounce soft-start circuit features forward conduction and reverse cutoff. When a forward voltage is applied to the diode, the diode conducts, allowing current to flow; when a reverse voltage is applied to the diode, the diode cuts off, blocking the current. This characteristic is utilized to limit reverse voltage and current within safe limits, thereby protecting the core board from damage.

[0048] NVIDIA core boards have stringent requirements for circuit protection to ensure their stability and reliability. As a crucial component of circuit protection, the DC debouncing soft-start circuit needs to possess characteristics of fast response and low loss. By selecting appropriate diode components and optimizing the circuit design, good compatibility with NVIDIA core boards can be achieved, providing effective circuit protection.

[0049] Figure 6 This is a circuit diagram of the core board configuration circuit in the carrier board compatible with the NVIDIA core board of this utility model. Figure 6 As shown, the core board configuration circuit includes: pin 1 of the serial EEPROM chip U17 is connected to one end of resistor R131 and one end of resistor R132 respectively; pin 2 of the serial EEPROM chip U17 is connected to one end of resistor R129 and one end of resistor R130 respectively; pin 3 of the serial EEPROM chip U17 is connected to one end of resistor R127 and one end of resistor R128 respectively; pin 7 of the serial EEPROM chip U17 is connected to one end of resistor R126; pin 8 of the serial EEPROM chip U17 is connected to one end of capacitor C134; and the other ends of resistors R126, R128, R130, R132, and C134 are all grounded.

[0050] The core board configuration circuit is used to realize signal transmission and configuration control between the core board and the carrier board.

[0051] NVIDIA core boards support a variety of extended functions and interfaces, therefore the core board configuration circuitry needs to be flexible and scalable. By optimizing circuit design and selecting appropriate configuration chips, good compatibility with NVIDIA core boards can be achieved, and the configuration and initialization requirements of various carrier boards can be supported.

[0052] Figure 7 This is a circuit diagram of the fan interface circuit in the carrier board of this utility model, which is compatible with the NVIDIA core board. Figure 7 As shown, the fan interface circuit includes: pin 1 of the single-bit dual-power bus transceiver chip U15 is connected to one end of capacitor C430; pin 3 of the single-bit dual-power bus transceiver chip U15 is connected to one end of resistor R122 and one end of resistor R543 respectively; pin 4 of the single-bit dual-power bus transceiver chip U15 is connected to one end of resistor R119; pin 6 of the single-bit dual-power bus transceiver chip U15 is connected to one end of capacitor C429; the other end of capacitor C429, the other end of resistor R119, and capacitor... The other end of C430 and the other end of resistor R122 are grounded. The other end of resistor R543 is connected to pin 4 of field-effect transistor chip J13. Pin 2 of field-effect transistor chip J13 is connected to one end of resistor R124 and one end of capacitor C132. The other end of resistor R124 is connected to pin 3 of field-effect transistor chip J13 and the drain of field-effect transistor Q20. The gate of field-effect transistor Q20 is connected to one end of resistor R123. The other end of resistor R123 is connected to the source of field-effect transistor Q20.

[0053] In specific implementation, the single-bit dual-power bus transceiver chip U15 can be, but is not limited to, SN74LVC1T45DCKR, etc.

[0054] The fan interface circuit is used to connect external fan devices to achieve heat dissipation control.

[0055] NVIDIA motherboards have stringent requirements for thermal control to ensure their stability and reliability. The fan connector circuitry ensures good compatibility with NVIDIA motherboards and provides effective thermal control.

[0056] Figure 8 This is a circuit diagram of the serial port circuit in the carrier board of this utility model, which is compatible with the NVIDIA core board. Figure 8 As shown, the serial port circuit includes: pin 1 of level conversion chip U16 is connected to one end of capacitor C129, pin 5 of level conversion chip U16 is connected to one end of resistor R120, pin 7 of level conversion chip U16 is connected to one end of resistor R125, and pin 8 of level conversion chip U16 is connected to one end of capacitor C130 and one end of resistor R125 respectively.

[0057] In practice, the level conversion chip U16 can be, but is not limited to, TXB0302DQMR, etc.

[0058] The serial port circuit is used to enable serial communication between the core board and external devices.

[0059] Serial port circuits typically employ communication protocols such as RS-232, RS-485, or USB-to-serial. RS-232 and RS-485 communicate via differential signals, offering longer transmission distances and better interference resistance. USB-to-serial converters transform a USB interface into a standard serial interface, enabling connection to external devices. The serial port circuitry is responsible for converting signals from external devices into a signal format recognizable by the core board and transmitting data and control signals through the serial communication interface.

[0060] NVIDIA core boards support multiple serial communication protocols and interface standards. Therefore, the serial port circuitry needs to be flexible and scalable to meet the needs of different external devices. By selecting appropriate communication protocols and interface standards and optimizing circuit design, good compatibility with NVIDIA core boards can be achieved, supporting the connection and communication of various external devices.

[0061] Figure 9 This is a circuit diagram of the M.2 interface monitoring circuit in the carrier board of this utility model, which is compatible with the NVIDIA core board. Figure 9 As shown, the M.2 interface monitoring circuit includes: pin 4 of buffer chip U56 is connected to one end of resistor R518, pin 5 of buffer chip U56 is connected to one end of capacitor C392, and pin 2 of buffer chip U56 is connected to one end of resistor R497, one end of resistor R512, one end of resistor R513, and one end of resistor R514, respectively.

[0062] The M.2 interface monitoring circuit is used to monitor the status and performance of storage devices (such as SSDs) installed in the M.2 slot. The M.2 interface monitoring circuit can monitor the status of the storage device in real time to ensure its normal operation and stable performance.

[0063] NVIDIA core boards support high-speed storage interfaces and data transfer capabilities. Therefore, the M.2 interface monitoring circuitry needs to possess high accuracy and real-time performance to meet the monitoring requirements of storage devices. The M.2 interface monitoring circuitry achieves good compatibility with NVIDIA core boards and provides them with effective storage device monitoring functionality.

[0064] Figure 10 This is a circuit diagram of the PoE Gigabit Ethernet circuit in the carrier board of this utility model, which is compatible with the NVIDIA core board. Figure 10As shown, the Gigabit Ethernet circuit with PoE includes: pin 10 of Ethernet connector chip J1 is connected to one end of capacitor C37; pin 11 of Ethernet connector chip J1 is connected to one end of resistor R36; pin 14 of Ethernet connector chip J1 is connected to one end of resistor R37; pin 12 of Ethernet connector chip J1 is connected to one end of resistor R146; pin 13 of Ethernet connector chip J1 is connected to one end of resistor R147; pin 1 of Ethernet connector chip J1 is connected to one end of resistor R35 and one end of capacitor C136 respectively; and the other end of resistor R36 is connected to the other end of resistor R37 and the other end of resistor R35 respectively.

[0065] Ethernet connector chip J1 is responsible for handling the sending and receiving of data packets, as well as the transmission and reception of physical layer signals. In specific implementations, Ethernet connector chip J1 can be, but is not limited to, HR911130C, etc.

[0066] NVIDIA core boards support high-speed network communication and data transmission. Therefore, circuitry with PoE Gigabit Ethernet needs to feature high-speed data transmission and low latency to meet network communication requirements. Simultaneously, the PoE power management module needs stable power output and efficient energy management to ensure the normal operation of the core board and its components. Circuitry with PoE Gigabit Ethernet achieves good compatibility with NVIDIA core boards and provides them with efficient network communication and power supply capabilities.

[0067] The beneficial effects of this invention, through the design of the above embodiments, are as follows: The DC power input management circuit ensures that the core board receives a stable and reliable power supply, which is crucial for maintaining the continuous and efficient operation of the system; the USB switch circuit allows users to flexibly control the opening and closing of the USB interface, which not only helps save power but also protects the core board from unauthorized device connections when necessary; the introduction of the camera serial interface connector circuit enables the core board to easily connect to various external camera devices, providing strong support for image processing and machine vision applications; the unidirectional conductivity of the DC anti-shake soft-start circuit provides additional protection for the core board, effectively preventing reverse voltage and current surges, further enhancing the stability and security of the system; the core board configuration circuit simplifies signal transmission and configuration control between the core board and the carrier board, providing developers with greater flexibility and convenience; the addition of the fan interface circuit and the circuit with PoE Gigabit Ethernet solves the problems of heat dissipation, data transmission, and power supply, respectively, enabling the core board to maintain excellent stability and scalability even in high-performance application scenarios.

[0068] This utility model has been described based on specific embodiments, but those skilled in the art will understand that various changes and equivalent substitutions can be made without departing from the scope of this utility model. Furthermore, to adapt to specific applications of this utility model, numerous modifications can be made without departing from its protection scope. Therefore, this utility model is not limited to the specific embodiments disclosed herein, but includes all embodiments falling within the protection scope of the claims.

Claims

1. A carrier board compatible with NVIDIA core boards, characterized in that, include: The core board is electrically connected to a DC power input management circuit, a USB switch circuit, a camera serial interface connector circuit, a DC image stabilization soft-start circuit, a core board configuration circuit, a fan interface circuit, a serial port circuit, an M.2 interface monitoring circuit, and a PoE Gigabit Ethernet circuit. The DC power input management circuit converts external DC power into stable voltage and current for the core board. The USB switch circuit controls the on / off state of the USB interface. The camera serial interface connector circuit connects to external camera devices for image data transmission and control signal exchange. The DC image stabilization soft-start circuit provides unidirectional conductivity, protecting the core board from reverse voltage and current surges. The core board configuration circuit enables signal transmission and configuration control between the core board and the carrier board. The fan interface circuit connects to external fans for heat dissipation control. The serial port circuit enables serial communication between the core board and external devices. The M.2 interface monitoring circuit monitors the status and performance of storage devices installed in the M.2 slot. The PoE Gigabit Ethernet circuit enables data transmission and power supply between the core board and network devices.

2. The carrier board compatible with NVIDIA core boards according to claim 1, characterized in that, The DC power input management circuit includes: the source of the field-effect transistor Q25 is connected to one end of capacitor C168, one end of resistor R181, one end of capacitor C171, the cathode of diode D65, one end of resistor R171, one end of diode D64, and one end of DC terminal J16; the other end of diode D64 is grounded; the other end of resistor R171 is connected to one end of capacitor C143; and the other end of capacitor C143, the anode of diode D65, and the other end of capacitor C171 are all connected to the source of the field-effect transistor Q25. The resistor R181 is grounded. The other end of the resistor R181 is connected to one end of the resistor R182, the other end of the capacitor C168, and the gate of the field-effect transistor Q25. The other end of the resistor R182 is grounded. The drain of the field-effect transistor Q25 is connected to one end of the resistor R260 and one end of the resistor R261. The other end of the resistor R260 is connected to one end of the capacitor C203, and the other end of the capacitor C203 is grounded. The other end of the resistor R261 is connected to one end of the capacitor C204, and the other end of the capacitor C204 is grounded.

3. The carrier board compatible with NVIDIA core boards according to claim 1, characterized in that, The USB switch circuit includes: pin 10 of USB switch chip U11 is connected to one end of resistor R450, the other end of resistor R450 is grounded; pin 1 of USB switch chip U11 is connected to one end of resistor R451; pin 2 of USB switch chip U11 is connected to one end of resistor R452; pin 7 of USB switch chip U11 is connected to one end of resistor R453; pin 6 of USB switch chip U11 is connected to one end of resistor R454; pin 8 of USB switch chip U11 is connected to one end of resistor R95, the other end of resistor R95 is grounded; and the other end of resistor R451 is connected to the other ends of resistors R452, R453, and R454 respectively.

4. The carrier board compatible with NVIDIA core boards according to claim 1, characterized in that, The camera serial interface connector circuit includes: pin 1 of FFC&FPC connector J20 is connected to one end of capacitor C106; pin 5 of FFC&FPC connector J20 is connected to one end of diode D35; pin 6 of FFC&FPC connector J20 is connected to one end of diode D34 and pin 4 of single-supply single-buffer gate chip U57, pin 8 of FFC&FPC connector J20 is connected to one end of diode D33; pin 9 of FFC&FPC connector J20 is connected to one end of diode D32; and pin 11 of FFC&FPC connector J20 is connected to one end of diode D31. Pin 12 of FFC&FPC connector J20 is connected to one end of diode D30; pin 14 of FFC&FPC connector J20 is connected to one end of diode D29; pin 15 of FFC&FPC connector J20 is connected to one end of diode D28; pin 17 of FFC&FPC connector J20 is connected to one end of diode D27; pin 18 of FFC&FPC connector J20 is connected to one end of diode D26; pin 20 of FFC&FPC connector J20 is connected to one end of diode D25; and pin 6 of FFC&FPC connector J21 is connected to one end of diode D24.

5. The carrier board compatible with NVIDIA core boards according to claim 1, characterized in that, The DC debounce soft-start circuit includes: the drain of the field-effect transistor Q23 is connected to the emitter of the transistor Q24A; the collector of the transistor Q24A is connected to the base of the transistor Q24A, one end of the resistor R179, and the base of the transistor Q24B; the other end of the resistor R179 is connected to one end of the resistor R180 and grounded; the other end of the resistor R180 is connected to the gate of the field-effect transistor Q23 and the collector of the transistor Q24B; and the source of the field-effect transistor Q23 is connected to the emitter of the transistor Q24B.

6. The carrier board compatible with NVIDIA core boards according to claim 1, characterized in that, The core board configuration circuit includes: pin 1 of the serial EEPROM chip U17 is connected to one end of resistor R131 and one end of resistor R132 respectively; pin 2 of the serial EEPROM chip U17 is connected to one end of resistor R129 and one end of resistor R130 respectively; pin 3 of the serial EEPROM chip U17 is connected to one end of resistor R127 and one end of resistor R128 respectively; pin 7 of the serial EEPROM chip U17 is connected to one end of resistor R126; pin 8 of the serial EEPROM chip U17 is connected to one end of capacitor C134; and the other ends of resistors R126, R128, R130, R132, and C134 are all grounded.

7. The carrier board compatible with NVIDIA core boards according to claim 1, characterized in that, The fan interface circuit includes: pin 1 of the single-bit dual-power bus transceiver chip U15 is connected to one end of capacitor C430; pin 3 of the single-bit dual-power bus transceiver chip U15 is connected to one end of resistor R122 and one end of resistor R543 respectively; pin 4 of the single-bit dual-power bus transceiver chip U15 is connected to one end of resistor R119; pin 6 of the single-bit dual-power bus transceiver chip U15 is connected to one end of capacitor C429; the other end of capacitor C429, the other end of resistor R119, and capacitor C... The other end of resistor 430 and the other end of resistor R122 are grounded. The other end of resistor R543 is connected to pin 4 of field-effect transistor chip J13. Pin 2 of field-effect transistor chip J13 is connected to one end of resistor R124 and one end of capacitor C132 respectively. The other end of resistor R124 is connected to pin 3 of field-effect transistor chip J13 and the drain of field-effect transistor Q20 respectively. The gate of field-effect transistor Q20 is connected to one end of resistor R123. The other end of resistor R123 is connected to the source of field-effect transistor Q20.

8. The carrier board compatible with NVIDIA core boards according to claim 1, characterized in that, The serial port circuit includes: pin 1 of level conversion chip U16 is connected to one end of capacitor C129, pin 5 of level conversion chip U16 is connected to one end of resistor R120, pin 7 of level conversion chip U16 is connected to one end of resistor R125, and pin 8 of level conversion chip U16 is connected to one end of capacitor C130 and one end of resistor R125 respectively.

9. The carrier board compatible with NVIDIA core boards according to claim 1, characterized in that, The M.2 interface monitoring circuit includes: pin 4 of buffer chip U56 is connected to one end of resistor R518, pin 5 of buffer chip U56 is connected to one end of capacitor C392, and pin 2 of buffer chip U56 is connected to one end of resistor R497, one end of resistor R512, one end of resistor R513, and one end of resistor R514, respectively.

10. The carrier board compatible with NVIDIA core boards according to any one of claims 1 to 9, characterized in that, The PoE Gigabit Ethernet circuit includes: pin 10 of Ethernet connector chip J1 is connected to one end of capacitor C37; pin 11 of Ethernet connector chip J1 is connected to one end of resistor R36; pin 14 of Ethernet connector chip J1 is connected to one end of resistor R37; pin 12 of Ethernet connector chip J1 is connected to one end of resistor R146; pin 13 of Ethernet connector chip J1 is connected to one end of resistor R147; pin 1 of Ethernet connector chip J1 is connected to one end of resistor R35 and one end of capacitor C136 respectively; and the other end of resistor R36 is connected to the other end of resistor R37 and the other end of resistor R35 respectively.

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