Memory chip capable of switching read modes
By introducing switchable single-ended and differential read reference circuits into the memory chip, the problem of high scrap rate of resistive memory chips caused by process fluctuations has been solved, achieving higher production efficiency and lower production costs.
Patent Information
- Application Number
- CN202520613434.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2026-02-24
- Estimated Expiration
- 2035-04-02
AI Technical Summary
The high scrap rate of resistive memory chips in existing technologies leads to increased production costs, mainly due to read window failures caused by process fluctuations.
Design a memory chip with switchable read mode, including a write driver component, a read reference circuit and a resistive memory array. It adopts a switching mechanism between single-ended reference circuit and differential reference circuit to dynamically adjust the read mode according to process fluctuations, so as to avoid waste caused by the reference resistor deviating from the read window.
By switching the read reference circuit, the scrap rate caused by process fluctuations was reduced, production efficiency and the yield of memory chips were improved, and production costs were reduced.
Smart Images
Figure CN223941553U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuits, and in particular to a memory chip with switchable read modes. Background Technology
[0002] With technological advancements, the demand for data storage is increasing. Resistive memory is a new type of non-volatile storage technology. It combines the advantages of traditional random access memory (RAM) and flash memory, offering higher storage density and faster data access speeds.
[0003] Reading information from resistive memory depends on the difference between the high-resistance state resistor Rh and the low-resistance state resistor Rl. To distinguish between "1" and "0", a suitable reference resistor needs to be determined to accurately determine the stored information in the bit. The reference resistor is usually chosen between the distribution curves of Rh and Rl. There are two modes for reading resistive memory. One mode uses a separate reference resistor as a reference for information reading, called single-ended structure. Single-ended structure can save array area, but the high and low temperature windows are poor, and read window failure is prone to occur. The other mode uses other bits in the resistive memory as references, and the state of the reference bit is opposite to the state of the bit storing information, called differential structure. Differential structure has a larger read window, and the high and low temperature read windows are better.
[0004] Normally, the read circuit of a chip uses a single-ended structure, with an optimal reference resistor set before the chip leaves the factory. However, due to process variations, the read window between the Rh and Rl distribution curves of some chips within the wafer may be small, or the set optimal reference resistor may not be within the read window of that chip. This will result in a certain number of unusable bits. If the proportion of unusable bits is too large, the chip can only be considered a failure and classified as a scrap chip, causing huge losses and significantly increasing the production cost of memory chips.
[0005] Therefore, how to reduce the scrap rate in the memory chip manufacturing process, thereby lowering production costs, is a problem that urgently needs to be solved by those skilled in the art. Utility Model Content
[0006] The purpose of this invention is to provide a memory chip with switchable read modes to solve the problem of high production costs caused by excessively high scrap rates in the prior art.
[0007] To solve the above-mentioned technical problems, this utility model provides a memory chip with switchable read mode, including a write drive component, a read reference circuit and a resistive memory array;
[0008] The resistive memory array includes multiple resistive memory cells arranged in an array and multiple bit lines and source lines arranged in a cross pattern. The resistive memory cells are electrically connected to the bit lines and source lines.
[0009] The write driver component is electrically connected to the resistive memory array and is used to write to the resistive memory cell;
[0010] The read reference circuit includes a single-ended reference circuit and a differential reference circuit. The read reference circuit reads the resistive memory cell through the single-ended reference circuit or the differential reference circuit.
[0011] Optionally, in the switchable read mode memory chip, the resistive memory array has a one-bit width.
[0012] Optionally, in the switchable read mode memory chip, the read reference circuit reads the resistive memory cell through the single-ended reference circuit;
[0013] The write driver component includes a first driver module; the first driver module is used to write all the resistive memory cells in the resistive memory array.
[0014] Optionally, in the switchable read mode memory chip, the read reference circuit reads the resistive memory cell through the differential reference circuit;
[0015] The write driver component includes a first driver module and a second driver module;
[0016] The first driving module is used to write all the resistive information storage cells in the resistive storage array;
[0017] The second driving module is used to write to all the reference resistive memory cells in the resistive memory array.
[0018] Optionally, in the switchable read mode memory chip, in the resistive memory array, two adjacent bit lines share the same address;
[0019] In the direction of the bit line arrangement, two adjacent resistive memory cells form a differential pair.
[0020] Optionally, in the aforementioned switchable read mode memory chip, the resistive memory array has a two-bit width;
[0021] The resistive memory array includes a first array and a second array.
[0022] Optionally, in the switchable read mode memory chip, the read reference circuit reads the resistive memory cell through the single-ended reference circuit;
[0023] The write driver component includes a third driver module; the third driver module is used to write resistive memory cells in the first array and resistive memory cells in the second array.
[0024] Optionally, in the switchable read mode memory chip, the read reference circuit reads the resistive memory cell through the differential reference circuit;
[0025] The write driver component includes a third driver module and a fourth driver module;
[0026] The third driving module is used to write to the resistive storage cells in the first array; the resistive storage cells in the first array are resistive information storage cells.
[0027] The fourth driving module is used to write to the resistive memory cell in the second array; the resistive memory cell in the second array is a reference resistive memory cell.
[0028] Optionally, in the memory chip with switchable read mode, the address decoding arrangement of the first array and the second array is the same, and the resistive memory cells with the same address in the first array and the second array form a differential pair.
[0029] Optionally, in the switchable read mode memory chip, the resistive memory cell is a magnetic tunnel junction cell.
[0030] Optionally, in the aforementioned switchable read mode memory chip, the resistive memory cell is a magnetic tunnel junction cell;
[0031] And / or, the read reference circuit switches between reading the resistive memory cell via the single-ended reference circuit and reading the resistive memory cell via the differential reference circuit through a register or bonding process.
[0032] The present invention provides a switchable read mode memory chip, comprising a write driver component, a read reference circuit, and a resistive memory array; the resistive memory array includes multiple array-arranged resistive memory cells and multiple cross-arranged bit lines and source lines, wherein the resistive memory cells are electrically connected to the bit lines and source lines; the write driver component is electrically connected to the resistive memory array and is used to write to the resistive memory cells; the read reference circuit includes a single-ended reference circuit and a differential reference circuit, wherein the read reference circuit reads the resistive memory cells through the single-ended reference circuit or the differential reference circuit. In this invention, two switchable read reference circuits are provided in the memory chip. When the chip is tested using a single-ended reference circuit with a reference resistor, and the proportion of failed resistive memory cells is too large due to process fluctuations causing the reference resistor to be outside the read window of the chip, the single-ended reference circuit can be abandoned, and the read reference circuit of the memory chip can be switched to a differential reference circuit in time. This transforms the defective chip in the single-ended reference circuit mode into a qualified memory chip in the differential reference circuit mode, which can effectively avoid yield loss caused by process fluctuations and improve production efficiency. Attached Figure Description
[0033] To more clearly illustrate the technical solutions of the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 A schematic diagram of a read reference circuit structure for a specific embodiment of the switchable read mode memory chip provided by this utility model;
[0035] Figure 2 A schematic diagram of a read reference circuit structure for another specific embodiment of the switchable read mode memory chip provided by this utility model;
[0036] Figure 3 A schematic diagram of a resistive memory array structure of a specific embodiment of the memory chip with switchable read mode provided by this utility model;
[0037] Figure 4 A schematic diagram of the write driver component structure of a specific embodiment of the switchable read mode storage chip provided by this utility model;
[0038] Figure 5 A schematic diagram of a resistive memory array structure for another specific embodiment of the switchable read mode memory chip provided by this utility model;
[0039] Figure 6 A schematic diagram of a resistive memory array structure for another specific embodiment of the switchable read mode memory chip provided by this utility model.
[0040] Figure 7 A schematic diagram of a resistive memory array structure of another specific embodiment of the memory chip with switchable read mode provided by this utility model.
[0041] The figure includes 10-read reference circuit, 20-resistive memory array, 21-resistive memory cell, 20A-first array, 20B-second array, 21A-differential pair, 30-write driver component, 31-first driver module, and 32-second driver module. Detailed Implementation
[0042] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0043] The core of this invention is to provide a memory chip with switchable read modes, and a schematic diagram of one specific embodiment is shown below. Figures 1 to 5 As shown, this is referred to as Specific Implementation Method 1, which includes a write drive component 30, a read reference circuit 10, and a resistive storage array 20.
[0044] The resistive memory array 20 includes a plurality of resistive memory cells 21 arranged in an array and a plurality of bit lines and source lines arranged in a cross pattern. The resistive memory cells 21 are electrically connected to the bit lines and source lines.
[0045] The write drive component 30 is electrically connected to the resistive memory array 20 and is used to write to the resistive memory cell 21;
[0046] The read reference circuit 10 includes a single-ended reference circuit and a differential reference circuit. The read reference circuit 10 reads the resistive storage cell 21 through the single-ended reference circuit or the differential reference circuit.
[0047] The driving component includes a driving unit. The memory chip performs writing to the resistive memory cell 21 in the resistive memory array 20 through the driving unit. The driving unit can be single or multiple, and this utility model does not limit it.
[0048] A schematic diagram of the read reference circuit 10 is shown below. Figure 1 and Figure 2 As shown, when the memory chip operates in single-ended reference mode, Figure 1 The circuitry highlighted by the dashed line is operational when the memory chip is operating in differential reference mode. Figure 2 The part of the circuit highlighted by the dashed line is in operation. Rint in the figure represents the reference resistor in the single-ended reference circuit, and SA represents the current amplifier.
[0049] In one specific implementation, the resistive memory array 20 has a one-bit width.
[0050] In other words, the resistive memory array 20 in this specific embodiment is a single array composed of adjacent bit lines and source lines, which can be referred to as Figure 3The resistive memory array 20 with a bit width has a simple structure, low manufacturing process requirements, and low production cost. Of course, resistive memory arrays 20 with other bit widths can also be set, and this utility model does not limit it.
[0051] Furthermore, the read reference circuit 10 reads the resistive storage cell 21 through the single-ended reference circuit;
[0052] The write drive component 30 includes a first drive module 31; the first drive module 31 is used to write all the resistive memory cells 21 in the resistive memory array 20.
[0053] In this preferred embodiment, the read reference circuit 10 reads the resistive memory cell 21 through the single-ended reference circuit. This can also be considered as the memory chip operating in single-ended reference mode. The write drive component 30 is configured with only one drive module, meaning the first drive module 31 writes to all the resistive memory cells 21 in the resistive memory array 20, which significantly reduces production costs. (See reference...) Figure 3 , Figure 3 The diagram shows the array structure of the memory chip operating in single-ended reference mode, with each resistive memory cell 21 being an independent memory cell for decoding. This array has n+2 BL (bit lines) and m+1 WL (word lines), and the chip capacity is (n+2)*(m+1) bits.
[0054] In another specific implementation, the read reference circuit 10 reads the resistive storage cell 21 through the differential reference circuit;
[0055] The write driver component 30 includes a first driver module 31 and a second driver module 32;
[0056] The first driving module 31 is used to write all the resistive information storage cells 21 in the resistive storage array 20;
[0057] The second driving module 32 is used to write all the reference resistive memory cells 21 in the resistive memory array 20.
[0058] Unlike the single-ended reference mode of the one-bit resistive memory array 20 described earlier, in this specific embodiment, the read reference circuit 10 reads the resistive memory cells 21 through the differential reference circuit. In other words, the memory chip operates in differential reference mode. Differential reference mode requires half of the resistive memory cells 21 (bits) to be used for actual data storage, while the other half serves as a reference. This halves the actual amount of data that the resistive memory array 20 can store, but it is still usable and has higher read accuracy. In this invention, the resistive memory cells 21 used for actual data storage are called resistive information storage cells 21, and the resistive memory cells 21 used as references are called reference resistive memory cells 21. It is easy to see that when the memory chip operates in single-ended reference mode, all resistive memory cells 21 are resistive information storage cells 21; when operating in differential reference mode, half of the resistive memory cells 21 are resistive information storage cells 21, and the other half are reference resistive memory cells 21.
[0059] Please see the schematic diagram of the write driver component 30. Figure 4 , Figure 4 The document provides two driver modules, namely the first driver module 31 and the second driver module 32. The output terminals of the first driver module 31 are connected to EN and Din respectively, and the output terminals of the second driver module 32 are connected to EN_B and Din respectively.
[0060] The first driving module 31 and the second driving module 32 can simultaneously write to the resistive memory array 20 to improve writing efficiency, or they can write in a time-division manner. The specific situation can be adjusted, and this utility model does not limit it.
[0061] Furthermore, in the resistive memory array 20, two adjacent bit lines share the same address;
[0062] In the direction of the bit line arrangement, two adjacent resistive memory cells 21 form a differential pair 21A.
[0063] Please refer to Figure 5 In this preferred embodiment, the resistive memory cell 21 storing data and the resistive memory cell 21 serving as a reference actually use the same address, and the resistive memory cells 21 on two adjacent bit lines are formed into a differential pair 21A. This can greatly improve the speed of fault determination after a problem occurs, improve troubleshooting efficiency and the working stability of the memory chip. (See reference...) Figure 5 , Figure 5 The difference pair 21A is outlined with a dashed line.
[0064] In one specific embodiment, both the first driving module 31 and the second driving module 32 operate simultaneously. The first driving module 31 is responsible for writing to the resistive information storage unit 21, and the second driving module 32 is responsible for writing to the reference resistive storage unit 21. At this time, the address decoding (see...) Figure 5 )compared to Figure 3 There will also be some changes; two adjacent BLs will be compiled to the same address, and the bit line where the resistive information storage cell 21 is located will be named BL. <n>The bit line containing the reference resistive memory cell 21 is named BL_B. <n>Two adjacent resistive memory cells 21 in the bit line arrangement direction form a differential pair 21A, which stores one bit of information. At this time, the number of BLs decoded is halved to (n+2) / 2, while the number of WLs remains m+1. The available capacity of the chip is now (n+2)*(m+1) / 2, which is halved.
[0065] In addition, the resistive storage unit 21 is a magnetic tunnel junction unit.
[0066] The magnetic tunnel junction unit is a novel memory with great potential. It has the advantages of simple circuit design, fast read and write speed, unlimited erase and write cycles, and no data loss when power is off. Of course, other types of resistive memory units 21 can also be selected according to the actual situation. This utility model will not be described in detail here.
[0067] Furthermore, the read reference circuit 10 switches between reading the resistive memory cell 21 via the single-ended reference circuit and reading the resistive memory cell 21 via the differential reference circuit through a register or bonding process.
[0068] Registers can be added to the memory chip to control which circuit in the read reference circuit 10 is connected to the resistive memory array 20. This method is simple to operate and highly automated. On the other hand, the type of single-pass circuit used in the read reference circuit 10 can be changed through the bonding process to change the reference mode of the memory chip at a lower cost.
[0069] The present invention provides a switchable read mode memory chip, comprising a write driver component 30, a read reference circuit 10, and a resistive memory array 20; the resistive memory array 20 includes a plurality of arrayed resistive memory cells 21 and a plurality of cross-arranged bit lines and source lines, wherein the resistive memory cells 21 are electrically connected to the bit lines and source lines; the write driver component 30 is electrically connected to the resistive memory array 20 and is used to write to the resistive memory cells 21; the read reference circuit 10 includes a single-ended reference circuit and a differential reference circuit, wherein the read reference circuit 10 reads the resistive memory cells 21 through the single-ended reference circuit or the differential reference circuit. In this invention, two switchable read reference circuits 10 are provided in the memory chip. When the chip is tested using a single-ended reference circuit with a reference resistor, and the proportion of failed resistive memory cells 21 is too large due to process fluctuations causing the reference resistor to be outside the read window of the chip, the single-ended reference circuit can be abandoned, and the read reference circuit 10 of the memory chip can be switched to a differential reference circuit in time. This transforms the defective chip in the single-ended reference circuit mode into a qualified memory chip in the differential reference circuit mode, which can effectively avoid yield loss caused by process fluctuations and improve production efficiency.
[0070] Based on the first specific implementation method, the resistive memory array 20 is further improved to obtain the second specific implementation method, the structural schematic diagram of which is shown below. Figures 6 to 7 As shown, it includes a write driver component 30, a read reference circuit 10, and a resistive memory array 20;
[0071] The resistive memory array 20 includes a plurality of resistive memory cells 21 arranged in an array and a plurality of bit lines and source lines arranged in a cross pattern. The resistive memory cells 21 are electrically connected to the bit lines and source lines.
[0072] The write drive component 30 is electrically connected to the resistive memory array 20 and is used to write to the resistive memory cell 21;
[0073] The read reference circuit 10 includes a single-ended reference circuit and a differential reference circuit. The read reference circuit 10 reads the resistive memory cell 21 through the single-ended reference circuit or the differential reference circuit.
[0074] The resistive memory array 20 has a two-bit width;
[0075] The resistive memory array 20 includes a first array 20A and a second array 20B.
[0076] The difference between this specific embodiment and the above specific embodiment is that the resistive memory array 20 is determined to have a two-bit width in this specific embodiment. The rest of the structure is the same as the above specific embodiment, and will not be described in detail here.
[0077] In this specific embodiment, the resistive storage array 20 is divided into a first array 20A and a second array 20B, that is, the resistive storage array 20 is isolated into two parts, to avoid circuit failure causing all resistive storage cells 21 to fail, thereby improving data security.
[0078] In a preferred embodiment, the read reference circuit 10 reads the resistive storage cell 21 through the single-ended reference circuit;
[0079] The write drive component 30 includes a third drive module; the third drive module is used to write resistive memory cells 21 in the first array 20A and resistive memory cells 21 in the second array 20B.
[0080] In this preferred embodiment, the resistive memory array 20 with a two-bit width operates in single-ended reference mode. All resistive memory cells 21 in the first array 20A and the second array 20B serve as resistive information storage cells 21, with a physical isolation layer between them—that is, the isolation between the second array 20B and the first array 20A. This significantly improves data security while ensuring the maximum amount of data stored in the memory chip. See the array structure diagram below. Figure 6 This array has a two-bit width and uses two current amplifiers (SAs) for decoding. Each SA has a decoding array range of (n+1)*(m+1) resistive memory cells 21, resulting in a chip capacity of 2*(n+1)*(m+1) bits. The structure diagram of this two-bit wide array operating in single-ended reference mode is shown below. Figure 6 As shown in the figure, DEC is the decoder.
[0081] In another specific implementation, the read reference circuit 10 reads the resistive storage cell 21 through the differential reference circuit;
[0082] The write driver component 30 includes a third driver module and a fourth driver module;
[0083] The third driving module is used to write to the resistive storage unit 21 in the first array 20A; the resistive storage unit 21 in the first array 20A is a resistive information storage unit 21;
[0084] The fourth driving module is used to write to the resistive memory cell 21 in the second array 20B; the resistive memory cell 21 in the second array 20B is a reference resistive memory cell 21.
[0085] In this preferred embodiment, two driving modules are also provided, namely the third driving module and the fourth driving module. The two driving modules write to the first array 20A and the second array 20B respectively, which can greatly improve the writing efficiency and avoid the situation where all resistive memory cells 21 become unwriteable after the failure of a single driving module. The structural diagram of the third driving module and the fourth driving module in the driving assembly can be found in the following diagram. Figure 4 The structural diagrams of the first driving module 31 and the second driving module 32 are shown below and will not be described in detail here.
[0086] Furthermore, the address decoding arrangement of the first array 20A and the second array 20B is the same, and the resistive memory cells 21 with the same address in the first array 20A and the second array 20B form a differential pair 21A. Please refer to... Figure 7 The address decoding settings of the first array 20A and the second array 20B are arranged in the same way, and the resistive memory cells 21 with the same address in the first array 20A and the second array 20B form a differential pair 21A (in Figure 7 (Extended by a dashed line) can effectively improve fault location when errors occur and improve maintenance efficiency.
[0087] As a specific embodiment, in differential structure mode, both the third driving module and the fourth driving module operate simultaneously. The third driving module is responsible for writing to the resistive memory cell 21 of the first array 20A, and the fourth driving module is responsible for writing to the resistive memory cell 21 of the second array 20B. At this time, the address decoding method remains unchanged, the chip's bit width is halved, and only one SA operates. Figure 7 Two resistive memory cells 21 with the same address decoding form a differential pair 21A. At this time, the chip capacity is (n+1)*(m+1) bits, which is halved.
[0088] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0089] It should be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0090] The switchable read mode memory chip provided by this utility model has been described in detail above. Specific examples have been used to illustrate the principle and implementation of this utility model. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core idea of this utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made to this utility model without departing from the principle of this utility model, and these improvements and modifications also fall within the protection scope of this utility model.< / n> < / n>
Claims
1. A memory chip with switchable read modes, characterized in that, This includes write driver components, read reference circuitry, and resistive memory array; The resistive memory array includes multiple resistive memory cells arranged in an array and multiple bit lines and source lines arranged in a cross pattern. The resistive memory cells are electrically connected to the bit lines and source lines. The write driver component is electrically connected to the resistive memory array and is used to write to the resistive memory cell; The read reference circuit includes a single-ended reference circuit and a differential reference circuit. The read reference circuit reads the resistive memory cell through the single-ended reference circuit or the differential reference circuit.
2. The memory chip with switchable read mode as described in claim 1, characterized in that, The resistive memory array has a one-bit width.
3. The memory chip with switchable read mode as described in claim 2, characterized in that, The read reference circuit reads the resistive memory cell through the single-ended reference circuit; The write driver component includes a first driver module; the first driver module is used to write all the resistive memory cells in the resistive memory array.
4. The memory chip with switchable read mode as described in claim 2, characterized in that, The read reference circuit reads the resistive memory cell through the differential reference circuit; The write driver component includes a first driver module and a second driver module; The first driving module is used to write all the resistive information storage cells in the resistive storage array; The second driving module is used to write to all the reference resistive memory cells in the resistive memory array.
5. The memory chip with switchable read mode as described in claim 4, characterized in that, In the resistive memory array, two adjacent bit lines share the same address; In the direction of the bit line arrangement, two adjacent resistive memory cells form a differential pair.
6. The memory chip with switchable read mode as described in claim 1, characterized in that, The resistive memory array has a two-bit width; The resistive memory array includes a first array and a second array.
7. The memory chip with switchable read mode as described in claim 6, characterized in that, The read reference circuit reads the resistive memory cell through the single-ended reference circuit; The write driver component includes a third driver module; the third driver module is used to write resistive memory cells in the first array and resistive memory cells in the second array.
8. The memory chip with switchable read mode as described in claim 6, characterized in that, The read reference circuit reads the resistive memory cell through the differential reference circuit; The write driver component includes a third driver module and a fourth driver module; The third driving module is used to write to the resistive storage cells in the first array; the resistive storage cells in the first array are resistive information storage cells. The fourth driving module is used to write to the resistive memory cell in the second array; the resistive memory cell in the second array is a reference resistive memory cell.
9. The memory chip with switchable read mode as described in claim 8, characterized in that, The first array and the second array have the same address decoding arrangement, and the resistive memory cells with the same address in the first array and the second array form a differential pair.
10. The memory chip with switchable read mode as described in claim 1, characterized in that, The resistive storage unit is a magnetic tunnel junction unit; And / or, the read reference circuit switches between reading the resistive memory cell via the single-ended reference circuit and reading the resistive memory cell via the differential reference circuit through a register or bonding process.