Standard unit test structure
By dividing the standard unit into M modules and matching the number of PADs, the problem of not being able to directly connect complex standard units for testing in the prior art is solved, realizing efficient testing in a real physical environment and improving testing accuracy and efficiency.
Patent Information
- Application Number
- CN202520101763.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-16
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2035-01-16
AI Technical Summary
Existing technologies cannot directly characterize the process conditions of complex standard cell structures in actual customer chips, especially under the limitations of the number of PADs and metal layers, making it difficult to conduct tests.
A standard unit test structure is provided, which divides the standard unit into M modules, each module containing Ni basic elements and multiple PADs. Exhaustive characterization is performed according to the actual physical environment to ensure that the number of PADs in each module matches the number of basic elements, thereby enabling direct outgoing testing of each basic element.
While keeping the front-end process layer of the product chip unchanged, direct connection testing of complex standard cells in a real physical environment was achieved, which improved testing efficiency and accuracy, and saved the product area of the test chip and the number of PADs.
Smart Images
Figure CN223955750U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of integrated circuit design technology, and in particular relates to a standard unit test structure. Background Technology
[0002] After the integrated circuit design is completed, the design data needs to be sent to the manufacturing plant for chip manufacturing. During chip manufacturing, the design team can use graphical tools to monitor and analyze process parameters. Typically, dedicated testkeys are designed to characterize the product's process level. This design / testing / analysis approach is quite mature, but it faces a problem: it cannot directly characterize the actual process conditions within the customer's chip. To understand the failure status and electrical characteristics of specific components in the product chip, a design approach and method are proposed: while keeping the front-end and middle-end process layers of the product chip unchanged, the interconnect layers and back-end process layers are modified into test structures to achieve a physical environment consistent with that of the product chip.
[0003] For advanced process nodes, the test structure is usually modified by directly connecting PADs (pads) to directly use the layout in the actual chip, and monitor the relevant structural parameters to characterize the actual chip process.
[0004] Due to the limitations of the number of PADs / metal layers in the direct-connect PAD method, complex standard cell structures such as registers are often difficult to directly connect for testing. However, these standard cells are frequently reused in actual circuits, making them a crucial part that directly impacts circuit performance. Utility Model Content
[0005] To address the problems of the prior art, this invention provides a standard unit test structure to enable direct testing of complex standard unit structures.
[0006] This utility model provides a standard unit test structure, including M modules. The M modules are divided according to the actual physical environment of the standard unit. The standard unit is exhaustively characterized by N basic elements in the M modules.
[0007] The i-th module includes N i Basic components and N i Multiple PADs directly connected to the aforementioned basic element; where 1≤i≤M, N1+...+N i ...+N M =N;
[0008] The number of the PADs in each of the modules matches the number of the basic element test PADs in the corresponding module, and is used for testing the respective basic elements through the PADs, and the maximum number of the PADs in each of the modules is not greater than the number of the pins supported by the tester probe card.
[0009] In some embodiments, the basic elements include one or more of transistors, resistors, capacitors, and diodes.
[0010] In some embodiments, the number of the PADs in the module ranges from 20 to 24.
[0011] In some embodiments, the basic elements are transistors, wherein,
[0012] When the test structure includes one of the modules, the module includes a first region having a plurality of first transistors and a second region having a plurality of second transistors; the first transistors and the second transistors are of different types and are respectively tested through direct connection to the PADs in the module.
[0013] In some embodiments, the plurality of first transistors in the first region share a base terminal, and the plurality of second transistors in the second region share a base terminal; the two base terminals are respectively tested through direct connection to different PADs in the first region and the second region.
[0014] In some embodiments, adjacent first transistors in the first region share a source terminal or a drain terminal, and adjacent second transistors in the second region share a source terminal or a drain terminal; the source terminals and the drain terminals are respectively tested through direct connection to different PADs in the module.
[0015] In some embodiments, the basic elements are transistors, wherein,
[0016] When the test structure includes at least two of the modules, different transistors in the same module are of the same type and are respectively tested through direct connection to the PADs in the corresponding module.
[0017] In some embodiments, different transistors in the same module share a base terminal, and the base terminal is tested through direct connection to the PADs in the corresponding module.
[0018] In some embodiments, when the test structure includes at least two of the modules, adjacent transistors in the same module share a source terminal or a drain terminal, and the source terminal or the drain terminal is respectively tested through direct connection to the PADs in the corresponding module.
[0019] In some embodiments, the standard cell includes N transistors, and the test structure includes a first module and a second module, wherein,
[0020] The first module comprises N1 first transistors and a plurality of PADs directly connected with the N1 first transistors, the N1 first transistors share a base terminal and adjacent two first transistors share a source terminal or a drain terminal, and the source terminal, the drain terminal, the gate terminal and the base terminal of the N1 first transistors are respectively connected to test through the PADs in the first module;
[0021] The second module comprises N2 second transistors and a plurality of PADs directly connected with the N2 second transistors, the N2 second transistors share a base terminal and adjacent two second transistors share a source terminal or a drain terminal, and the source terminal, the drain terminal, the gate terminal and the base terminal of the N2 second transistors are respectively connected to test through the PADs in the second module; wherein N1+N2=N.
[0022] The above standard unit test structure comprises M modules, the M modules are obtained by dividing the standard unit according to an actual physical environment, the standard unit is characterized by N basic elements in the M modules, the i-th module comprises N i basic elements and a plurality of PADs directly connected with the N i basic elements, the number of the PADs in each module matches the number of the basic elements in the corresponding module, and each basic element is connected to test through the PADs. In this way, all the basic elements in the standard unit can be characterized by the series and parallel connection in the actual physical environment, and each basic element is connected to test through the PADs in the M modules, so that the actual process of the entire complex structure of the standard unit can be characterized by the test results of different positions of the M modules through single or multiple probe card tests and data collection. BRIEF DESCRIPTION OF DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0024] Figure 1 The schematic diagram of the standard unit test structure provided in Embodiment Three of the present application.
[0025] Figure 2 The structural schematic diagram of the standard unit register provided in the present application.
[0026] Figure 3Provided by this utility model Figure 2 The test results of the standard unit test structure shown are illustrated. Figure 1 .
[0027] Figure 4 Provided by this utility model Figure 2 The test results of the standard unit test structure shown are illustrated. Figure 2 .
[0028] Figure 5 This is a schematic diagram of the standard unit test structure provided in Embodiment 1 of this utility model.
[0029] Figure 6 This is a schematic diagram of the standard unit test structure provided in Embodiment 2 of this utility model.
[0030] Figure 7 This is a schematic diagram of the standard unit test structure provided in Embodiment 3 of this utility model. Detailed Implementation
[0031] The foregoing and other technical contents, features, and effects of this utility model will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the scope of this utility model.
[0032] In integrated circuits, the standard cell library is the foundation of digital integrated circuit design. The standard cell library includes one or more standard cells and their corresponding layouts. A standard cell is a collection of pre-designed and verified basic logic gates and functional units. Each standard cell corresponds to a specific circuit device, and the layout is used to display the relevant information of that device. When designing integrated circuit (IC) chips, the required standard cells are simply retrieved from the standard cell library according to the circuit requirements. Automatic placement and routing then yield the corresponding circuit layout. The design is then performed based on this layout, simplifying the integrated circuit design process and improving chip design efficiency.
[0033] Typically, standard cells are reused extensively in actual chip circuits. To improve the yield and performance of product chips, it is necessary to modify the connection layer and the back-end process layer into a test structure (i.e., directly using the layout in the actual chip and modifying the test structure by directly connecting PADs) while keeping the front-end and middle-end process layers of the product chip unchanged) and extract relevant parameters of the standard cells for monitoring, thereby characterizing the process status of the actual chip.
[0034] However, for complex standard cell structures such as registers, it is difficult to directly interface out the test due to the limitations of the number of PADs / metal layers in the direct connection mode.
[0035] The utility model provides a standard cell test structure, can guarantee product chip front section process layer does not change the premise, through the key device direct connection to PAD, the connecting layer is transformed with rear section process layer to realize and product chip consistent physical environment, realize the direct connection test of product chip key device under real physical environment. Exemplarily, the standard cell test structure provided by the application can remove the CT (contact) connecting layer, M1 and upper metal layers in the product layout by layout extraction, and then select the standard cell in the product layout, and obtain the standard cell test structure by rearranging the rear section wiring, and then interface out the test.
[0036] Specifically, as shown in Figures 1-7 The standard cell test structure includes M modules divided according to the actual physical environment of the standard cell, that is, the M modules are obtained by block division according to the actual series-parallel connection mode of each basic element in the standard cell, the i-th module includes N i basic elements and a plurality of PADs directly connected to the N i basic elements, 1≤i≤M, N i ...+N M =N, so that the standard cell is exhaustively characterized by a total of N basic elements in the M modules.
[0037] It should be noted that the N basic elements can be all basic elements in the standard cell, or part of the basic elements selected for selective characterization test according to the test requirements, which is not limited in the application.
[0038] The number of PADs in each module matches the number of basic element test PADs in the corresponding module, and each basic element in the module is tested by the PAD. It can be understood that in the application, the number of PADs in each module is at least equal to the number of PADs required for testing the basic elements in the corresponding module, so that all N basic elements of the standard cell are tested by the PADs in each module.
[0039] The standard cell includes at least one of basic circuit devices commonly used in circuit design, such as logic gates, registers, selectors, full adders, PLLs (Phase-Locked Loop), and Tsensors (Temperature Sensor), and the basic element includes one or more of transistors, resistors, capacitors, and diodes. In actual application, the standard cell can be selected according to the test needs, and after the M modules are divided, all or selective characterization of the N basic elements of the standard cell is performed, which is not limited herein.
[0040] In the test, each basic element in the M modules of the standard cell test structure is connected through the PAD of the corresponding module, and the probe card of the test machine is physically connected to the PAD on the test structure through the probe. The test machine applies various test signals, including voltage, current, clock signal, etc., to the test structure through the probe card. The output signal of the test structure in response is transmitted back to the test machine through the probe card for data acquisition, so as to obtain the test results of each basic element at different positions, thereby characterizing the actual process of the entire complex structure. For example, Figure 2 The standard cell register contains 21 PMOS and 21 NMOS, and the test results obtained after characterization of the M modules of the standard cell test structure are as shown in Figure 3 and Figure 4
[0041] It can be understood that different test machines have different test interfaces and probe card designs. The number of PADs in the module is not only related to the probe card configuration and functional requirements of the test machine, but also closely related to the hardware design and parallel test capability of the test machine. Different probe cards support different numbers of pins, and different test machine types support different parallel test lines, which will directly affect the number configuration of the PADs in the module. In order to ensure that the test structure can be correctly connected and efficiently tested with the test machine, the number of PADs in the module needs to be matched with the test machine, that is, the maximum number of PADs in each module is not greater than the number of pins supported by the probe card of the test machine. Generally, the probe card can support 24 / 48 / 100 pin arrays, and for other types, different types of probe cards or custom can be selected.
[0042] Correspondingly, the number of PADs in the module can range from 20 to 24 to adapt to different probe card types. When the number of PADs in the module is small, more modules need to be divided according to the actual physical environment of the standard cell to represent a complex standard cell, and multiple pin testing is required due to the influence of probe card design and tester testing capacity. The time spent on needle lifting and needle moving increases in the test, which is not conducive to the improvement of test efficiency. When the number of PADs in the module is large, it cannot adapt to the mainstream tester probe card, and the customization cost is increased.
[0043] The standard cell test structure can be provided with one or more to cover different device types. For example, the transistors in the standard cell test structure can cover VT (Threshold Voltage), GL (Gate Length), GW (Gate Width), NDP (number of dummy poly), and other parameters, and the device types are as comprehensive as possible, so as to fully represent the process of the actual chip.
[0044] The above standard cell test structure can exhaustively represent all basic elements of the standard cell according to the series-parallel connection mode of the basic elements in the actual physical environment, and each basic element is connected to the test through the PAD by M modules, so that the actual division of the M modules of the standard cell can be tested by the probe card single or multiple pin testing, and the test results of the different positions of the M modules can be used to represent the actual process of the complex structure of the standard cell.
[0045] According to the complexity of the standard cell and the number of basic elements to be represented, the standard cell test structure can be composed of one or more modules. The following embodiments will be described in combination with the drawings.
[0046] Embodiment one
[0047] In this embodiment, the standard cell test structure includes one or more modules, and the transistors contained in each module can be several different types of transistors, and the several different types of transistors are dispersedly arranged.
[0048] Exemplarily, as shown in FIG. 1, the standard cell test structure includes two modules, and each module contains several different types of transistors, which are dispersedly arranged. Figure 5As shown, the standard unit test structure includes a first module (Module 1) and a second module (Module 2). The two modules are determined based on the actual physical environment of the standard unit, and each module includes 24 PADs. The standard unit (i.e., register) includes 7 Trs (Tr1-Tr7), of which 4 are NMOS and 3 are PMOS. The standard unit register is exhaustively characterized using the 7 Trs from the two modules. Each of the 7 Trs is tested by directly connecting to the PADs in its corresponding module. Specifically, the source (S), drain (D), gate (G), and base (B) terminals of each Tr (not shown in the figure) need to be tested by directly connecting to 4 PADs. In the first module, Tr1 connects PAD 1-PAD 4, Tr2 connects PAD 5-PAD 8, Tr3 connects PAD 9-PAD 12, Tr4 connects PAD 13-PAD 16, Tr5 connects PAD 17-PAD 20, and Tr6 connects PAD 21-PAD 24. In the second module, Tr7 connects PAD 1-PAD 4.
[0049] Example 2
[0050] In some embodiments, the standard unit test structure includes a module comprising a first region having a plurality of first transistors and a second region having a plurality of second transistors. The first and second transistors are of different types, and are respectively connected to a PAD directly in the module for testing.
[0051] Optionally, when the test structure includes one of the modules, a plurality of first transistors in the first region share a common base terminal, and a plurality of second transistors in the second region share a common base terminal; the two base terminals are respectively connected to different PADs in the first region and the second region for testing.
[0052] Optionally, when the test structure includes one of the modules, adjacent first transistors in the first region share a source or drain terminal, and adjacent second transistors in the second region share a source or drain terminal; the source terminal and the drain terminal are respectively connected to different PADs in the module for testing.
[0053] For example, such as Figure 6 As shown, the standard unit test structure includes one module, which is determined according to the actual physical environment of the standard unit. This module includes 24 PADs. The standard unit is a register, which includes 9 Tr (Transistors), of which 4 are PMOS (P1-P4) and 5 are NMOS (N1-N5). The standard unit register is exhaustively characterized by the 9 Trs in one module. The 9 Trs are tested by connecting the PADs directly to the first and second regions of the module.
[0054] Specifically,
[0055] 4 PMOS (P1-P4) are arranged in the first region of the module, the 4 PMOS (P1-P4) share a base end B and adjacent two PMOS share a source end S or a drain end D, the source end S, the drain end D, the gate end G and the base end B of the 4 PMOS (P1-P4) are respectively connected to the test through the direct connection of the PAD in the first region. In the first region, P1 is connected to PAD 2, PAD 3 and PAD 4, P2 is connected to PAD 4, PAD 5 and PAD 6, P3 is connected to PAD 6, PAD 7 and PAD 8, and P4 is connected to PAD 8, PAD 9 and PAD 10. PAD 1 can be connected to the base end B in the first region as a share body pad.
[0056] 5 NMOS (N1-N5) are arranged in the second region of the module, the 5 NMOS (N1-N5) share a base end B and adjacent two NMOS share a source end S or a drain end D, the source end S, the drain end D, the gate end G and the base end B of the 5 NMOS (N1-N5) are respectively connected to the test through the direct connection of the PAD in the second region. In the second region, PAD 11 can be connected to the base end B in the second region as a share body pad, N1 is connected to PAD 12, PAD 13 and PAD 14, N2 is connected to PAD 14, PAD 15 and PAD 16, N3 is connected to PAD 16, PAD 17 and PAD 18, N4 is connected to PAD 18, PAD 19 and PAD 20, and N5 is connected to PAD 20, PAD 21 and PAD 22.
[0057] Through the above embodiment, different types of transistors in the module are divided into different regions for separate test, the same type of transistors in the region can share a base end B, or adjacent transistors can share a source end S or a drain end D, thereby saving the test chip product area and the number of PADs, not only facilitating the re-layout of the back-end wire, but also dividing fewer modules in the same physical environment of the standard cell, concentrating various test signals for needle testing, and further improving the test efficiency.
[0058] Example three
[0059] As Figure 7As shown in the embodiment, when the standard cell test structure includes one module, the transistors contained in the module are the same type of transistors. For example, the module can include a plurality of first transistors, the first transistors being PMOS or NMOS, the plurality of first transistors sharing a base end B, and adjacent two first transistors sharing a source end S or a drain end D, the source end S, the drain end D, the gate end G and the base end B of the plurality of first transistors being respectively connected to the PAD in the module for testing.
[0060] As shown in the embodiment, when the standard cell test structure includes one module, the transistors contained in the module are the same type of transistors. For example, the module can include a plurality of first transistors, the first transistors being PMOS or NMOS, the plurality of first transistors sharing a base end B, and adjacent two first transistors sharing a source end S or a drain end D, the source end S, the drain end D, the gate end G and the base end B of the plurality of first transistors being respectively connected to the PAD in the module for testing. Figure 1 As shown in the embodiment, when the standard cell test structure includes one module, the transistors contained in the module are the same type of transistors. For example, the module can include a plurality of first transistors, the first transistors being PMOS or NMOS, the plurality of first transistors sharing a base end B, and adjacent two first transistors sharing a source end S or a drain end D, the source end S, the drain end D, the gate end G and the base end B of the plurality of first transistors being respectively connected to the PAD in the module for testing.
[0061] As shown in the embodiment, when the standard cell test structure includes one module, the transistors contained in the module are the same type of transistors. For example, the module can include a plurality of first transistors, the first transistors being PMOS or NMOS, the plurality of first transistors sharing a base end B, and adjacent two first transistors sharing a source end S or a drain end D, the source end S, the drain end D, the gate end G and the base end B of the plurality of first transistors being respectively connected to the PAD in the module for testing.
[0062] As shown in the embodiment, when the standard cell test structure includes one module, the transistors contained in the module are the same type of transistors. For example, the module can include a plurality of first transistors, the first transistors being PMOS or NMOS, the plurality of first transistors sharing a base end B, and adjacent two first transistors sharing a source end S or a drain end D, the source end S, the drain end D, the gate end G and the base end B of the plurality of first transistors being respectively connected to the PAD in the module for testing.
[0063] Figure 1 As shown in the embodiment, when the standard cell test structure includes one module, the transistors contained in the module are the same type of transistors. For example, the module can include a plurality of first transistors, the first transistors being PMOS or NMOS, the plurality of first transistors sharing a base end B, and adjacent two first transistors sharing a source end S or a drain end D, the source end S, the drain end D, the gate end G and the base end B of the plurality of first transistors being respectively connected to the PAD in the module for testing.
[0064] As shown in the embodiment, when the standard cell test structure includes one module, the transistors contained in the module are the same type of transistors. For example, the module can include a plurality of first transistors, the first transistors being PMOS or NMOS, the plurality of first transistors sharing a base end B, and adjacent two first transistors sharing a source end S or a drain end D, the source end S, the drain end D, the gate end G and the base end B of the plurality of first transistors being respectively connected to the PAD in the module for testing.
[0065] Through the above embodiment, the different transistor types in the standard cell are divided into different modules, and the same type of transistors in the module share the base end B, or adjacent transistors share the source end S or the drain end D, thereby saving the test chip product area and the PAD number, facilitating the re-layout back-end routing, and facilitating the concentrated application of various test signals for the needle test, and further improving the test efficiency.
[0066] The technical features of the above embodiments can be combined arbitrarily, and in order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the description.
[0067] The above embodiments only express several implementation manners of the utility model, the description is more specific and detailed, but it cannot be understood as the limitation of the utility model patent scope. It should be pointed out that for ordinary skilled person in the art, on the premise of not departing from the utility model concept, a number of modifications and improvements can be made, which belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent should be subject to the appended claims.
Claims
1. A standard cell test structure, characterized by, M modules are included, and the M modules are divided according to an actual physical environment of the standard cell, and the standard cell is exhaustively characterized by N basic elements in the M modules; wherein, The ith module includes N i basic elements and a plurality of PADs directly connected with the N i basic elements; wherein 1≤i≤M, N i 1+...+N M i=N. The number of the PADs in each module matches the number of the PADs for testing the basic elements in the corresponding module, and each PAD in each module is used for testing each basic element through the PAD, and the maximum number of the PADs in each module is not greater than the number of pins supported by a probe card of a tester.
2. The standard cell test structure of claim 1, wherein, The basic elements include one or more of a transistor, a resistor, a capacitor and a diode.
3. The standard cell test structure of claim 1, wherein, The number of the PADs in each module ranges from 20 to 24.
4. The standard cell test structure of claim 1, wherein, The basic elements are transistors, wherein, When the test structure includes one module, the module includes a first area with a plurality of first transistors and a second area with a plurality of second transistors, the first transistors and the second transistors are of different types, and are respectively tested through direct connection with PADs in the module.
5. The standard cell test structure of claim 4, wherein, The plurality of first transistors in the first area share a base terminal, and the plurality of second transistors in the second area share a base terminal, and the two base terminals are respectively tested through direct connection with different PADs in the first area and the second area.
6. The standard cell test structure of claim 4, wherein, Adjacent first transistors in the first area share a source terminal or a drain terminal, and adjacent second transistors in the second area share a source terminal or a drain terminal, and the source terminals and the drain terminals are respectively tested through direct connection with different PADs in the module.
7. The standard cell test structure of claim 1, wherein, The basic elements are transistors, wherein, When the test structure includes at least two modules, different transistors in the same module are of the same type, and are respectively tested through direct connection with PADs in the corresponding module.
8. The standard cell test structure of claim 7, wherein, Different transistors in the same module share a base terminal, and the base terminal is tested through direct connection with a PAD in the corresponding module.
9. The standard cell test structure of claim 7, wherein, When the test structure includes at least two modules, adjacent transistors in the same module share a source terminal or a drain terminal, and the source terminal or the drain terminal is respectively tested through direct connection with a PAD in the corresponding module.
10. The standard cell test structure of claim 7, wherein, The standard cell includes N transistors, and the test structure includes a first module and a second module, wherein, The first module includes N1 first transistors and a plurality of PADs directly connected to the N1 first transistors, the N1 first transistors share a base terminal, and adjacent two first transistors share a source terminal or a drain terminal, and the source terminals, the drain terminals, the gate terminals and the base terminals of the N1 first transistors are respectively tested through direct connection with PADs in the first module; The second module comprises N2 second transistors and a plurality of PADs directly connected with the N2 second transistors, the N2 second transistors share a base end, and adjacent two second transistors share a source end or a drain end, and the source end, the drain end, the gate end and the base end of the N2 second transistors are respectively connected out for testing through the PADs in the second module; wherein N1+N2=N.