Product AI generation type design system for additive manufacturing

Abstract

The utility model relates to the technical field of additive manufacturing, in particular to an additive manufacturing oriented product AI creation type design system which is composed of a multi-channel sampling circuit, a synchronous control circuit, a data caching circuit, a communication circuit and a power supply circuit. The multi-channel sampling circuit is provided with three independent sampling channels, each channel comprises a signal conditioning circuit and an analog-to-digital conversion chip, and input signals can be preprocessed. The synchronous control circuit comprises a crystal oscillator circuit, a phase-locked loop circuit and a clock distribution chip, and sampling synchronism is guaranteed. The data cache circuit is used for separating and marking the data insertion layer to facilitate data management; the communication circuit guarantees signal anti-interference and stable transmission; the power supply circuit outputs voltages of different specifications through the voltage stabilizing chip set to meet the power supply requirements of the chips. According to the system, accurate acquisition, synchronous processing and stable transmission of multi-dimensional signals can be realized, the requirements of additive manufacturing AI generation type design on high-quality data are accurately matched, and the operation reliability and the data utilization efficiency of the system are improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to additive manufacturing technical field, concretely relates to product AI creative design system for additive manufacturing. BACKGROUND

[0002] As one of the core technologies of the fourth industrial revolution, additive manufacturing technology has been widely used in aerospace, medical devices, automobile manufacturing and other fields. In the additive manufacturing process, it is necessary to monitor the temperature field distribution, laser power change, molten pool morphology characteristics and other multi-dimensional physical parameters in real time to ensure the stability of product quality. The traditional manual experience parameter adjustment method cannot meet the precision manufacturing demand of complex structural parts, and the AI creative design can intelligently optimize the process parameters, predict the defect position and realize self-adaptive control through the training of neural network model based on massive process data. However, the training effect of the AI model is highly dependent on the quality and integrity of the input data. The temperature signal changes fast in the additive manufacturing process, which requires high sampling rate, and the strain signal is weak, which requires high resolution, and the layer switching requires accurate timestamp marking. Under this background, developing a special acquisition system that can synchronously acquire multiple types of sensor signals, maintain clock consistency, automatically label manufacturing layer information and efficiently transmit massive data has become a key technical basis for promoting the intelligentization of additive manufacturing.

[0003] The existing additive manufacturing data acquisition scheme usually adopts a general data acquisition card, which has the following problems: 1. Single channel or simple parallel sampling method is usually used, which cannot configure differentiated sampling precision and frequency according to the characteristics of different physical quantities, resulting in distortion of fast-changing signals or redundancy of slow-changing signals. 2. Independent clock sources are used for each sampling channel, lacking a hardware-level synchronization mechanism, and there is a microsecond-level time offset between different sensor data, affecting the accuracy of multi-physical field coupling analysis. 3. There is a lack of layer separation markers in the data stream, making it difficult to establish an accurate mapping relationship from process parameters to single-layer quality control during AI training, and manual post-processing is required to align the timestamps. These problems restrict the construction accuracy of the digital twin model of the additive manufacturing process, and an integrated and highly reliable special data acquisition solution is urgently needed. UTILITY MODEL CONTENT

[0004] The utility model aims at providing product AI creative design system for additive manufacturing to solve the problems of asynchronous multi-channel signal sampling of the data acquisition card and the inability to organize data by layers in the prior art.

[0005] To solve the above technical problems, the utility model adopts the technical scheme of comprising: a multi-channel sampling circuit comprising three independent sampling channel units; each sampling channel unit comprises a signal conditioning circuit and an analog-to-digital conversion chip, the signal conditioning circuit comprises an input interface connector, a preamplifier, a filter capacitor and a conditioning resistor, the output end of the preamplifier is connected to the analog input end of the analog-to-digital conversion chip through the filter capacitor;

[0006] The synchronous control circuit comprises a crystal circuit and a clock distribution chip; an output end of the crystal circuit is connected to a clock input end of the clock distribution chip; the clock distribution chip has three clock output ends, and each clock output end is connected to a clock input pin of an analog-to-digital conversion chip of a corresponding sampling channel unit;

[0007] The data buffer circuit comprises a FIFO storage chip and an address controller; a data input end of the FIFO storage chip is connected to digital output pins of the analog-to-digital conversion chips in parallel through a data bus; and an output end of the address controller is connected to an address input end of the FIFO storage chip.

[0008] The communication circuit comprises a communication protocol chip and an interface connector; a data end of the communication protocol chip is connected to a data output end of the FIFO storage chip.

[0009] According to the technical scheme, the signal conditioning circuit further comprises:

[0010] The differential amplifier chip has a first input terminal and a second input terminal; the first input terminal is connected to a positive input pin of the differential amplifier chip through a first input resistor; and the second input terminal is connected to a negative input pin of the differential amplifier chip through a second input resistor.

[0011] A common-mode filter capacitor is connected in parallel between the positive input pin and the negative input pin of the differential amplifier chip.

[0012] An output pin of the differential amplifier chip is connected to an input end of the preamplifier through a series resistor; and a feedback resistor is connected between a feedback pin and an output pin of the preamplifier.

[0013] According to the technical scheme, the synchronous control circuit further comprises:

[0014] The phase-locked loop circuit is connected between the crystal circuit and the clock distribution chip; the phase-locked loop circuit comprises a phase-locked loop chip, a loop filter capacitor and a frequency division resistor.

[0015] A reference clock input end of the phase-locked loop chip is connected to an output end of the crystal circuit; a loop filter pin of the phase-locked loop chip is grounded through the loop filter capacitor; and an output end of the phase-locked loop chip is connected to a clock input end of the clock distribution chip through the frequency division resistor.

[0016] An impedance matching resistor is connected in series to each clock output end of the clock distribution chip.

[0017] According to the technical scheme, the data buffer circuit further comprises:

[0018] The hierarchical mark circuit comprises a trigger signal input terminal, an edge detection chip and a counter chip;

[0019] The trigger signal input terminal is connected to an input pin of the edge detection chip, and an output pin of the edge detection chip is connected to a count input end of the counter chip;

[0020] A count output end of the counter chip is connected to a mark input end of the address controller, and a mark output end of the address controller is electrically connected to a mark data input end of the FIFO storage chip, for writing layer separation mark data into the FIFO storage chip.

[0021] With the technical scheme, the three independent sampling channel units in the multi-channel sampling circuit comprise:

[0022] The first sampling channel unit is configured with a 12-bit resolution chip as the analog-digital conversion chip, and a sampling frequency configuration pin is connected to a medium voltage through a configuration resistor, for configuring a 100 kHz sampling frequency;

[0023] The second sampling channel unit is configured with a 16-bit resolution chip as the analog-digital conversion chip, and a sampling frequency configuration pin is connected to a high voltage through a configuration resistor, for configuring a 10 kHz sampling frequency;

[0024] The third sampling channel unit is configured with a 24-bit resolution chip as the analog-digital conversion chip, and a sampling frequency configuration pin is connected to a low voltage through a configuration resistor, for configuring a 1 kHz sampling frequency.

[0025] With the technical scheme, the communication circuit further comprises:

[0026] The twisted pair driving chip is connected to the input end of the communication protocol chip, and the output end of the twisted pair driving chip is connected to the differential signal terminal of the interface connector through a matching resistor network.

[0027] The isolation transformer is connected between the twisted pair driving chip and the interface connector, the primary coil of the isolation transformer is connected to the output end of the twisted pair driving chip, and the secondary coil is connected to the interface connector.

[0028] With the technical scheme, the power supply circuit further comprises a power input interface, a voltage stabilizing chip set and a filter capacitor set; the power input interface is connected to the input pin one of the voltage stabilizing chip set, the voltage stabilizing chip set outputs +5V voltage to the power pin of the analog-digital conversion chip through the output pin one; the power input interface is connected to the input pin two of the voltage stabilizing chip set, and the voltage stabilizing chip set outputs +3.3V voltage to the power pin of the communication protocol chip through the output pin two.

[0029] The above technical solution includes a data cache circuit and a status monitoring circuit. The FIFO memory chip is equipped with a full flag output terminal and an empty flag output terminal. The full flag output terminal and the empty flag output terminal are electrically connected to the status input terminal of the address controller, respectively, and are used to feed back the storage status information of the FIFO memory chip to the address controller.

[0030] The above technical solution includes an electrostatic discharge (ESD) protection circuit, which consists of a TVS diode and a common-mode choke. The TVS diode is connected in parallel between the signal terminal of the interface connector and ground, and the common-mode choke is connected in series between the twisted-pair driver chip and the isolation transformer to provide ESD protection and common-mode interference suppression.

[0031] The power supply circuit in the above technical solution also includes a power indicator circuit and an overcurrent protection circuit. The power indicator circuit includes a power indicator light and a current-limiting resistor. The power indicator light is electrically connected to the output terminal of the voltage regulator chip group through the current-limiting resistor. The overcurrent protection circuit includes a resettable fuse, which is connected in series between the power input interface and the input terminal of the voltage regulator chip group.

[0032] Due to the adoption of the above technical solution, the technological progress achieved by this utility model compared to the prior art is as follows:

[0033] This invention establishes three independent sampling channel units, each equipped with a signal conditioning circuit and an analog-to-digital converter (ADC). The signal conditioning circuit includes an input interface connector, a preamplifier, a filter capacitor, and a conditioning resistor. The output of the preamplifier is connected to the analog input of the ADC through the filter capacitor, forming a hardware channel for independent acquisition and preprocessing of multiple signals. A crystal oscillator circuit and a clock distribution chip constitute a synchronization control circuit. The clock distribution chip has three clock outputs, each connected to the clock input pin of the ADC in each sampling channel unit, providing a unified hardware clock source for the three sampling channels and solving the problem of asynchronous sampling of multiple signals in existing technologies. The data buffer circuit uses a FIFO memory chip and an address controller. The data input of the FIFO memory chip is connected in parallel with the digital output pins of each ADC through a data bus, and the output of the address controller is connected to the address input of the FIFO memory chip, providing an efficient hardware foundation for data buffering. The communication circuit uses a communication protocol chip and an interface connector. The data end of the communication protocol chip is connected to the data output end of the FIFO storage chip, which ensures the stable transmission of the acquired data and provides a reliable data acquisition hardware platform for additive manufacturing AI generative design. Attached Figure Description

[0034] The present invention will be further described below with reference to the accompanying drawings.

[0035] Fig. 1 It is the principle schematic view of the product AI generative design system for additive manufacturing of the utility model;

[0036] Fig. 2 It is the circuit structure schematic view of the multi-channel sampling module of the utility model;

[0037] Fig. 3 It is the circuit structure schematic view of the synchronous control module of the utility model.

[0038] In the figure: 1, multi-channel sampling circuit;11, first sampling channel unit;12, second sampling channel unit;13, third sampling channel unit;2, synchronous control circuit;3, data buffer circuit;4, communication circuit. DETAILED DESCRIPTION

[0039] The utility model will be further explained in detail in combination with examples:

[0040] Example 1

[0041] As Figs. 1-3 Indicated, the utility model provides product AI generative design system for additive manufacturing, include:

[0042] This embodiment provides a kind of product AI generative design system for additive manufacturing, the system is based on the four-layer printed circuit board of FR-4 material quality construction, circuit board size is 180mm ×120mm, board thickness 1.6mm.

[0043] Multi-channel sampling circuit 1 includes three independent sampling channel units, including:

[0044] The first sampling channel unit 11 is used for collecting fast-varying signals such as vibration, the sampling frequency is 100 kHz, the resolution is 12 bits, the input interface connector J1 adopts a double-row seat, the IN1+ pin is connected to the positive terminal of the sensor signal, and the IN1- pin is connected to the negative terminal of the sensor signal. The differential amplifier chip U1 adopts INA128 instrument amplifier, the gain resistor RG1 connected between the D0 pin and the D7 pin is 499Ω, and the gain is 101 times; the IN- pin is connected to the D1 pin of J1 through the input resistor R10, and the IN+ pin is connected to the D0 pin of J1 through the input resistor R11, and the resistance values of R10 and R11 are both 1kΩ. The common-mode filter capacitor C20 connected in parallel between D1 and D2 is 100pF. The negative power supply pin V- is connected to-5V negative power supply. The OUT pin is connected to the preamplifier through the series resistor R12. The preamplifier U2 adopts OP07CP operational amplifier, the IN- pin is connected to the U1 output through the input resistor R13, the feedback resistor R14 connected between D1 and D5 pins is 10kΩ, and the inverting amplifier is formed. The D5 pin output end is connected to the analog-to-digital conversion chip U3 through the filter capacitor C21 after the series regulating resistor R15. U3 adopts Analog Devices AD7476ARTZ, 12-bit SAR ADC, the VREF pin is connected to the reference voltage source output, the SDATA serial data output pin is connected to the data bus DB0 pin through the pull-up resistor R16 connected to +3.3V_D, the SCLK pin is connected to the clock signal CLK_CH1 pin and the matching resistor R17 in series with 33Ω, and the VDD pin is connected to +5V_A and the decoupling capacitors C30 and C31 in parallel.

[0045] The second sampling channel unit 12 is used for collecting medium-speed signals such as temperature, the sampling frequency is 10 kHz, the resolution is 16 bits, the input interface J2 circuit topology is similar to the first channel, the differential amplifier U4 is INA128, the gain resistor RG2 is 2.49kΩ, and the gain is 21 times. The preamplifier U5 is OP07CP, configured as a gain-2 times inverting amplifier, the input resistor R20 is 10kΩ, and the feedback resistor R21 is 20kΩ. The analog-to-digital conversion chip U6 adopts ADS8326, 16-bit SAR ADC, the AINP pin is connected to the filter capacitor C32, the AVDD pin is connected to +5V_A and the decoupling capacitors C33 and C34 in parallel, the REFIN pin is connected to the reference voltage source, the D0 to D3 digital output pins are connected to the data bus DB1 to DB4 pins respectively, the SCLK pin is connected to the CLK_CH2 pin and the matching resistor R22 in series with 33Ω, and the DVDD pin is connected to +3.3V_D.

[0046] The third sampling channel unit 13 is used for collecting strain and other high-precision low-frequency signals, with a sampling frequency of 1 kHz and a resolution of 24 bits. The differential amplifier INA128 is used in the input interface J3, with a gain resistor RG3 of 10 kΩ, achieving a gain of 6 times. The preamplifier OP07CP is configured as an inverting amplifier with a gain of -5, with an input resistor R30 of 10 kΩ and a feedback resistor R31 of 50 kΩ. The analog-to-digital conversion chip ADS1220 is used, with a 24-bit ADC, with the AIN0 pin connected to the filter capacitor C35, the AVDD pin connected to +5V_A with the decoupling capacitors C36 and C37 in parallel, the SCLK pin connected to the CLK_CH3 pin with a matching resistor R32 of 33 Ω in series, the DOUT data output pin connected to the data bus DB5 with an isolation resistor R33 of 47 Ω in series, and the DVDD pin connected to +3.3V_D. The reference voltage source for the three-channel sampling unit is a 5.0V reference voltage.

[0047] The synchronous control circuit 2 is responsible for providing strict synchronization clock signals for the three-channel sampling, ensuring synchronous sampling of multiple signals. The circuit includes a crystal oscillator circuit and a phase-locked loop circuit. The active crystal oscillator XO1 is used, with a model of Abracon ASE-25.000MHz-LC-T and a frequency of 25 MHz. The EN pin of XO1 is connected to +3.3V_D through a pull-up resistor R40, the OUT pin outputs a 25 MHz clock signal with a source-end matching resistor R41 of 33 Ω in series, and the VDD pin is connected to +3.3V_D with decoupling capacitors C38 and C39 in parallel.

[0048] The phase-locked loop circuit adopts a programmable clock synthesizer U10, model CDCE913, with three independent clock output functions. The CLKIN reference clock input terminal pin of U10 is connected to the OUT pin of XO1 and connected to ground in parallel with a 50Ω terminal resistor R42, and its SDA 50Ω and SCL 50Ω are I2C interfaces, connected to the I2C pins of the microcontroller MCU through pull-up resistors R43 and R44, respectively, for configuring register parameters, and the Y0 pin outputs a 1.6MHz clock signal, which is output as CLK_CH1 for the first sampling channel unit 11 after being connected in series with an impedance matching resistor R45 of 33Ω. The Y1 pin outputs a 160kHz clock signal, which is output as CLK_CH2 for the second sampling channel unit 12 after being connected in series with a resistor R46 of 33Ω. The Y2 pin outputs a 16kHz clock signal, which is output as CLK_CH3 for the third sampling channel after being connected in series with a resistor R47 of 33Ω. The PLL_VDD pin is connected to +3.3V_D in parallel with decoupling capacitors C40 and C41, the PLL_FILTER loop filter pin is connected to ground in parallel with filter capacitors C42 and C43, and the filter pin is connected in series with a frequency division resistor R48 of 1kΩ between the filter pin and the power supply. U10 configures the frequency division ratio through the I2C interface, and the three clock outputs are strictly synchronized, respectively driving three ADC chips to sample synchronously, effectively solving the problem of asynchronous sampling of multiple signals.

[0049] The data buffer circuit 3 is responsible for receiving the digital data output by the three ADCs, buffering and organizing by layers, including FIFO storage chips, address controllers and layered marker circuits. The FIFO storage chip U11 uses Cypress CY7C4265V with a capacity of 64Kx9bit. The D0 to D8 data input terminal pins of U11 are connected in parallel through the data bus to the digital output ports of the analog-to-digital conversion chips in the three data acquisition units: the D0 pin is connected to the SDATA pin of U3, the D1 to D4 pins are connected to the D0 to D3 pins of U6, the D5 pin is connected to the DOUT pin of U9, and the D6 to D8 pins are used for layer marker data. The W write enable terminal pin is connected to the WR write control signal terminal pin of the address controller, the OE output enable terminal pin is connected to the RD read control signal terminal pin, and the Q0 to Q8 data output terminal pins are connected to the data input terminals of the communication protocol chip. The FF full flag terminal pin and the EF empty flag output terminal pin are connected to the address controller for state monitoring. The power supply terminal pin VCC is connected to +3.3V_D in parallel with decoupling capacitors C44, C45, C46 and C47.

[0050] The address controller adopts a microcontroller MCU, model number STM32F103C8T6. The NRST reset end of the MCU is connected to a reset circuit, the VDDA analog power supply pin is connected in parallel to +3.3V_A and decoupling capacitors C48 and C49. The PA0 pin is configured as a GPIO output and is connected to the W write enable end of U11, the PA1 pin is configured as a GPIO output and is connected to the R read enable end of U11, the PA2 pin and the PA3 pin are configured as GPIO inputs and are connected to the FF and EF flag pins of U11. PB9 and PB10 are configured as I2C interfaces and are connected to the SDA and SCL pins of U10 for configuring a phase-locked loop chip. PB12 and PB13 are configured as external interrupt inputs and are connected to the EOC conversion end signal of U9 and the DRDY data ready signal of U8, respectively. The MCU controls the read and write operations of the FIFO through an interrupt response mechanism, thereby achieving efficient data cache management.

[0051] The hierarchical marking circuit is used for receiving a Z-axis layer changing signal of a printing device to realize data storage by layers. The trigger signal input terminal J4 adopts an MSTB 2.5 / 2-ST wiring terminal, the TRIG pin is connected to the layer changing signal, and the D0 pin is connected to GND. The edge detection chip U12 adopts a Schmitt trigger SN74LVC1G17, the A input end pin is connected to the D0 pin of J4 and is connected to ground through a pull-down resistor R56, a parallel filter capacitor C83 is 100 nF, and the Y output end pin is connected to a counter chip through a series isolation resistor R57. The counter chip U13 adopts a SN74LV8154 dual 16-bit binary counter, the CCLK count clock input end pin is connected to the output of U11, the QA0 to QA15 pins are parallel output ends, the QA0 to QA7 are connected to the GPIO pins of the MCU, and each signal line is connected in series with an isolation resistor 100Ω. When the printing device changes layers, the TRIG signal generates an edge trigger to count U13, and after the MCU detects the change in the count value, a layer separation mark is inserted in the FIFO storage space. The specific implementation manner is to write a specific flag code 0xAA in the D6 to D8 data bits, so as to realize automatic segmented storage of data by printing layers and solve the problem of data organization by layers.

[0052] The reset circuit adopts a voltage monitoring reset chip U14, model number Maxim MAX809SEUR, threshold value 2.93V, the RESET output end pin is connected to +3.3V_D through a pull-up resistor R67, and the output end pin is connected to the NRST pin of the MCU, the RS pin of U9 and the CCLR pin of U13. When the power supply voltage is lower than the threshold value, the U14 outputs a low-level reset signal to ensure reliable reset of the system.

[0053] The communication circuit 4 is responsible for transmitting the buffered data to the host computer through the industrial Ethernet interface. The communication protocol chip U15 uses Microchip ENC28J60 independent Ethernet controller, SSOP-28 package, supporting 10Mbps transmission rate. The SO, SI, SCK, CS pins of U15 are SPI interface pins, connected to the SPI interface of the MCU for data transmission and register configuration. The TPIN+ pin and the TPIN- pin are the receiving differential input terminals, and the TPOUT+ pin and the TPOUT- pin are the transmitting differential output terminals. The RBIAS bias resistance terminal is grounded through the resistance R68 of 2.49kΩ. The OSC1 to OSC5 pins are crystal pins, and a 25MHz passive crystal Y1 is connected between OSC1 and OSC2, with a load capacitor C93 and C94 of 18pF respectively connected in parallel between the two ends and GND. The power supply pin VDD is connected to +3.3V_D in parallel with multiple decoupling capacitors.

[0054] The transmitting differential output terminals TPOUT+ and TPOUT- of U15 are each connected to the primary winding of the isolation transformer T1 after being connected in series with source-end matching resistors R70 and R71 of 12.5Ω. T1 uses Pulse H1102NL Ethernet transformer with a 1:1 turns ratio and integrated common-mode choke to provide 1500V electrical isolation. The receiving coil of T1 is connected to the receiving differential input terminals TPIN+ and TPOIN- of U15 through series resistors R76 and R77, realizing bidirectional transmission of signals. The isolation transformer effectively prevents ground interference and improves the system's anti-interference ability.

[0055] The power supply circuit is responsible for providing stable multi-channel power supply for the entire system, including analog power supply, digital power supply, and reference voltage source power supply. The circuit uses WAGO 2060 series spring-type terminal blocks as the power supply input interface, with the input port connected to +24V DC input and the output port connected to GND. The input end is connected in series with a self-restoring fuse, and the back end is connected in parallel with a transient suppression diode, providing overvoltage protection.

[0056] The voltage stabilizing chip set includes three independent voltage stabilizing circuits. The first one uses a Texas Instruments switching regulator to provide a +5V / 3A analog power supply. The second one uses a super-low noise LDO voltage regulator to output a +3.3V / 1A digital power supply. The third one uses a super-low noise LDO voltage regulator U3 to output a +5V / 0.2A reference power supply.

[0057] The working process of the system is as follows:

[0058] After the system is powered on, the +24V power supply is protected and filtered, and each power supply such as +5V_A, +3.3V_D, +5V_VREF is generated in turn, and the power supply indication LED is lit. The reset chip U14 releases the reset signal after detecting that the power supply is stable, and the MCU starts and executes the initialization program. The MCU first configures the phase-locked loop chip U13 through the I2C interface, sets the frequency division ratio to generate three synchronous clock signals of 1.6MHz, 160kHz and 16kHz, and drives three ADC chips respectively. The MCU then initializes the FIFO chip U14 to empty the storage space, configures the sampling mode and gain parameters of the ADC chips U6, U9 and U12, and initializes the Ethernet controller U15 through the SPI interface to set the network parameters. The system enters the ready state and waits for the sampling trigger.

[0059] The synchronous control circuit uses phase-locked loop (PLL) technology to realize multi-channel clock synchronization. The phase-locked loop chip U10 uses the 25MHz clock signal output by the crystal oscillator circuit as the reference clock, forms a closed loop control through the internal phase discriminator, loop filter and voltage-controlled oscillator, and generates multiple output clocks that are strictly phase-locked with the reference clock. The three output clocks Y0, Y1 and Y2 are configured through different frequency division ratios to generate 1.6MHz, 160kHz and 16kHz clock signals, respectively, to drive three ADC chips for synchronous sampling. Since the three clock signals are derived from the same reference clock and are locked by the phase-locked loop, the phase deviation between the clock signals can be controlled within nanoseconds, effectively solving the problem of asynchronous sampling of multiple signals.

[0060] During data sampling, the three ADCs are strictly synchronized to start sampling under the drive of their respective clocks. The sensor signal enters through the input interface, is amplified and filtered by the differential amplifier and the preamplifier in turn, and is converted to the ADC input range. The signal conditioning circuit uses an instrument amplifier for differential signal amplification, effectively suppressing common-mode interference; the preamplifier uses an operational amplifier to form an inverting amplifier circuit, realizing further amplification and impedance matching of the signal. After the ADC completes the analog-to-digital conversion, the digital data is output to the parallel data bus, and a conversion completion signal is generated to trigger the MCU interrupt. The MCU responds to the interrupt to generate a FIFO write enable signal, and writes the data on the data bus to the FIFO storage chip. The above signal conditioning and analog-to-digital conversion method is a conventional technical means in the field of data acquisition system design.

[0061] When the printing device changes layer, the Z-axis layer changing signal is input to the trigger terminal J4, is shaped after the Schmitt trigger U12 triggers the counter U13 to count plus one. The MCU detects the change of the count value, and writes the layer separation mark data in the FIFO. The specific method is: writing a specific mark code 0xAA in D6 to D8 data bits, so as to realize automatic segmentation storage of data according to the printing layer. The layer separation mark method adopts the mode of detecting edge trigger signal by the counter and writing specific mark code, which is a conventional technical means in the field of digital circuit design.

[0062] The data buffer adopts a FIFO (First In First Out) memory to realize. The FIFO storage chip U11 has independent read and write clocks and read and write pointers, and supports asynchronous read and write operations. The MCU controls the read and write operations of the FIFO through an interrupt response mechanism: when the ADC generates a conversion completion signal, the MCU responds to the interrupt and generates a write enable signal to write data into the FIFO; when the communication circuit is ready, the MCU generates a read enable signal to read data from the FIFO and send it. The full flag FF and the empty flag EF of the FIFO are used to prevent data overflow and empty reading. The FIFO buffer management method is a conventional technical means in the field of embedded data acquisition system design.

[0063] During data transmission, the MCU reads data from the FIFO periodically, and sends the data to the Ethernet controller U20 through the SPI interface. U20 encapsulates the data into an Ethernet data packet and transmits it to the host computer. The host computer software parses the data packet, organizes the data according to the layer separation mark, and stores, analyzes and visualizes the data. Through the cooperative work of the hardware circuit, the system realizes strict synchronous acquisition of three process parameters and layer-organized data, effectively solving the problems of the prior art.

[0064] The above has made a detailed description of the general utility model, but some modifications or improvements can be made on the basis of the utility model, which is obvious to those skilled in the art. Therefore, without departing from the spirit of the utility model, the modification or improvement is within the protection scope of the utility model.

Claims

1. A product AI generative design system for additive manufacturing, characterized in that, include: The multi-channel sampling circuit (1) includes three independent sampling channel units; Each sampling channel unit includes a signal conditioning circuit and an analog-to-digital converter chip. The signal conditioning circuit includes an input interface connector, a preamplifier, a filter capacitor, and a conditioning resistor. The output of the preamplifier is connected to the analog input of the analog-to-digital converter chip through the filter capacitor. Synchronous control circuit (2) includes a crystal oscillator circuit and a clock distribution chip; the output terminal of the crystal oscillator circuit is connected to the clock input terminal of the clock distribution chip, and the clock distribution chip has three clock output terminals, each of which is connected to the clock input pin of the analog-to-digital converter chip corresponding to the sampling channel unit. The data caching circuit (3) includes a FIFO storage chip and an address controller. The data input terminal of the FIFO storage chip is connected in parallel with the digital output pin of each of the analog-to-digital converter chips through a data bus. The output terminal of the address controller is connected to the address input terminal of the FIFO storage chip. The communication circuit (4) includes a communication protocol chip and an interface connector, wherein the data terminal of the communication protocol chip is connected to the data output terminal of the FIFO storage chip.

2. The AI ​​generative design system for additive manufacturing products according to claim 1, characterized in that: The signal conditioning circuit further includes: The differential amplifier chip has an input interface connector that includes a first input terminal and a second input terminal. The first input terminal is connected to the positive input pin of the differential amplifier chip through a first input resistor, and the second input terminal is connected to the inverting input pin of the differential amplifier chip through a second input resistor. A common-mode filter capacitor is connected in parallel between the positive input pin and the negative input pin of the differential amplifier chip. The output pin of the differential amplifier chip is connected to the input terminal of the preamplifier through a series resistor, and a feedback resistor is connected between the feedback pin and the output pin of the preamplifier.

3. The AI ​​generative design system for additive manufacturing products according to claim 1, characterized in that: The synchronization control circuit (2) further includes: A phase-locked loop circuit is connected between the crystal oscillator circuit and the clock distribution chip. The phase-locked loop circuit includes a phase-locked loop chip, a loop filter capacitor, and a frequency divider resistor. The reference clock input terminal of the phase-locked loop chip is connected to the output terminal of the crystal oscillator circuit, the loop filter pin of the phase-locked loop chip is grounded through the loop filter capacitor, and the output terminal of the phase-locked loop chip is connected to the clock input terminal of the clock distribution chip through the frequency divider resistor. Each clock output terminal of the clock distribution chip is connected in series with an impedance matching resistor.

4. The AI ​​generative design system for additive manufacturing products according to claim 1, characterized in that: The data cache circuit (3) also includes: The layered marking circuit includes a trigger signal input terminal, an edge detection chip, and a counter chip; The trigger signal input terminal is connected to the input pin of the edge detection chip, and the output pin of the edge detection chip is connected to the counting input terminal of the counter chip; The counter chip's counting output terminal is connected to the address controller's tag input terminal, and the address controller's tag output terminal is electrically connected to the FIFO memory chip's tag data input terminal, used to write layer separation tag data to the FIFO memory chip.

5. The AI ​​generative design system for additive manufacturing products according to claim 1, characterized in that: The three independent sampling channel units in the multi-channel sampling circuit (1) include: The first sampling channel unit (11) has an analog-to-digital conversion chip that is a 12-bit resolution chip. The sampling frequency configuration pin is connected to a medium level through a configuration resistor to configure a 100kHz sampling frequency. The second sampling channel unit (12) has an analog-to-digital conversion chip that is a 16-bit resolution chip. The sampling frequency configuration pin is connected to a high level through a configuration resistor to configure a 10kHz sampling frequency. The third sampling channel unit (13) has a 24-bit resolution chip for analog-to-digital conversion. The sampling frequency configuration pin is connected to a low level through a configuration resistor to configure a 1kHz sampling frequency.

6. The AI ​​generative design system for additive manufacturing products according to claim 1, characterized in that: The communication circuit (4) further includes: The communication protocol chip has a differential output pin connected to the input terminal of the twisted pair driver chip, and the output terminal of the twisted pair driver chip is connected to the differential signal terminal of the interface connector through a matching resistor network. An isolation transformer is connected between the twisted-pair driver chip and the interface connector. The primary coil of the isolation transformer is connected to the output terminal of the twisted-pair driver chip, and the secondary coil is connected to the interface connector.

7. The AI ​​generative design system for additive manufacturing products according to claim 1, characterized in that: It also includes a power supply circuit, including a power input interface, a voltage regulator chip set, and a filter capacitor bank; the power input interface is connected to the input pin one of the voltage regulator chip set, and the voltage regulator chip set outputs a +5V voltage to the power pin of the analog-to-digital converter chip through the output pin one; the power input interface is connected to the input pin two of the voltage regulator chip set, and the voltage regulator chip set outputs a +3.3V voltage to the power pin of the communication protocol chip through the output pin two.

8. The AI ​​generative design system for additive manufacturing products according to claim 1, characterized in that: The data caching circuit (3) further includes a status monitoring circuit. The FIFO storage chip is provided with a full flag output terminal and an empty flag output terminal. The full flag output terminal and the empty flag output terminal are electrically connected to the status input terminal of the address controller, respectively, and are used to feed back the storage status information of the FIFO storage chip to the address controller.

9. The AI ​​generative design system for additive manufacturing products according to claim 6, characterized in that: The communication circuit (4) also includes an electrostatic discharge protection circuit, which includes a TVS diode and a common-mode choke. The TVS diode is connected in parallel between the signal terminal of the interface connector and ground, and the common-mode choke is connected in series between the twisted-pair driver chip and the isolation transformer to provide electrostatic discharge protection and common-mode interference suppression.

10. The AI ​​generative design system for additive manufacturing products according to claim 7, characterized in that: The power supply circuit also includes a power indicator circuit and an overcurrent protection circuit. The power indicator circuit includes a power indicator light and a current-limiting resistor. The power indicator light is electrically connected to the output terminal of the voltage regulator chip group through the current-limiting resistor. The overcurrent protection circuit includes a resettable fuse, which is connected in series between the power input interface and the input terminal of the voltage regulator chip group.

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