Inverter and power electronic device

Abstract

The utility model provides an inverter and a power electronic device, and relates to the technical field of semiconductor devices, and the inverter comprises a first packaging structure, a second packaging structure, a first copper bar, a second copper bar and a third copper bar. The first package structure has at least one first transistor, and a first connection terminal electrically connected to the first transistor. The second package structure has at least one second transistor, and a second connection terminal and a third connection terminal electrically connected to the second transistor. The first copper bar and the second copper bar are DC input and output ends respectively, the third copper bar is an AC output end, and the projection of the second copper bar and the projection of the third copper bar in the second direction are not overlapped. Therefore, the projection of the direct-current busbar formed by the first copper bar and the second copper bar and the projection of the alternating-current busbar formed by the third copper bar in the first direction are not overlapped, the purpose of separating the direct-current busbar from the alternating-current busbar in space is achieved, the effect of well reducing parasitic inductance is achieved, and the design difficulty of the copper bars can also be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to an inverter and a power electronic device. BACKGROUND

[0002] With the rapid development of the semiconductor industry, the application of semiconductor devices is also more and more widely. Among them, the semiconductor device can be used to control the current, for example, the inverter, and the working performance thereof plays an important role for the entire power electronic device to which it is applied. Therefore, how to improve the functional performance of the inverter has become the research focus of the person skilled in the art. CONTENT OF THE UTILITY MODEL

[0003] Therefore, the present application provides an inverter and a power electronic device, and the scheme is as follows:

[0004] An inverter, comprising:

[0005] A packaging structure, the packaging structure comprises a first packaging structure and a second packaging structure arranged along a first direction, the first direction being parallel to a mounting surface of the packaging structure; the first packaging structure has at least one first transistor, the second packaging structure has at least one second transistor, and the first transistor and the second transistor are electrically connected one by one; wherein the first packaging structure further has at least one first connecting terminal, the first transistor and the first connecting terminal are electrically connected one by one, the second packaging structure further has at least one second connecting terminal and at least one third connecting terminal, the second transistor and the second connecting terminal are electrically connected one by one, and the second transistor and the third connecting terminal are electrically connected one by one;

[0006] A first copper bar, the first copper bar is located on a side of the first packaging structure away from the second packaging structure, and is electrically connected with the first transistor through the first connecting terminal;

[0007] A second copper bar, the second copper bar extends along the first direction and is arranged along a second direction with the packaging structure, and the second copper bar is electrically connected with the second transistor through the second connecting terminal; wherein the second direction is perpendicular to the mounting surface of the packaging structure, the first copper bar is a direct current input end of the inverter, and the second copper bar is an output end of a direct current loop of the inverter;

[0008] A third copper bar, the third copper bar is located on a side of the second packaging structure away from the first packaging structure, and is electrically connected with the second transistor through the third connecting terminal, and the third copper bar is an alternating current output end of the inverter; wherein a projection of the second copper bar along the second direction and a projection of the third copper bar along the second direction do not overlap.

[0009] Optionally, further comprising:

[0010] a direct current bus capacitor, located on a side of the first packaging structure facing away from the second packaging structure, having a positive connection terminal and a negative connection terminal;

[0011] the positive connection terminal is electrically connected with the first copper bar;

[0012] the negative connection terminal is electrically connected with the second copper bar.

[0013] Optionally, a projection of the second copper bar along the second direction covers a projection of the first packaging structure along the second direction, and covers a projection of an area of the second packaging structure other than the third connection terminal along the second direction.

[0014] Optionally, the first packaging structure further has at least one fourth connection terminal, and the second packaging structure further has at least one fifth connection terminal;

[0015] the first transistor is further electrically connected with the fourth connection terminal one by one, and the second transistor is further electrically connected with the fifth connection terminal one by one;

[0016] wherein the fourth connection terminal is electrically connected with the fifth connection terminal one by one, so that the first transistor and the second transistor are electrically connected one by one.

[0017] Optionally, the first packaging structure further comprises at least one first connection layer, and the first transistor is located on a surface of the first connection layer and is electrically connected with the first connection terminal through the first connection layer;

[0018] the second packaging structure further comprises at least one second connection layer, and the second transistor is located on a surface of the second connection layer and is electrically connected with the third connection terminal and the fifth connection terminal through the second connection layer.

[0019] Optionally, the first transistor is a MOS field effect transistor, and the second transistor is a MOS field effect transistor.

[0020] Optionally, a drain of the first transistor is electrically connected with the first connection terminal, and a source of the first transistor is electrically connected with the fourth connection terminal;

[0021] a source of the second transistor is electrically connected with the second connection terminal, a drain of the second transistor is electrically connected with the third connection terminal, and the drain of the second transistor is further electrically connected with the fifth connection terminal.

[0022] Optionally, the first transistor is composed of an IGBT transistor and a diode, the anode of the diode is electrically connected with the collector of the IGBT transistor, and the cathode of the diode is electrically connected with the emitter of the IGBT transistor; the second transistor is composed of an IGBT transistor and a diode, the anode of the diode is electrically connected with the collector of the IGBT transistor, and the cathode of the diode is electrically connected with the emitter of the IGBT transistor.

[0023] Optionally, the collector of the first transistor is electrically connected with the first connection terminal, and the emitter of the first transistor is electrically connected with the fourth connection terminal.

[0024] The emitter of the second transistor is electrically connected with the second connection terminal, the collector of the second transistor is electrically connected with the third connection terminal, and the collector of the second transistor is also electrically connected with the fifth connection terminal.

[0025] A power electronic device comprising the inverter of any of the above embodiments.

[0026] Compared with the related art, the technical scheme of the present application has the following advantages:

[0027] The inverter comprises a packaging structure and first to third copper bars. The packaging structure comprises a first packaging structure having at least one first transistor and a second packaging structure having at least one second transistor, the first packaging structure further having a first connection terminal electrically connected with the first transistor, and the second packaging structure further having a second connection terminal and a third connection terminal electrically connected with the second transistor. The first copper bar is located on the side of the first packaging structure away from the second packaging structure and is electrically connected with the first transistor through the first connection terminal. The second copper bar extends along a first direction and is arranged along a second direction in sequence with the packaging structure and is electrically connected with the second transistor through the second connection terminal. The third copper bar is located on the side of the second packaging structure away from the first packaging structure and is electrically connected with the second transistor through the third connection terminal. The first copper bar and the second copper bar are direct current input and output terminals respectively, the third copper bar is an alternating current output terminal, and the projection of the second copper bar along the second direction does not overlap the projection of the third copper bar along the second direction. Therefore, the projection of the direct current busbar composed of the first copper bar and the second copper bar along the first direction does not overlap the projection of the alternating current busbar composed of the third copper bar along the first direction, thereby achieving the purpose of spatial separation of the direct current busbar and the alternating current busbar, avoiding the intersection of the alternating current busbar and the direct current busbar, having a good effect of reducing parasitic inductance, and also reducing the design difficulty of the copper bar and simplifying the production process. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the accompanying drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of the provided drawings.

[0029] The structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the present specification, to be understood and read by those skilled in the art, and do not have technical significance to limit the conditions that can be implemented by the present application. Therefore, any modification of structure, change of proportion relationship or adjustment of size, which does not affect the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0030] Figure 1 A schematic diagram of a related art inverter structure;

[0031] Figure 2 A schematic diagram of an inverter structure provided by the present application;

[0032] Figure 3 A schematic diagram of an inverter circuit structure provided by the present application;

[0033] Figure 4 Another schematic diagram of an inverter structure provided by the present application;

[0034] Figure 5 Another schematic diagram of an inverter structure provided by the present application;

[0035] Figure 6 Another schematic diagram of an inverter structure provided by the present application. DETAILED DESCRIPTION

[0036] The embodiments in the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0037] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0038] As described in the background section, how to improve the working performance of the inverter has become a key research topic for those skilled in the art.

[0039] In the related art, as shown in Figure 1 Figure 1 The upper pipe and the lower pipe have the same packaging structure, and the AC output is led out from the middle layers (628 and 614) of the upper pipe and the lower pipe. The upper pipe, the lower pipe and the DC bus copper bars (606 and 608) form a stack, which can reduce the parasitic inductance of the inverter. However, the scheme has the following problems: when the AC copper bars lead out the AC from the middle layers (628 and 614), the AC copper bars will cross the DC bus copper bars (606 and 608). Since the voltage on the copper bars is relatively high and a large current flows through, the crossing of the copper bars brings great difficulty to the design of the copper bars, and increases the complexity of the production process; and the crossing of the AC copper bars and the DC bus copper bars will damage the integrity of the stacked copper bars, affecting the effect of the stacked copper bars on reducing the parasitic inductance.

[0040] Based on the above, the application provides an inverter, as shown in Figure 2 The inverter comprises:

[0041] A packaging structure 110, the packaging structure 110 comprises a first packaging structure 111 and a second packaging structure 112 arranged along a first direction, the first direction being parallel to the mounting surface of the packaging structure 110. The first packaging structure 111 encapsulates at least one first transistor 1, forming an upper pipe of the inverter, and the second packaging structure 112 encapsulates at least one second transistor 2, forming a lower pipe of the inverter, and the first transistor 1 and the second transistor 2 are electrically connected one by one, that is, the upper pipe and the lower pipe of the inverter are electrically connected.

[0042] The first packaging structure 111 further has at least one first connecting terminal 1111, the first transistor 1 is electrically connected to the first connecting terminal 1111 one by one, the second packaging structure 112 further has at least one second connecting terminal 1121 and at least one third connecting terminal 1122, the second transistor 2 is electrically connected to the second connecting terminal 1121 one by one, and the second transistor 2 is further electrically connected to the third connecting terminal 1122 one by one. Specifically, the first packaging structure 111 has a first connecting terminal 1111 extending outward through a plastic encapsulation layer, a portion of the first connecting terminal 1111 located in the first packaging structure 111 is electrically connected to the first transistor 1, and the second packaging structure 112 has a second connecting terminal 1121 and a third connecting terminal 1122 extending outward through a plastic encapsulation layer, portions of the second connecting terminal 1121 and the third connecting terminal 1122 located in the second packaging structure 112 are electrically connected to the second transistor 2.

[0043] ​The first copper bar 201 is located on the side of the first packaging structure 111 away from the first packaging structure 111, that is, the first copper bar 201, the first packaging structure 111 and the second packaging structure 112 are arranged in the first direction in turn. The first copper bar 201 is electrically connected to the first transistor 1 through the first connecting terminal 1111.

[0044] The second copper bar 202 extends in the first direction and is arranged in the second direction along the packaging structure 110 in turn, and the second copper bar 202 is electrically connected to the second transistor 2 through the second connecting terminal 1121. The second direction is perpendicular to the mounting surface of the packaging structure 110, that is, the second copper bar 202 and the packaging structure 110 are arranged in the second direction in layers. In addition, the first copper bar 201 is the direct current positive electrode of the inverter, and the second copper bar 202 is the direct current negative electrode of the inverter. It should be noted that, as shown in Figure 3 When the first packaging structure 111 has a plurality of first transistors 1, the arrangement direction of the plurality of first transistors 1 is parallel to the plane where the second copper bar 202 is located, and the plurality of first transistors 1 are arranged in the third direction. When the second packaging structure 112 has a plurality of second transistors 2, the arrangement direction of the plurality of second transistors 2 is parallel to the plane where the second copper bar 202 is located, and the plurality of second transistors 2 are arranged in the third direction. The third direction and the first direction are both parallel to the mounting surface of the packaging structure, but the third direction and the first direction are perpendicular.

[0045] The third copper bar 203 is located on the side of the second packaging structure 112 away from the first packaging structure 111, that is, the first copper bar 201, the first packaging structure 111, the second packaging structure 112 and the third copper bar 203 are arranged in the first direction in turn. In addition, the third copper bar 203 is electrically connected to the second transistor 2 through the third connecting terminal 1122, and the third copper bar 203 is the alternating current output end of the inverter. Specifically, the direct current signal of the inverter flows through the first transistor 1 through the first copper bar 201 and then flows out through the third copper bar 203, or the direct current signal of the inverter flows through the second transistor 2 through the second copper bar 202 and then flows out through the third copper bar 203, so as to realize inversion.

[0046] It should be noted that for the inverter provided in the present application, the projection of the second copper bar 202 in the second direction does not overlap the projection of the third copper bar 203 in the second direction.

[0047] As can be known from the above, the second copper bar 202 and the packaging structure 110 of the inverter are arranged in a stack along the second direction, and the projection of the second copper bar 202 along the second direction does not overlap the projection of the third copper bar 203 along the second direction. In addition, the first copper bar 201, the first packaging structure 111, the second packaging structure 112, and the third copper bar 203 are arranged in sequence along the first direction, so that the projection of the first copper bar 201 along the second direction does not overlap the projection of the third copper bar 203 along the second direction, that is, the direct-current copper bus (referred to as direct-current bus) of the inverter composed of the first copper bar 201 and the second copper bar 202 does not overlap the alternating-current copper bus (referred to as alternating-current bus) composed of the third copper bar 203 along the first direction, thereby achieving the purpose of spatial separation of the direct-current bus and the alternating-current bus, and avoiding the cross of the alternating-current bus and the direct-current bus. Compared with the related art, while the packaging structure and the direct-current bus are arranged in a stack, that is, while the upper tube and the lower tube of the inverter are arranged in a stack with the direct-current bus, the inverter of the present application also avoids the cross of the alternating-current bus and the direct-current bus when the alternating-current bus is led out, has a good effect of reducing the parasitic inductance, so that the parasitic inductance of the inverter is low, which helps to improve the working performance of the inverter and increase the heat dissipation efficiency of the inverter. At the same time, the cross of the alternating-current bus and the direct-current bus when the alternating-current bus is led out is also avoided, which can also reduce the design difficulty of the copper bar, make the welding of the copper bar easy to realize, and simplify the production process.

[0048] Based on the foregoing embodiments, in an embodiment of the present application, as shown in Figure 4 the inverter further comprises:

[0049] a direct-current bus capacitor 300, which is located on the side of the first packaging structure 111 away from the second packaging structure 112, is electrically connected with the power supply, and has a positive connection terminal 301 and a negative connection terminal 302. It should be noted that the power supply is a power supply for providing a direct-current signal to the inverter, which can be part of the inverter, part of the device in which the inverter is located, or an independent power supply for providing a direct-current signal to the inverter only. The present application does not limit this, which is determined according to the situation.

[0050] Among them, the positive connection terminal 301 of the direct-current bus capacitor 300 is electrically connected with the first copper bar 201, so that the direct-current signal is input through the first copper bar 201, and the negative connection terminal 302 of the direct-current bus capacitor 300 is electrically connected with the second copper bar 202, so that the direct-current signal is input through the second copper bar 202.

[0051] Based on the foregoing embodiments, in one embodiment of the present application, the projection of the second copper bar 202 along the second direction covers the projection of the first packaging structure 111 along the second direction, and the projection of the second copper bar 202 along the second direction also covers the projection of the area in the second packaging structure 112 except the third connecting terminal 1122 along the second direction. That is, the projection of the second copper bar 202 along the second direction covers the projection of the area in the packaging structure 110 except the AC output terminal along the second direction, so that the DC bus bar in the inverter can be stacked with the upper pipe and the lower pipe, and the separation of the DC bus bar and the AC bus bar is ensured, so that the parasitic inductance of the inverter is low, which helps to improve the working performance of the inverter and increase the heat dissipation efficiency of the inverter.

[0052] In addition, the projection of the second copper bar 202 along the second direction covers the projection of the area in the packaging structure 110 except the AC output terminal along the second direction, and the second copper bar 202 is electrically connected with the negative connecting terminal 302, and the packaging structure 110 is electrically connected with the positive connecting terminal 301, so that the electric field generated by the second copper bar 202 can offset the electric field generated by the packaging structure 110, thereby further reducing the parasitic inductance.

[0053] It should be noted that in other embodiments of the present application, the above-mentioned DC bus capacitor 300 can also be located below the packaging structure 110, that is, the first copper bar 201, the packaging structure 110 and the DC bus capacitor 300 are stacked and arranged, and the present application does not limit this, which is determined according to the specific circumstances.

[0054] Based on the foregoing embodiments, in one embodiment of the present application, as shown in Figure 5 The first packaging structure 111 also has at least one fourth connecting terminal 1112, and the second packaging structure 112 also has at least one fifth connecting terminal 1123.

[0055] Specifically, the first transistor 1 is electrically connected one-to-one with the first connecting terminal 1111, and the first transistor 1 is also electrically connected one-to-one with the fourth connecting terminal 1112. The second transistor 2 is electrically connected one-to-one with the second connecting terminal 1121 and the third connecting terminal 1122, and the second transistor 1 is also electrically connected one-to-one with the fifth connecting terminal 1123.

[0056] The fourth connection terminal 1112 is electrically connected to the fifth connection terminal 1123, thereby electrically connecting the first transistor 1 and the second transistor 2. This allows a DC signal to be input from the first connection terminal 1111 via the first copper busbar 201, then through the first transistor 1, and finally out through the third copper busbar 203 (the AC terminal); or a DC signal to be input from the third connection terminal 1122 via the second copper busbar 202, then through the second transistor 2, and finally out through the third copper busbar 203 (the AC terminal), thus achieving inversion. It should be noted that when the inverter is working, the first transistor 1 and the second transistor 2 are not turned on simultaneously.

[0057] Based on the foregoing embodiments, in one embodiment of this application, such as Figure 6 As shown, the first package structure 111 further includes at least one first connection layer 1113. The first transistor 1 is located on the surface of the first connection layer 1113 and is electrically connected to the first connection terminal 1111 through the first connection layer 1113. Specifically, the first transistor 1 is located one-to-one on the surface of the first connection layer 1113, and a portion of the first connection terminal 1111 is located on the surface of the first connection layer, while the other portion extends outward from the first package structure 111 through the molding layer, so that the first transistor 1 is electrically connected to the first connection terminal 1111 and electrically connected to the first copper busbar 201 through the first connection terminal 1111.

[0058] The second package structure 112 also has at least one second connection layer 1124, with the second transistor 2 corresponding to the second connection layer 1124, located on the surface of the second connection layer 1124, electrically connected to the third connection terminal 1122 through the second connection layer 1124, and electrically connected to the fifth connection terminal 1123.

[0059] Specifically, the second transistor 2 is located on the surface of the second connection layer 1124, and the third connection terminal 1122 and the fifth connection terminal 1123 are respectively located on two sides of the second transistor 2 along the first direction. Among them, the third connection terminal 1122 is located on the side away from the first packaging structure 111, and a part of the third connection terminal 1122 is located on the surface of the second connection layer 1124, and the other part extends to the outside of the second packaging structure 112 through the plastic sealing layer, so that the second transistor 2 is electrically connected with the third connection terminal 1122, and is electrically connected with the third copper bar 203 through the third connection terminal 1122. The fifth connection terminal 1123 is located on the side towards the first packaging structure 111, and a part of the fifth connection terminal 1123 is located on the surface of the second connection layer 1124, and the other part extends to the outside of the second packaging structure 112 through the plastic sealing layer, so that the second transistor 2 is electrically connected with the fifth connection terminal 1123, and is electrically connected with the fourth connection terminal 1112 through the fifth connection terminal 1123, thereby the first transistor 1 and the second transistor 2 are electrically connected. It should be noted that one end of the second connection terminal 1121 is directly electrically connected to the second transistor 2, and extends to the outside of the second packaging structure 112 through the plastic sealing layer, and the other end is electrically connected with the second copper bar 202.

[0060] It should be noted that the first packaging structure 111 can include a copper clad ceramic substrate, and the above-mentioned first connection layer 1113 is a copper clad layer on one side of the copper clad ceramic substrate. Similarly, the second packaging structure 112 can include a copper clad ceramic substrate, and the above-mentioned second connection layer 1124 is a copper clad layer on one side of the copper clad ceramic substrate. It should also be noted that it should be understood that the inverter can also include a common substrate (not shown in the drawings), and the packaging structure 110 and the direct current bus capacitor 300 can be located on the common substrate.

[0061] Based on the foregoing embodiment, in an embodiment of the present application, the first transistor 1 is a MOS field effect transistor, and the second transistor 2 is a MOS field effect transistor.

[0062] Specifically, the drain of the first transistor 1 is electrically connected with the first connection terminal 1111, and the source of the first transistor 1 is electrically connected with the fourth connection terminal 1112.

[0063] The source of the second transistor 2 is electrically connected with the second connection terminal 1121, the drain of the second transistor 2 is electrically connected with the third connection terminal 1122, and the drain of the second transistor 2 is also electrically connected with the fifth connection terminal 1123.

[0064] In another embodiment of the present application, the first transistor 1 is composed of an IGBT (Insulated Gate Bipolar Transistor, IGBT for short) and a diode, wherein the positive electrode of the diode is electrically connected with the collector of the IGBT, and the negative electrode of the diode is electrically connected with the emitter of the IGBT. The second transistor 2 is composed of an IGBT and a diode, wherein the positive electrode of the diode is electrically connected with the collector of the IGBT, and the negative electrode of the diode is electrically connected with the emitter of the IGBT. It should be noted that in order to provide a reverse conduction path for the IGBT, a diode is generally anti-parallel connected with the IGBT, so the first transistor 1 and the second transistor 2 are composed of an IGBT and a diode.

[0065] Specifically, the collector of the first transistor 1 is electrically connected with the first connection terminal 1111, and the emitter of the first transistor 1 is electrically connected with the fourth connection terminal 1112.

[0066] The emitter of the second transistor 2 is electrically connected with the second connection terminal 1121, the collector of the second transistor 2 is electrically connected with the third connection terminal 1122, and the collector of the second transistor 2 is also electrically connected with the fifth connection terminal 1123.

[0067] From the above, it can be seen that for the inverter provided by the present application, the type of transistor can be various, and can be flexibly selected according to actual conditions, and the practicability is high.

[0068] Correspondingly, the present application also provides a power electronic device, which comprises the inverter described in any of the above embodiments.

[0069] In summary, the application provides an inverter and a power electronic device, the inverter comprising: a packaging structure, a first copper bar to a third copper bar. The packaging structure comprises a first packaging structure having at least one first transistor and a second packaging structure having at least one second transistor, the first packaging structure further having a first connecting terminal electrically connected to the first transistor, and the second packaging structure further having a second connecting terminal and a third connecting terminal electrically connected to the second transistor. The first copper bar is located on the side of the first packaging structure away from the second packaging structure and is electrically connected to the first transistor through the first connecting terminal. The second copper bar extends in a first direction and is arranged in sequence with the packaging structure in a second direction and is electrically connected to the second transistor through the second connecting terminal. The third copper bar is located on the side of the second packaging structure away from the first packaging structure and is electrically connected to the second transistor through the third connecting terminal. Wherein the first copper bar and the second copper bar are direct current input and output terminals respectively, and the third copper bar is an alternating current output terminal, and the projection of the second copper bar along the second direction does not overlap with the projection of the third copper bar along the second direction. As can be seen, the direct current busbar composed of the first copper bar and the second copper bar does not overlap with the alternating current busbar composed of the third copper bar in the projection along the first direction, thereby achieving the purpose of spatial separation of the direct current busbar and the alternating current busbar, avoiding the formation of alternating current busbar and direct current busbar, having a good effect of reducing parasitic inductance, and can also reduce the design difficulty of copper bar and simplify the production process.

[0070] The various embodiments in the specification are described in a progressive, or parallel, or progressive and parallel combination manner, and each embodiment focuses on the difference from other embodiments. The same or similar regions of each embodiment can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the related parts can be referred to the method area description.

[0071] It should be noted that in the description of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation on the present application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there can be a component disposed therebetween.

[0072] It is also noted that the relational terms herein, such as first and second, and the like, are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a vesicle or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such vesicle or apparatus. An element proceeded by "comprises a... " does not, without more constraints, preclude the existence of additional identical elements in the vesicle or apparatus that comprises the recited element.

[0073] The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An inverter, characterized in that, include: The encapsulation structure includes a first encapsulation structure and a second encapsulation structure arranged along a first direction, wherein the first direction is parallel to the mounting surface of the encapsulation structure. The first package structure has at least one first transistor, and the second package structure has at least one second transistor, with the first transistor and the second transistor being electrically connected in a one-to-one correspondence; wherein, the first package structure also has at least one first connection terminal, with the first transistor being electrically connected in a one-to-one correspondence with the first connection terminal, and the second package structure also has at least one second connection terminal and at least one third connection terminal, with the second transistor being electrically connected in a one-to-one correspondence with the second connection terminal, and the second transistor also being electrically connected in a one-to-one correspondence with the third connection terminal. The first copper busbar is located on the side of the first packaging structure opposite to the second packaging structure and is electrically connected to the first transistor through the first connection terminal. The second copper busbar extends along the first direction and is arranged with the package structure along the second direction, and the second copper busbar is electrically connected to the second transistor through the second connection terminal; wherein, the second direction is perpendicular to the mounting surface of the package structure, the first copper busbar is the DC input terminal of the inverter, and the second copper busbar is the output terminal of the DC circuit of the inverter; The third copper busbar is located on the side of the second packaging structure opposite to the first packaging structure, and is electrically connected to the second transistor through the third connection terminal. The third copper busbar is the AC output terminal of the inverter. The projection of the second copper busbar along the second direction does not overlap with the projection of the third copper busbar along the second direction.

2. The inverter according to claim 1, characterized in that, Also includes: A DC bus capacitor, wherein the DC bus capacitor is located on the side of the first package structure opposite to the second package structure, and has a positive connection terminal and a negative connection terminal; The positive terminal is electrically connected to the first copper busbar. The negative terminal is electrically connected to the second copper busbar.

3. The inverter according to claim 1, characterized in that, The projection of the second copper busbar along the second direction covers the projection of the first package structure along the second direction, and also covers the projection of the area in the second package structure other than the third connection terminal along the second direction.

4. The inverter according to claim 3, characterized in that, The first packaging structure also has at least one fourth connection terminal, and the second packaging structure also has at least one fifth connection terminal; The first transistor is also electrically connected to the fourth connection terminal in a corresponding manner, and the second transistor is also electrically connected to the fifth connection terminal in a corresponding manner. The fourth connection terminal is electrically connected to the fifth connection terminal in a one-to-one correspondence, so that the first transistor and the second transistor are electrically connected in a one-to-one correspondence.

5. The inverter according to claim 4, characterized in that, The first package structure further includes at least one first connection layer, the first transistor is located on the surface of the first connection layer, and is electrically connected to the first connection terminal through the first connection layer; The second package structure further includes at least one second connection layer, the second transistor is located on the surface of the second connection layer, and is electrically connected to the third connection terminal and the fifth connection terminal through the second connection layer.

6. The inverter according to claim 4, characterized in that, The first transistor is a MOS field-effect transistor, and the second transistor is a MOS field-effect transistor.

7. The inverter according to claim 6, characterized in that, The drain of the first transistor is electrically connected to the first connection terminal, and the source of the first transistor is electrically connected to the fourth connection terminal. The source of the second transistor is electrically connected to the second connection terminal, the drain of the second transistor is electrically connected to the third connection terminal, and the drain of the second transistor is also electrically connected to the fifth connection terminal.

8. The inverter according to claim 4, characterized in that, The first transistor is composed of an IGBT transistor and a diode. The positive terminal of the diode is electrically connected to the collector of the IGBT transistor, and the negative terminal of the diode is electrically connected to the emitter of the IGBT transistor. The second transistor is composed of an IGBT transistor and a diode. The positive terminal of the diode is electrically connected to the collector of the IGBT transistor, and the negative terminal of the diode is electrically connected to the emitter of the IGBT transistor.

9. The inverter according to claim 8, characterized in that, The collector of the first transistor is electrically connected to the first connection terminal, and the emitter of the first transistor is electrically connected to the fourth connection terminal. The emitter of the second transistor is electrically connected to the second connection terminal, the collector of the second transistor is electrically connected to the third connection terminal, and the collector of the second transistor is also electrically connected to the fifth connection terminal.

10. A power electronic device, characterized in that, Inverter including any one of claims 1-9 above.

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