Semiconductor device and electronic equipment

Abstract

The utility model provides a semiconductor device and an electronic device, and relates to the field of semiconductors, the semiconductor device comprises at least one single-core power half-bridge, and a ceramic substrate, an upper tube chip, an upper tube D terminal, a lower tube S terminal, a lower tube chip and an AC connecting copper bar in each single-core power half-bridge are arranged in an up-and-down lamination mode. The vertical lamination mode effectively shortens the distance between the conductive parts, thereby remarkably reducing the parasitic inductance of the device and the whole power system, reducing the problems of energy loss, signal distortion, electromagnetic interference and the like, and further promoting the improvement of the efficiency and reliability of the system.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor technology field, concretely relates to a semiconductor device and electronic equipment. BACKGROUND

[0002] Power semiconductor device is a kind of semiconductor device that can withstand large current and high voltage, mainly used in the large power (usually refers to the current is dozens to several thousand ampere, voltage is several hundred volts above) electronic device in electric energy conversion and electric energy control circuit.

[0003] Figure 1 It is a kind of power semiconductor device packaging design scheme schematic diagram in prior art, Figure 1 The technical scheme shown in the figure, the packaging structure of power semiconductor device does not adopt up-down laminated packaging design, so that the parasitic inductance generated when terminal is connected is higher. UTILITY MODEL CONTENTS

[0004] Therefore, the utility model embodiment provides a laminated design semiconductor device to reduce its parasitic inductance.

[0005] To achieve the above object, the utility model embodiment provides the following technical scheme:

[0006] A semiconductor device, comprising:

[0007] At least one single-core power half-bridge;

[0008] The single-core power half-bridge comprises:

[0009] Ceramic substrate;

[0010] Upper tube chip, the upper tube chip is arranged on the upper tube ceramic substrate first copper clad layer of the ceramic substrate;

[0011] Lower tube chip, the lower tube chip is arranged on the lower tube ceramic substrate first copper clad layer of the ceramic substrate, and the S pole of the upper tube chip is connected with the D pole of the lower tube chip through upper tube S pole connecting conductor;

[0012] Upper tube D pole terminal, one end of the upper tube D pole terminal is connected with the upper tube ceramic substrate first copper clad layer;

[0013] AC connection copper bar, the AC connection copper bar is connected with the D pole of the lower tube chip through the lower tube ceramic substrate first copper clad layer of the ceramic substrate;

[0014] Lower tube S pole terminal, the lower tube S pole terminal is connected with the S pole of the lower tube chip through lower tube S pole connecting conductor, and the lower tube S pole terminal is laminated with the upper tube D pole terminal;

[0015] The D poles of the upper chip of each single-core power half-bridge are connected with equal impedance, the S poles of the upper chip of each single-core power half-bridge are connected with equal impedance, the D poles of the lower chip of each single-core power half-bridge are connected with equal impedance, and the S poles of the lower chip of each single-core power half-bridge are connected with equal impedance.

[0016] Optionally, in the semiconductor device, an insulating layer is coated on the region of the upper chip which is not connected with the first copper layer of the upper ceramic substrate and the upper S pole connecting conductor.

[0017] An insulating layer is coated on the region of the lower chip which is not connected with the first copper layer of the upper ceramic substrate and the lower S pole connecting conductor.

[0018] Optionally, in the semiconductor device, the upper D pole terminal, the lower S pole terminal and the AC connecting copper bar of each single-core power half-bridge are shared.

[0019] Optionally, in the semiconductor device, the upper D pole terminal and the lower S pole terminal are distributed on the first side of the semiconductor device, and the AC connecting copper bar is arranged on the second side of the semiconductor device, the first side and the second side being two symmetrical sides of the semiconductor device.

[0020] The monitoring terminal and the temperature detecting element of the semiconductor device are arranged on the third side or the fourth side of the semiconductor device, the first side, the second side, the third side and the fourth side being four side edges of the semiconductor device.

[0021] Optionally, in the semiconductor device, the monitoring terminal comprises:

[0022] an upper D pole monitoring terminal, an upper G pole terminal, an upper S pole terminal, a lower G pole terminal, a lower S pole terminal, a first temperature detecting terminal and a second temperature detecting terminal.

[0023] The first temperature detecting terminal and the second temperature detecting terminal are connected with the input terminal and the output terminal of the temperature detecting element respectively, and are used to provide a temperature detecting signal to an external detecting unit.

[0024] Optionally, in the semiconductor device, the first temperature detecting terminal, the second temperature detecting terminal and the temperature detecting element are arranged on the third side of the semiconductor device.

[0025] The upper D pole monitoring terminal, the upper G pole terminal, the upper S pole terminal, the lower G pole terminal and the lower S pole terminal are arranged on the fourth side of the semiconductor device.

[0026] Optionally, in the semiconductor device, further comprising:

[0027] a heat sink.

[0028] The heat sink is disposed on a side of the ceramic substrate distal from the upper and lower dies.

[0029] Optionally, in the semiconductor device described above, the lower S pole connecting conductor and the upper S pole connecting conductor are flexible layer connecting conductors.

[0030] An electronic device comprising a power device made of any of the semiconductor devices described above, the electronic device being a car.

[0031] Based on the technical solutions described above, the semiconductor device provided in the embodiments of the present application includes at least one single-core power half-bridge, the ceramic substrate, the upper die, the upper die D pole terminal, the lower die S pole terminal, the lower die, and the AC connecting copper bar in each single-core power half-bridge are disposed in an up-down stacking manner, thereby realizing efficient stacking of the conductive components. This design not only optimizes the performance and efficiency of the system, but also significantly improves the space utilization and integration. Through accurate manufacturing and assembly processes, the conductive components are accurately stacked together to form a continuous conductive path, ensuring the physical and electrical integrity of the stacked structure. Not only does this help reduce the size and weight of the system, but it also enhances the connection reliability and stability between the conductive components. More importantly, the up-down stacking manner effectively shortens the distance between the conductive components, thereby significantly reducing the parasitic inductance of the device itself and the entire power system, reducing energy loss, signal distortion, and electromagnetic interference, and further improving the efficiency and reliability of the system. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0033] Figure 1 A design scheme diagram of the power semiconductor device package and the power system disclosed in the prior art;

[0034] Figure 2 A circuit topology diagram of the existing inverter main power system;

[0035] Figure 3 A circuit symbol of IGBT;

[0036] Figure 4 A chip structure diagram of IGBT;

[0037] Figure 5 An electrical symbol of MOSFET;

[0038] Figure 6 A schematic diagram of a chip structure of a MOSFET;

[0039] Figure 7 A sectional view of a single-core power half-bridge in a semiconductor device disclosed by an embodiment of the present application;

[0040] Figure 8 A schematic diagram of a structure of a semiconductor device disclosed by an embodiment of the present application;

[0041] Figure 9 A side view of a semiconductor device disclosed by an embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0043] First, the related terms in the present application are explained:

[0044] Power electronics: a device composed of power semiconductor devices, passive devices (inductors, capacitors), structural components, heat dissipation systems and control devices, which can realize conversion and control of electric energy.

[0045] Power system: a system composed of high-voltage and high-power parts in a power electronic converter device, mainly including power semiconductor devices, passive devices (inductors or capacitors), electrical connection components (such as copper bars, wires, etc.).

[0046] Power semiconductor chip: made of semiconductor materials such as silicon (Si), silicon carbide (SiC) and gallium nitride (GaN), which can realize conversion and control of electric energy through fast turn-on and turn-off, mainly including IGBT (usually made of Si), MOSFET (usually made of Si, SiC and GaN), diode (made of Si or SiC), etc. The present application is referred to as "chip".

[0047] Power semiconductor packaging: the power semiconductor chip cannot be used directly and must be installed in a module through a series of process to realize the connection between chips, the electrical connection of chips to the outside, the heat dissipation of chips, the protection of chips (insulation, waterproof, dustproof, oxidation prevention, mechanical damage prevention) and other functions. The structure of the module is called power semiconductor packaging. In the present application, it is referred to as "packaging".

[0048] Power semiconductor device: a module composed of a power semiconductor chip and a power semiconductor package is called a power semiconductor device. This application is abbreviated as "device".

[0049] Inverter: a power electronic device that converts DC power into AC power, whose main power system is as shown in Figure 2 . Figure 2 The left side is the DC input of the inverter, which is generally a DC power supply such as a battery, Figure 2 The right side is the AC output. The inverter is composed of a three-phase inverter bridge arm, and power semiconductor devices S1 and S2 (MOSFETs shown in the figure) form an A-phase inverter bridge arm. S1 is the upper tube of the inverter bridge arm, and the D terminal of S1 is connected to the DC+ bus; S2 is the lower tube of the inverter bridge arm, and the S terminal of S2 is connected to the DC- bus. Point A is the connection point of the S terminal of S1 and the D terminal of S2, which is the AC output point of the A-phase inverter bridge arm; S1 and S2 are alternately and complementarily turned on, and can output AC voltage at point A. Similarly, the working principles of B-phase and C-phase are the same.

[0050] IGBT: Insulated Gate Bipolar Transistor, a kind of power semiconductor device, whose symbol is as shown in Figure 3 and Figure 4 . IGBT has three terminals, collector (C terminal), emitter (E terminal) and gate (G terminal). When the voltage between the G terminal and the E terminal exceeds a certain value (threshold voltage), the IGBT is turned on, and the current can flow from the C terminal to the E terminal, but not in the reverse direction. In order to provide a path for reverse conduction of IGBT, a diode is generally connected in anti-parallel with the IGBT.

[0051] MOSFET: Metal Oxide Semiconductor FET, a kind of power semiconductor device, whose symbol is as shown in Figure 5 and Figure 6 . MOSFET has three terminals, drain (D terminal), source (S terminal) and gate (G terminal). When the voltage between the G terminal and the S terminal exceeds a certain value (threshold voltage), the MOSFET is turned on, and the current can flow from the D terminal to the S terminal. Due to the structure of MOSFET, there is a reverse-parallel diode, so whether the MOSFET is in the on state or not, the current can flow from the S terminal to the D terminal.

[0052] Referring to Figure 7 and Figure 8 , the present application discloses a power semiconductor device, comprising:

[0053] at least one single-core power half-bridge 100;

[0054] The single-core power half-bridge 100 comprises:

[0055] A ceramic substrate, comprising: a ceramic substrate second copper clad layer 121, a ceramic substrate ceramic layer 119 arranged on the ceramic substrate second copper clad layer 121, an upper tube ceramic substrate first copper clad layer 118 and a lower tube ceramic substrate first copper clad layer 120 arranged on the side of the ceramic substrate ceramic layer 119 away from the ceramic substrate second copper clad layer 121;

[0056] An upper tube chip 107 arranged on the upper tube ceramic substrate first copper clad layer 118;

[0057] A lower tube chip 115 arranged on the lower tube ceramic substrate first copper clad layer 120, and the S pole of the upper tube chip 107 is connected to the D pole of the lower tube chip 115 through an upper tube S pole upper tube flexible layer connection conductor 110;

[0058] An upper tube D pole terminal 102, one end of which is connected to the upper tube ceramic substrate first copper clad layer 118, the upper tube ceramic substrate first copper clad layer 118 and the lower tube ceramic substrate first copper clad layer 120 are arranged on the same side of the ceramic substrate ceramic layer 119 and are in the same horizontal plane, and the upper tube ceramic substrate first copper clad layer 118 and the lower tube ceramic substrate first copper clad layer 120 are electrically isolated, and in the process of generating the upper tube ceramic substrate first copper clad layer 118 and the lower tube ceramic substrate first copper clad layer 120, a first copper clad layer can be generated directly on the ceramic substrate ceramic layer 119, and then the first copper clad layer is divided into two independent regions by etching, one of which is the upper tube ceramic substrate first copper clad layer 118, and the other is the lower tube ceramic substrate first copper clad layer 120;

[0059] An alternating current connection copper bar 117 connected to the D pole of the lower tube chip 115 through the lower tube ceramic substrate first copper clad layer 120 of the ceramic substrate;

[0060] A lower tube S pole terminal 103 connected to the S pole of the lower tube chip 115 through a lower tube S pole lower tube flexible layer connection conductor 111, and the lower tube S pole terminal 103 is arranged in a stack with the upper tube D pole terminal 102;

[0061] The D pole of the upper tube chip of each single-core power half-bridge is connected with impedance equal to each other, the S pole of the upper tube chip of each single-core power half-bridge is connected with impedance equal to each other, the D pole of the lower tube chip of each single-core power half-bridge is connected with impedance equal to each other, and the S pole of the lower tube chip of each single-core power half-bridge is connected with impedance equal to each other.

[0062] The design of the lower tube S pole terminal 103 and the upper tube D pole terminal 102 in a stacked manner facilitates the integration of the semiconductor device with an external power supply, a bus capacitor and the like, ensures the integrity of the stacked part of the system design, and further reduces the parasitic inductance of the power integrated system. Meanwhile, the copper bar connection in the design scheme can be welded, the welding process is easy to implement, the difficulty of power system design is reduced, and the production process is simplified.

[0063] In the above structure, the upper tube D pole terminal 102, the sintered silver welding area 105 and the first copper layer 118 of the upper tube ceramic substrate together constitute the D pole passage 123 of the upper tube chip, realize the electrical connection function of the D pole of the upper tube chip, the sintered silver welding area 106, the upper tube S pole flexible layer connecting conductor 110 and the sintered silver welding area 112 together constitute the S pole passage 124 of the upper tube chip and the D pole of the lower tube chip 115, realize the electrical connection function of the S pole of the upper tube chip, and the lower tube S pole passage 125 is composed of the lower tube S pole terminal 103, the sintered silver welding area 104, the lower tube S pole flexible layer connecting conductor 111 and the sintered silver welding area 114, realizes the electrical connection function of the S pole of the lower tube chip, and the lower tube chip D pole connection passage 126 is composed of the sintered silver welding area 113, the first copper layer 120 of the lower tube ceramic substrate and the alternating current connection copper bar 117, realizes the electrical connection function of the D pole of the lower tube chip.

[0064] As can be seen from the above structure, the packaging structure of the power semiconductor device is mainly divided into two layers, the lower layer is connected with the positive electrode of the external power supply through the upper tube D pole terminal 102, and the current flows through the conductive components in turn 123, 107, 124, 120, 117, and finally connected with the outside through the alternating current connection copper bar (117), and the upper layer flows back to the negative electrode of the external power supply through the lower tube S pole terminal 103, the current of the upper layer flows through the conductive components 126, 115, 125, and realizes the electrical connection of 103 and 117. The upper layer passage and the lower layer passage are arranged in the vertical space, and the electromagnetic field generated thereby can be offset, thereby reducing the parasitic inductance of the entire power half-bridge.

[0065] As can be seen from the above scheme, the semiconductor device disclosed in the above embodiment of the present application comprises at least one single-core power half-bridge, the ceramic substrate, the upper tube chip, the upper tube D terminal, the lower tube S terminal, the lower tube chip and the AC connection copper bar in each single-core power half-bridge are arranged in an up-down stacking manner, realizing efficient stacking of the conductive components. This design not only optimizes the performance and efficiency of the system, but also significantly improves the space utilization and integration. Through precise manufacturing and assembly process, the various conductive components are accurately stacked together to form a continuous conductive path, ensuring the physical and electrical integrity of the stacked structure. Not only helps to reduce the size and weight of the system, but also enhances the connection reliability and stability between the conductive components. More importantly, the up-down stacking manner effectively shortens the distance between the conductive components, thereby significantly reducing the parasitic inductance of the device itself and the entire power system, reducing energy loss, signal distortion and electromagnetic interference, and further improving the efficiency and reliability of the system.

[0066] In the present embodiment, the distance between the lower tube chip 115 and the upper tube D terminal 102 and the lower tube S terminal 103 is greater than the distance between the upper tube chip 107 and the upper tube D terminal 102 and the lower tube S terminal 103, as shown in Figure 7 When the upper tube D terminal 102 and the lower tube S terminal 103 are located on the left side of the packaging structure, the lower tube chip 115 is located on the right side of the upper tube chip 107, and when the upper tube D terminal 102 and the lower tube S terminal 103 are located on the right side of the packaging structure, the lower tube chip 115 is located on the left side of the upper tube chip 107, thereby making the current path in the packaging module shorter and further reducing the size of the parasitic capacitance.

[0067] In the present embodiment, in order to ensure the reliability of the semiconductor device and prevent the upper tube chip 107 and the lower tube chip 115 in the semiconductor device from short-circuiting and other problems, referring to Figure 7 , the area of the upper tube chip 107 that is not connected to the upper tube ceramic substrate first copper clad layer 118 and the upper tube S terminal upper tube flexible layer connection conductor 110 is covered with an insulating layer, and the area of the lower tube chip 115 that is not connected to the lower tube ceramic substrate first copper clad layer 120 and the lower tube S terminal lower tube flexible layer connection conductor 111 is covered with an insulating layer. In the present application, the material of the insulating layer can be selected according to design requirements as long as it can achieve electrical isolation, for example, in the present scheme, the material of the insulating layer can be polyimide, which has high dielectric strength and good electrical insulation performance, can effectively prevent current leakage and electromagnetic interference, and ensure the safety and reliability of the chip.

[0068] Figure 7In the embodiment, 108, 109, 116 are insulating layers, in the embodiment, the material of the insulating layers can be selected from polyimide, polyimide 109 plays a role of insulating protection for the upper tube chip 107, polyimide 116 plays a role of insulating protection for the lower tube chip 115, and polyimide 108 plays a role of insulating protection for 110 and 111.

[0069] In the technical solution disclosed in the embodiment, the semiconductor device can include a plurality of single-core power half bridges, and the structure of each single-core power half bridge can be as shown in Figure 7 Further, the arrangement mode of each single-core power half bridge can be set according to user design requirements, for example, as shown in Figure 8 Each single-core power half bridge can share the same upper tube D terminal, lower tube S terminal and AC connection copper bar.

[0070] In the technical solution disclosed in the embodiment, in order to improve the consistency of each single-core power half bridge, the related impedances of each single-core power half bridge need to be kept equal, which can include the D terminal connection impedance of the upper tube chip, the S terminal connection impedance of the upper tube chip, the D terminal connection impedance of the lower tube chip and the S terminal connection impedance of the lower tube chip, that is, the D terminal connection impedance of the upper tube chip of each single-core power half bridge is equal, the S terminal connection impedance of the upper tube chip of each single-core power half bridge is equal, the D terminal connection impedance of the lower tube chip of each single-core power half bridge is equal, and the S terminal connection impedance of the lower tube chip of each single-core power half bridge is equal.

[0071] In the embodiment, the D terminal connection impedance of the upper tube chip of each single-core power half bridge can be realized by making the distance of the upper tube D terminal path 123 of the upper tube chip in all single-core power half bridges equal, as shown in Figure 7 The upper tube D terminal path 123 is composed of the upper tube D terminal 102, sintered silver 105 (the connection area of the upper tube chip and the first copper coating layer of the upper tube ceramic substrate) and the first copper coating layer 118 of the upper tube ceramic substrate, in order to realize the equal length of the upper tube D terminal path 123 of the upper tube chip of each single-core power half bridge, the length of the upper tube D terminal in each single-core power half bridge needs to be equal, the size of the connection area of the upper tube chip and the first copper coating layer of the upper tube ceramic substrate in each single-core power half bridge needs to be equal (in the following table 1, the upper tube chip and the first copper coating layer of the upper tube ceramic substrate are connected by sintered silver welding), and the length of the first copper coating layer of the upper tube ceramic substrate in each single-core power half bridge needs to be equal.

[0072] In the embodiment, the S terminal connection impedance of the upper tube chip of each single-core power half bridge can be realized by making the distance of the upper tube chip S terminal path 124 in all single-core power half bridges equal, as shown in Figure 7The upper tube chip S pole passage 124 is composed of sintered silver 106 (connection area of the upper tube S pole connecting conductor and the upper tube chip), connecting conductor 110 and sintered silver 112 (connection area of the upper tube S pole connecting conductor and the first copper coating layer of the lower tube ceramic substrate), in order to make the length of the upper tube chip S pole passage 124 of each single-core power half-bridge equal, the length of the upper tube S pole connecting conductor in each single-core power half-bridge needs to be made equal, the size of the connection area of the upper tube S pole connecting conductor and the upper tube chip in each single-core power half-bridge needs to be made the same, and the size of the connection area of the upper tube S pole connecting conductor and the first copper coating layer of the lower tube ceramic substrate in each single-core power half-bridge needs to be made the same.

[0073] In the embodiment, the D pole connection impedance of the lower tube chip of each single-core power half-bridge can be made equal by making the distance of the lower tube chip lower tube D pole passage 126 in all single-core power half-bridges equal, as shown in Figure 7 , the lower tube D pole passage 126 is composed of sintered silver 113 (connection area of the lower tube chip and the first copper coating layer of the lower tube ceramic substrate), the first copper coating layer of the lower tube ceramic substrate 120 and the alternating current connecting copper bar 117, in order to make the length of the lower tube chip upper tube D pole passage 126 of each single-core power half-bridge equal, the size of the connection area of the lower tube chip and the first copper coating layer of the lower tube ceramic substrate in each single-core power half-bridge needs to be made equal (in Table 1 below, the lower tube chip and the first copper coating layer of the lower tube ceramic substrate are welded by sintered silver), the length of the first copper coating layer of the lower tube ceramic substrate in each single-core power half-bridge needs to be made equal, and the length of the alternating current connecting copper bar in each single-core power half-bridge needs to be made equal.

[0074] In the embodiment, the S pole connection impedance of the lower tube chip of each single-core power half-bridge can be made equal by making the distance of the lower tube chip S pole passage 125 in all single-core power half-bridges equal, as shown in Figure 7 , the lower tube chip S pole passage 125 is composed of the lower tube S pole terminal 103, sintered silver 104 (connection area of the lower tube S pole connecting conductor and the lower tube S pole terminal), lower tube flexible layer connecting conductor 111 and sintered silver 114 (connection area of the lower tube chip and the lower tube S pole connecting conductor), in order to make the length of the lower tube chip S pole passage 125 of each single-core power half-bridge equal, the length of the lower tube S pole terminal in each single-core power half-bridge needs to be made equal, the size of the connection area of the lower tube S pole connecting conductor and the lower tube S pole terminal needs to be made the same, the length of the lower tube S pole connecting conductor needs to be made equal, and the size of the connection area of the lower tube chip and the lower tube S pole connecting conductor needs to be made the same.

[0075] By configuring the upper tube D pole passage 123, the upper tube chip S pole passage 124, the lower tube chip S pole passage 125 and the lower tube D pole passage 126 in the above manner, balanced design of the chip parallel electrical connection impedance is realized, and the current sharing consistency between the single-core power half-bridges is improved.

[0076] In the technical solution disclosed in the embodiment, in order to facilitate the connection of the semiconductor device and external devices, the distribution positions of each connection terminal in the semiconductor device can also be planned. Specifically, the upper tube D pole terminal and the lower tube S pole terminal are distributed on the first side of the semiconductor device, the AC connection copper bar is arranged on the second side of the semiconductor device, and the first side and the second side are symmetrical sides of the semiconductor device; the monitoring terminal and the temperature detection element of the semiconductor device are arranged on the third side or the fourth side of the semiconductor device, and the first side, the second side, the third side and the fourth side are four sides of the semiconductor device, and the first side, the second side, the third side and the fourth side form a closed rectangular area.

[0077] In the embodiment, the monitoring terminal includes an upper tube D pole monitoring terminal 202, an upper tube G pole terminal 204, an upper tube S pole terminal 206, a lower tube G pole terminal 208, a lower tube S pole terminal 210, a first temperature detection terminal 212 and a second temperature detection terminal 214; wherein the first temperature detection terminal 212 and the second temperature detection terminal are connected to the input end and the output end of the temperature detection element respectively, and are used to provide a temperature detection signal to an external detection unit.

[0078] The upper tube D pole monitoring terminal 202 is connected to the first copper clad layer 118 of the upper tube ceramic substrate through an upper tube D pole monitoring terminal connecting conductor, the upper tube G pole terminal 204 is connected to the G pole of each upper tube chip 107 through an upper tube G pole monitoring terminal connecting conductor 203, the upper tube S pole terminal 206 is connected to the S pole of each upper tube chip 107 through an upper tube S pole monitoring terminal connecting conductor 205, the lower tube G pole terminal 208 is connected to the G pole of each lower tube chip through a lower tube G pole monitoring terminal connecting conductor 207, and the lower tube S pole terminal 210 is connected to the S pole of each lower tube chip 115 through a lower tube S pole monitoring terminal connecting conductor 207.

[0079] In the embodiment, the monitoring terminals of the semiconductor device and the temperature detecting element are arranged in the side direction of the electrical connection terminals (102, 103 and 117), for example, the temperature detecting element 213, the first temperature monitoring terminal (the first temperature detecting terminal 212 and the second temperature detecting terminal 214), and the second control monitoring terminal are arranged on the right side of the electrical connection terminals, or are arranged on the left side of the electrical connection terminals, the first temperature detecting terminal and the second temperature detecting terminal are connected with the input terminal and the output terminal of the temperature detecting element respectively, and are used to provide the temperature detecting signal to the external detecting unit, see Figure 9 These monitoring terminals can be led out from the top or the side of the package shell 101 of the semiconductor device, the side is the third side or the fourth side. Of course, the temperature detecting element 213 and the first temperature monitoring terminal and the second control monitoring terminal can also be arranged on both sides of the electrical connection terminals, for example, the temperature detecting element 213 and the first temperature monitoring terminal are arranged on the left side of the electrical connection terminals, and the second control monitoring terminal is arranged on the right side of the electrical connection terminals, or the temperature detecting element 213 and the first temperature monitoring terminal are arranged on the right side of the electrical connection terminals, and the second control monitoring terminal is arranged on the left side of the electrical connection terminals.

[0080] In the embodiment, the material of the lower tube S pole connecting conductor and the upper tube S pole connecting conductor can be selected according to the design requirement, for example, the flexible layer connecting conductor can be used.

[0081] In the embodiment, in order to make the semiconductor device have excellent heat dissipation effect, the semiconductor device further comprises a heat sink 122; the heat sink 122 is arranged on the side of the ceramic substrate away from the lower tube ceramic substrate, the ceramic substrate is in direct contact with the heat sink for heat dissipation, the heat transfer thermal resistance is low, and the heat dissipation efficiency of the device can be improved.

[0082] In the embodiment, the heat sink 122 of the semiconductor device is fixed on the package shell 101, and a mechanical fixing terminal 211 can also be arranged on the heat sink 122, and one mechanical fixing terminal 211 is arranged on each corner of the heat sink 122.

[0083] In a specific embodiment, the composition of the semiconductor device and the label, name and function of each component are shown in Table 1:

[0084]

[0085]

[0086]

[0087] Table 1

[0088] An electronic device including the semiconductor device described in any one of the above embodiments, the electronic device being a home appliance or a car.

[0089] It should be noted that each of the above-described embodiments can be implemented in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be mutually referred to.

[0090] It should also be noted that the terms such as first and second, etc., are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or sequence between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, and also include other elements not explicitly listed, or further include elements inherent to such an article or device. Without more limitations, the element defined by the phrase "including a" does not exclude the presence of other identical elements in the article or device including the element.

[0091] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application should not be limited to the embodiments shown herein, but should be consistent with the widest scope of the principles and novel features disclosed herein.

[0092] The above description is only the preferred embodiments of the present application. It should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A semiconductor device, characterized by, Comprising: at least one single-core power half-bridge; the single-core power half-bridge comprising: a ceramic substrate; an upper tube chip disposed on an upper tube ceramic substrate first copper clad layer of the ceramic substrate; a lower tube chip disposed on a lower tube ceramic substrate first copper clad layer of the ceramic substrate, an S pole of the upper tube chip being connected to a D pole of the lower tube chip through an upper tube S pole connecting conductor; an upper tube D pole terminal, one end of the upper tube D pole terminal being connected to the upper tube ceramic substrate first copper clad layer; an alternating current connecting copper bar, the alternating current connecting copper bar being connected to the D pole of the lower tube chip through the lower tube ceramic substrate first copper clad layer of the ceramic substrate; a lower tube S pole terminal, the lower tube S pole terminal being connected to the S pole of the lower tube chip through a lower tube S pole connecting conductor, the lower tube S pole terminal being disposed in a stack with the upper tube D pole terminal; wherein a D pole connecting impedance of the upper tube chip of each single-core power half-bridge is equal, an S pole connecting impedance of the upper tube chip of each single-core power half-bridge is equal, a D pole connecting impedance of the lower tube chip of each single-core power half-bridge is equal, and an S pole connecting impedance of the lower tube chip of each single-core power half-bridge is equal.

2. The semiconductor device according to claim 1, wherein an insulating layer is used to coat a region of the upper tube chip that is not connected to the upper tube ceramic substrate first copper clad layer and the upper tube S pole connecting conductor; an insulating layer is used to coat a region of the lower tube chip that is not connected to the upper tube ceramic substrate first copper clad layer and the lower tube S pole connecting conductor.

3. The semiconductor device of claim 1, wherein each single-core power half-bridge shares the upper tube D pole terminal, the lower tube S pole terminal, and the alternating current connecting copper bar.

4. The semiconductor device of claim 1, wherein Comprising: the upper tube D pole terminal and the lower tube S pole terminal are distributed on a first side of the semiconductor device, the alternating current connecting copper bar is disposed on a second side of the semiconductor device, the first side and the second side being two symmetrical sides of the semiconductor device; a monitoring terminal and a temperature detection element of the semiconductor device are arranged on a third side or a fourth side of the semiconductor device, the first side, the second side, the third side, and the fourth side being four side edges of the semiconductor device.

5. The semiconductor device of claim 4, wherein, the monitoring terminal comprising: an upper tube D pole monitoring terminal, an upper tube G pole terminal, an upper tube S pole terminal, a lower tube G pole terminal, a lower tube S pole terminal, a first temperature detection terminal, and a second temperature detection terminal; wherein the first temperature detection terminal and the second temperature detection terminal are respectively connected to an input terminal and an output terminal of the temperature detection element, for providing a temperature detection signal to an external detection unit.

6. The semiconductor device according to claim 5, wherein the first temperature detection terminal, the second temperature detection terminal, and the temperature detection element are arranged on the third side of the semiconductor device; the upper tube D pole monitoring terminal, the upper tube G pole terminal, the upper tube S pole terminal, the lower tube G pole terminal, and the lower tube S pole terminal are arranged on the fourth side of the semiconductor device.

7. The semiconductor device of claim 1, wherein further comprising: a heat sink; the heat sink being disposed on a side of the ceramic substrate that is away from the upper tube chip and the lower tube chip.

8. The semiconductor device according to claim 1, wherein the lower tube S pole connecting conductor and the upper tube S pole connecting conductor are flexible layer connecting conductors.

9. An electronic device, comprising: a power device composed of the semiconductor device according to any one of claims 1-8.

10. The electronic device of claim 9, wherein, the electronic device is a vehicle.

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