Transistor with higher junction breakdown voltage

Abstract

The utility model provides a transistor with a strain source and drain structure, which is suitable for high-voltage application. A gate stack layer is arranged on the substrate, and the gate stack layer is provided with a gate dielectric layer and a gate structure. The gate spacer is present on a sidewall of the gate stack layer. The two lightly doped drain regions extend from below the gate stack layer to opposite sides of the gate stack layer. A plurality of strained source and drain structures are present in each lightly doped drain region. The strained source and drain structures do not extend below the gate spacer. Transistors can be used in high voltage components, and junction collapse can still be avoided.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a transistor with higher junction breakdown voltage. BACKGROUND

[0002] Integrated circuits are formed on semiconductor wafers. A photolithographic patterning process uses ultraviolet light to transfer a desired mask pattern to photoresist on the semiconductor wafer. An etching process can then be used to transfer the pattern to a layer beneath the photoresist. This process is repeated many times with different patterns to build up different layers on the wafer substrate and fabricate useful components.

[0003] Integrated circuits are composed of a large number of transistors. Field effect transistors are typically constructed from a substrate, with a conductive gate electrode on the substrate that controls the current between a source electrode and a drain electrode. An insulating gate dielectric layer electrically separates the gate from the source and drain electrodes. A semiconductor layer bridges the source and drain electrodes and is in contact with the gate dielectric layer. SUMMARY

[0004] Some embodiments of the present application relate to a transistor including a substrate, a gate stack, lightly doped drain regions, gate spacers, and SSD structures. The gate stack is on the substrate and includes a gate dielectric layer and a gate structure on the gate dielectric layer. First and second lightly doped drain (LDD) regions extend from below the gate stack to opposite sides of the gate stack. Gate spacers are on sidewalls of the gate stack and on the first and second LDD regions. A plurality of strain source and drain (SSD) structures are in each LDD region, with the SSD structures not extending below the gate spacers.

[0005] Some other embodiments of the present application relate to a transistor including a substrate. The substrate includes a fin extending between two source / drain regions. A gate dielectric layer is on at least three sides of the fin between the two source / drain regions. A gate layer is on the gate dielectric layer. Gate spacers are on sidewalls of the gate layer; lightly doped drain (LDD) regions extend from each source / drain region below the gate dielectric layer. A plurality of strain source and drain (SSD) structures are in each LDD region, with the SSD structures not extending below the gate spacers. BRIEF DESCRIPTION OF DRAWINGS

[0006] The aspects of the disclosure will be best understood by reading the following specific disclosure, in conjunction with the annexed drawings. It should be noted that, in accordance with the standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0007] FIG. 1Ais a Y-axis cross-sectional view of a transistor according to a first exemplary embodiment of some embodiments of the present disclosure.

[0008] FIG. 1B is a plan view of the first exemplary embodiment.

[0009] FIG. 2 is a flow chart of a method for forming a transistor according to some embodiments. FIGS. 3-16 Various steps of this method are illustrated.

[0010] FIG. 3 is a Y-axis cross-sectional view of a substrate before the method of FIG. 2

[0011] FIG. 4 is a Y-axis cross-sectional view of a substrate after forming one or more isolation regions to define an active region.

[0012] FIG. 5 is a Y-axis cross-sectional view of a substrate after forming lightly doped drain (LDD) regions on opposite sides of the active region.

[0013] FIG. 6 is a Y-axis cross-sectional view of a substrate after forming a gate stack including a gate dielectric layer and a dummy gate. The gate stack overlaps the two lightly doped drain regions.

[0014] FIG. 7 is a Y-axis cross-sectional view of a substrate after forming a seal layer on the sidewalls of the gate stack.

[0015] FIG. 8 is a Y-axis cross-sectional view of a substrate after forming a second seal layer on the sidewalls of the gate stack to form gate spacers.

[0016] FIG. 9A is a Y-axis cross-sectional view of a substrate after etching source / drain recesses or trenches into each exposed lightly doped drain (LDD) region on both sides of the gate stack.

[0017] FIG. 9B is a set of etch profile contours of source / drain trenches that can be formed depending on the concentration of a retardant present in the etching gas.

[0018] FIG. 10 is a Y-axis cross-sectional view of a substrate after epitaxy in the source / drain recesses to obtain a strained source and drain (SSD) structure.

[0019] FIG. 11 ​is a Y-axis cross-sectional view of the substrate after forming an interlayer dielectric (ILD) over the source / drain regions.

[0020] FIG. 12 is a Y-axis cross-sectional view of the substrate after removing dummy gates.

[0021] FIG. 13 is a Y-axis cross-sectional view of the substrate after applying a first insulating layer over the transistors.

[0022] FIG. 14 is a Y-axis cross-sectional view of the substrate after forming a via through the first insulating layer and extending to the gate structure and the SSD structure.

[0023] FIG. 15A is a Y-axis cross-sectional view of the substrate after applying a second insulating layer over the first insulating layer and forming pads in the second insulating layer to form source electrodes, drain electrodes, and gates to form a transistor package.

[0024] FIG. 15B is a Y-axis cross-sectional view of a transistor package according to another embodiment of the disclosure. Here, only one insulating layer is provided.

[0025] FIG. 16 is a perspective view of another embodiment of a transistor package illustrating that the gate is offset from the source electrodes and the drain electrodes along the X-axis.

[0026] FIG. 17 is a Y-axis cross-sectional view of a transistor according to another embodiment of the disclosure. Here, the gate dielectric layer is formed in a recess of the substrate.

[0027] FIG. 18 is a Y-axis cross-sectional view of a transistor according to another embodiment of the disclosure. Here, the gate dielectric layer and the gate structure extend into a recess of the substrate.

[0028] FIG. 19 is a perspective view of a transistor according to another embodiment of the disclosure. Here, the transistor is in the form of a FinFET having a three-dimensional structure.

[0029] FIG. 20 is a Y-axis cross-sectional view of a gate stack layer structure illustrated by cross-sectional line A-A in FIG. 19 .

[0030] FIG. 21 is a Y-axis cross-sectional view of an SSD structure illustrated by cross-sectional line B-B in FIG. 19 .

[0031] FIG. 22 is a flowchart of a method for forming a FinFET structure according to some embodiments of the disclosure. FIGS. 19-21 .

[0032] FIG. 23 Figure 1 1 is a plot of drain leakage current versus drain voltage. The y-axis is logarithmic, while the x-axis is linear. DETAILED DESCRIPTION

[0033] The following disclosure provides different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the making of first and second features on top of or in another feature in the description below can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features can not be in direct contact. In addition, the present disclosure can make repeated reference to a reference number and / or letter in various instances. Such repeated usage is for the purpose of simplicity and clarity and does not itself convey a relationship between the various embodiments and / or configurations discussed.

[0034] Also for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein for explaining the relationship between one component or feature to another component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0035] Numerical values in the specification and claims of this application should be understood to include any and all equivalents when reduced to the same number of significant figures as would be understood by one of ordinary skill in the art, and when the experimental error in conventional measurement techniques is taken into account. All ranges disclosed herein are inclusive of the recited endpoint and all intervening values.

[0036] The term "about" can be used to include any numerical value that can vary in order to stay within the basic function of the number. When used with a range, "about" also discloses the range defined by the absolute values of the two endpoints, e.g., "about 2 to about 4" also discloses the range "from 2 to 4". The term "about" can include plus or minus 10% of the indexed value.

[0037] The present disclosure relates to structures composed of different layers. When using the terms "on" or "over" to describe two different layers (including a substrate), it is meant that one layer is on or over the other layer. These terms do not necessarily denote a direct contact between two layers and allow for the presence of other layers between the two layers. For example, all layers of a structure can be considered to be "on" a substrate, even though they are not all in direct contact with the substrate. The term "directly" can be used to denote that two layers are in direct contact with each other and do not have any layers between them. In addition, when referring to performing a process step on or over a substrate, depending on the context, it should be interpreted as performing the process step on any layers that can be present on the substrate.

[0038] The present disclosure relates to transistors with higher source / drain (S / D) junction breakdown voltage, methods for fabricating the same, and methods using the same. Stress / strain techniques are used to increase carrier mobility in the channel of a transistor and improve component performance. Strain parallel to the length and width of the channel of a transistor is referred to as in-plane strain. It is known that biaxial in-plane tensile strain can improve the performance of N-type metal oxide semiconductor (NMOS) and compressive strain parallel to the length of the channel can improve the performance of P-type metal oxide semiconductor (PMOS). However, high voltage components typically do not use such stress / strain techniques because they result in lower junction breakdown voltage, which is especially undesirable at high voltages (greater than 9 volts). The present disclosure describes structures that can include strain engineered source / drain regions and still maintain high junction breakdown voltage.

[0039] FIG. 1A A Y-axis cross-sectional view of the transistor 101 is shown according to a first exemplary embodiment of some embodiments of the present disclosure, and FIG. 1A Some features are illustrated. FIG. 1B is a plan view near the top surface of the substrate in the first exemplary embodiment.

[0040] Reference is also made to FIG. 1A and FIG. 1BTransistor 101 is formed on substrate 110. For example, the two isolation regions 114 and 116 shown can be shallow trench isolation (STI) regions or deep trench isolation (DTI) regions. The region between them (the two isolation regions 114 and 116) is defined as active region 118. It is worth noting that there can also be an isolation region (not shown) along the X-axis, such that the active region is surrounded on all sides. Alternatively, isolation regions 114 and 116 can be considered together as a single isolation region because they are formed in the same step and are physically connected together.

[0041] Two lightly doped drain (LDD) regions 120 and 130 exist on the substrate and are located on opposite sides of the active region 118. The lightly doped drain region 120 extends from the isolation region 114 toward the center of the active region 118, and the lightly doped drain region 130 extends from the isolation region 116 toward the center of the active region. The two lightly doped drain regions 120 and 130 are not in contact with each other and are spaced apart from each other.

[0042] A gate stack layer 160 also exists on the substrate and is located within the active region 118. The gate stack layer 160 includes a gate dielectric layer 140 to overlap with the gate structure 150 above the gate dielectric layer 140. The gate stack layer 160 overlaps with the lightly doped drain regions 120, 130, or in other words, a portion of the gate stack layer 160 is perpendicularly positioned above each lightly doped drain region 120, 130. The lightly doped drain regions 120, 130 can also be described as extending away from the gate stack layer 160 toward the opposite side of the active region 118.

[0043] A selective first sealing layer 170 is located on the sidewall 162 of the gate stack layer 160 and is vertically oriented. A selective second sealing layer 180 contacts the first sealing layer 170 and is also vertically oriented. A gate spacer wall 190 contacts the second sealing layer 180 and is also vertically oriented. The selective first sealing layer 170, the selective second sealing layer 180, and the gate spacer wall 190 can all be described as being formed on the sidewall 162 of the gate stack layer 160. FIG. 1B As can be better seen in the plan view, the selective first sealing layer 170, the selective second sealing layer 180, and the gate spacer 190 surround the gate stack layer 160. The selective first sealing layer 170, the selective second sealing layer 180, and the gate spacer 190 are typically composed of a dielectric material.

[0044] A plurality of source / drain (S / D) trenches 200 are present in each lightly doped drain region 120, 130. Here, three S / D trenches 200 are illustrated in each lightly doped drain region 120, 130. The S / D trenches 200 are spaced apart from one another. Each S / D trench 200 includes a strained source and drain (SSD) structure 210. A top portion 212 of the SSD structure 210 is located above the substrate 110. Notably, the SSD structure 210 does not extend below the gate spacers 190. Dotted lines indicate the location of a semiconductor channel 230, which is spaced apart from the SSD structure 210. An intervening layer dielectric (ILD) region 240 is present above the S / D trenches 200.

[0045] Generally, the SSD structure 210 is formed by introducing dopants in silicon to increase the interatomic distance and change the lattice structure. This induces strain or stress in the semiconductor channel 230. The dopant concentration in the SSD structure 210 is in a gradient form, with the highest dopant concentration present along the perimeter or wall of the SSD structure 210, and the lowest dopant concentration present near the center of the SSD structure 210. As shown, the low dopant concentration portion is indicated by reference number 214, and the high dopant concentration portion is indicated by reference number 216. In particular embodiments, in the low dopant concentration portion, the dopant concentration can be about 1 x 1019to about 5 x 1020atoms per cubic centimeter. In the high dopant concentration portion, the dopant concentration can be about 5 x 1020to about 5 x 1021atoms per cubic centimeter. The dopant concentration generally varies smoothly from the periphery to the center. 19 (1E19) to about 5 x 1020atoms per cubic centimeter. In the high dopant concentration portion, the dopant concentration can be about 5 x 1020to about 5 x 1021atoms per cubic centimeter. The dopant concentration generally varies smoothly from the periphery to the center. 20 (5E20) to about 5 x 1021atoms per cubic centimeter. The dopant concentration generally varies smoothly from the periphery to the center. 20 (5E20) to about 5 x 1021atoms per cubic centimeter. The dopant concentration generally varies smoothly from the periphery to the center. 21 (5E20) to about 5 x 1021atoms per cubic centimeter. The dopant concentration generally varies smoothly from the periphery to the center.

[0046] Each lightly doped drain region 120, 130 has a width 125, 135 and a depth 127, 137, respectively. In particular embodiments, the width 125, 135 is about 200 nanometers to about 1000 nanometers, respectively. In particular embodiments, the depth 127, 137 is about 50 nanometers to about 300 nanometers, respectively. Combinations of width and depth are also contemplated. Other ranges and values for each of these properties are also within the scope of the present disclosure.

[0047] The gate dielectric layer 140 has a width 145 and a depth 147. In particular embodiments, the width 145 is about 300 nanometers to about 1000 nanometers. In particular embodiments, the depth 147 is about 10 nanometers to about 30 nanometers. Combinations of width and depth are also contemplated. Other ranges and values for each of these properties are also within the scope of the present disclosure.

[0048] The gate structure 150 has a width of 155 and a depth of 157. In a particular embodiment, the width 155 is about 300 nanometers to about 1000 nanometers. In a particular embodiment, the depth 157 is about 10 nanometers to about 100 nanometers. Combinations of width and depth are also contemplated. Other ranges and values ​​of each of these properties are also within the scope of this disclosure.

[0049] The first sealing layer 170 has a width of 175 and a depth of 177. In a particular embodiment, the width 175 is about 10 nanometers to about 30 nanometers. In a particular embodiment, the depth 177 is about 30 nanometers to about 100 nanometers. Combinations of width and depth may also be considered. Other ranges and values ​​of each of these properties are also within the scope of this disclosure.

[0050] The second sealing layer 180 has a width of 185 and a depth of 187. In a particular embodiment, the width 185 is about 10 nanometers to about 30 nanometers. In a particular embodiment, the depth 187 is about 30 nanometers to about 100 nanometers. Combinations of width and depth may also be considered. Other ranges and values ​​of each of these properties are also within the scope of this disclosure.

[0051] The gate spacer 190 has a width of 195 and a depth of 197. In a particular embodiment, the width 195 is about 10 nanometers to about 30 nanometers. In a particular embodiment, the depth 197 is about 30 nanometers to about 100 nanometers. Combinations of width and depth may also be considered. Other ranges and values ​​of each of these properties are also within the scope of this disclosure.

[0052] The dimensions of the S / D trench 200 and the SSD structure 210 can be discussed together. Each SSD structure 210 has a width 215 and a depth 217. In a particular embodiment, the width 215 is from about 10 nanometers to about 100 nanometers. In a particular embodiment, the depth 217 is from about 30 nanometers to about 100 nanometers. Combinations of width and depth may also be considered. Other ranges and values ​​of each of these properties are also within the scope of this disclosure.

[0053] Adjacent S / D trench 200 and SSD structure 210 are spaced apart from each other by a spacing width 232. In a particular embodiment, the width 232 is from about 10 nanometers to about 100 nanometers. Other ranges and values ​​are also within the scope of this disclosure.

[0054] FIG. 2 This is a flowchart illustrating a first method 300 for forming a transistor, based on some embodiments. FIGS. 3-16 Some steps of this method are illustrated. These diagrams provide different perspectives for a better understanding of this disclosure. Although the method steps are discussed below from the perspective of forming a single transistor, this discussion should be broadly interpreted as applicable to the simultaneous formation of multiple transistors.

[0055] FIG. 3 is a cross-sectional view of a substrate 110 on which a transistor will be formed. For example, the substrate 110 can be a wafer made of a semiconductor material. The semiconductor material can include silicon, such as crystalline forms of silicon. In alternative embodiments, the substrate 110 can be made of other elemental semiconductors, such as germanium, or can include compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium (SiGe), silicon germanium carbide, gallium arsenide phosphide, or indium gallium arsenide phosphide. In a particular embodiment, the substrate 110 is silicon. The substrate 110 includes an upper surface 112.

[0056] At step 305 in FIG. 2 and as shown in FIG. 4 one or more isolation regions are formed in the substrate 110 to define an active region 118 of the substrate 110. As shown here, two shallow trench isolation (STI) regions 114, 116 are formed in the substrate 110. The active region 118 is located in the area between the two shallow trench isolation regions 114, 116. As previously mentioned, when considering three-dimensional dimensions, the two shallow trench isolation regions 114, 116 can be connected to each other and can be considered as one isolation region.

[0057] The isolation regions 114, 116 are formed by patterning the substrate, etching trenches, and filling the trenches with a dielectric material. The dielectric material in the shallow trench isolation regions 114, 116 is typically silicon dioxide, but other dielectric materials can be used, such as undoped polysilicon, silicon oxide (e.g., SiO2), silicon nitride, silicon oxynitride, fluoride-doped silicate glass, or other low dielectric constant dielectric materials. Deposition can be accomplished using physical vapor deposition (PVD) or chemical vapor deposition (CVD) or spin-on processes known in the art, or by oxidation. If desired, the dielectric material can be deposited to a level above the upper surface 112 of the substrate and then recessed back down to the desired height.

[0058] At step 310 in FIG. 2 and as shown in FIG. 5As shown, two lightly doped drain (LDD) regions 120 and 130 are formed in the substrate 110 and located on opposite sides of the active region 118. The lightly doped drain regions 120 and 130 reduce the hot carrier effect that may occur in the saturation region of the transistor. As shown here, the first lightly doped drain region 120 extends from the shallow trench isolation region 114 to the center or middle of the active region 118. Similarly, the second lightly doped drain region 130 extends from another shallow trench isolation region 116 to the center or middle of the active region 118. However, the two lightly doped drain regions 120 and 130 do not contact each other. In other words, there is a gap 234 between the two lightly doped drain regions 120 and 130.

[0059] Lightly doped drain regions 120 and 130 can be fabricated by ion implantation or other suitable methods. In short, in ion implantation, an ion implanter is used to implant atoms into a silicon lattice, thereby modifying the conductivity of the lattice at the implantation site. An ion implanter typically includes an ion source, a beamline, and a process chamber. The ion source generates the desired ions. The beamline organizes the ions into a beam with high purity in terms of ion mass, energy, and matter. A mask, such as a patterned photoresist layer or a hard mask layer, is used to expose the desired area of ​​the substrate. The semiconductor wafer substrate in the process chamber is then irradiated with an ion beam. The ion beam strikes the exposed area on the wafer substrate, and ions can be implanted into the substrate at the desired depth as dopants. Alternatively, the substrate can be partially etched, followed by blanket deposition of the dopant, and finally annealed, in which the dopant reacts with the exposed silicon beneath.

[0060] Next, in FIG. 2 In step 315 and as follows FIG. 6 As shown, a gate dielectric layer 140 is formed on substrate 110. Similarly, CVD, PVD, atomic layer deposition (ALD), or other suitable deposition processes can be used to form the gate dielectric layer 140. Thermal oxidation can also be used to form the gate dielectric layer 140. Then, in FIG. 2 In step 320, a dummy gate 168 is formed on the gate dielectric layer 140. The dummy gate 168 is typically made of polysilicon. The dummy gate 168 can be formed using appropriate processes, such as CVD, PVD, ALD, or other deposition techniques. The resulting structure is illustrated in... FIG. 6 In the figure, the gate dielectric layer 140 and the dummy gate 168 can be collectively referred to as the gate stack layer 160. As shown, the gate stack layer 160 bridges the gap between the two lightly doped drain regions 120 and 130. In other words, the gate stack layer 160 overlaps with the two lightly doped drain regions 120 and 130. The gate stack layer 160 has sidewalls 162.

[0061] Next, inFIG. 2 A first seal layer 170 can be selectively formed on the sidewall 162 of the gate stack layer 160 in a selective step 325 and as shown in FIG. 7 The first seal layer 170 is vertically oriented and has a relatively narrow width. The first seal layer 170 is made of a dielectric material to electrically isolate the final gate. In a particular embodiment, the first seal layer 170 is silicon nitride (SiN) or silicon dioxide (Si02). The first seal layer 170 can be fabricated by CVD, PVD, ALD or other deposition techniques.

[0062] Referring now to FIG. 8 Similarly, in a selective step 330 of FIG. 2 , a second seal layer 180 can be selectively formed on the sidewall 162 of the gate stack layer 160 and over the first seal layer 170. Then, in a step 335 of FIG. 2 , a gate spacer 190 is formed on the sidewall of the gate stack layer 160. In a particular embodiment, the gate spacer 190 is silicon nitride (SiN) or silicon dioxide (Si02). The gate spacer 190 can be fabricated by CVD, PVD, ALD or other deposition techniques. As shown, the gate spacer 190 is formed over the lightly doped drain regions 120, 130.

[0063] Next, in a step 340 of FIG. 2 and as shown in FIG. 9A , a plurality of S / D trenches 200 are etched in each of the lightly doped drain regions 120, 130 to form source / drain regions 220. Each S / D trench 200 passes through the lightly doped drain region 120, 130 and extends into the substrate 110. This etching step is typically performed by dry etching and requires a non-isotropic etch profile. In a more particular embodiment, the etching gas can be a mixture of HBr / O2 / H2 in the desired proportions to obtain the desired shape of the trenches. As shown here, three spaced apart trenches are formed in each of the lightly doped drain regions 120, 130. Of particular note is that the S / D trenches 200 do not extend below the gate spacer 190. Thus, for the semiconductor channel 230, the distance 236 between the S / D trenches 200 and the channel 230 can be as small as 10 nanometers depending on the dimensions of the selective first seal layer 170, the selective second seal layer 180 and the gate spacer 190.

[0064] FIG. 9Bis a set of etch profile contours that can be formed for the source / drain trenches, depending on the concentration of a secondary etchant in the etch gas. In this regard, removal of the substrate 110 material forms the trenches 200. By-products of the etch process can form a protective layer on the exposed substrate as well as within the trenches, such that the etch rate at the bottom of the trench is greater than the etch rate near the top surface of the substrate (i.e., near the trench surface that is covered by the protective layer). The secondary etchant is more selective to the protective layer, such that the protective layer can be removed from the trench surface. When the concentration of the secondary etchant is "low", the resulting trench 200 has a trapezoidal profile, where the width 205 of the trench 200 at its bottom is greater than the width 207 of the trench 200 at its top. When the concentration of the secondary etchant is "medium", the resulting trench 200 has substantially vertical sidewalls, such that the width 205 of the trench 200 at its bottom is substantially equal to the width 207 of the trench 200 at its top. When the concentration of the secondary etchant is "high", the resulting trench 200 has a trapezoidal profile, where the width 205 of the trench 200 at its bottom is less than the width 207 of the trench 200 at its top. This etch profile can be referred to as a "necking" profile. Notably, the surface at the bottom of the trench 200 can be curved rather than linear. In particular embodiments, the S / D trenches 200 have a necking profile.

[0065] Then, in step 345, and as shown in FIG. 3C, a strained source and drain (SSD) structure 210 is formed within each S / D trench 200. Again, the SSD structure 210 does not extend below the gate spacers 190. FIG. 2 FIG. 10 In step 345, and as shown in FIG. 3C, a strained source and drain (SSD) structure 210 is formed within each S / D trench 200. Again, the SSD structure 210 does not extend below the gate spacers 190.

[0066] In some embodiments, the SSD structure 210 is formed by an epitaxial process. Examples of such processes include a selective epitaxy growth (SEG) process, vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), and some CVD deposition techniques. Typically, gaseous precursors that can interact with each other and / or with the substrate 110 are used. Doping species can be introduced during the epitaxial process by introducing a dopant species. The dopant species can include a p-type dopant, such as germanium (Ge) or boron (B); or an n-type dopant, such as phosphorous (P) or arsenic (As). Alternatively, an ion implantation process can be used to dope the SSD structure 210.

[0067] ​The SSD structure 210 can grow on the surface of the S / D trench 200, eventually filling the trench and also forming a top cap portion 212. As previously discussed, the dopant concentration can increase from the perimeter / wall 211 of the SSD structure 210 to the center 213 of the SSD structure 210. In other words, the dopant concentration increases with distance from the wall of the trench. The lower dopant concentration adjacent to the undoped silicon substrate helps to lower the Schottky barrier. The higher dopant concentration near the center of the SSD structure 210 can reduce the source / drain contact resistance. The dopant concentration can be varied by varying the ratio of gaseous precursors. In some particular embodiments, the SSD structure 210 is formed of SiP (for NMOS) or silicon germanium (for PMOS). In some embodiments, annealing can be performed to activate the dopants in the SSD structure 210. As a result, the semiconductor channel 230 is strained or stressed to increase the carrier mobility within the channel.

[0068] As FIG. 2 step 350 and as discussed in FIG. 11 , an intermediate dielectric (ILD) material can be applied over the source / drain regions 220 to form an ILD region 240. The ILD region 240 electrically isolates the source / drain regions 220 from the final gate structure or electrode. The ILD region 240 can be formed of any dielectric material, and need not be a high-k dielectric material. The ILD material can be deposited using any suitable method, such as CVD.

[0069] Then, continuing in FIG. 2 step 355 and as shown in FIG. 12 , the dummy gate 168 is removed to form a gate portion 169. This can be accomplished by etching or other suitable process. Then, in FIG. 2 step 360, a conductive gate material is deposited to fill the gate portion 169 and form the gate structure 150. For example, suitable gate materials can include metals such as W, titanium nitride, TiAl, Pt, Co, Rh, Pd, Ti, Ta, and the like or doped polysilicon. The resulting structure is illustrated in FIG. 1A and FIG. 1B which have been discussed previously.

[0070] Further processing can also be performed to encapsulate the transistor. For example, next, in FIG. 2 step 365 and as shown in FIG. 13As shown, a first insulating layer 250 is formed over the active region 118 including the source / drain regions 220 and the gate structure 150. This layer can be formed using a deposition process such as PVD, CVD, sub-atmospheric chemical vapor deposition, or other suitable deposition process. The material of the first insulating layer 250 can be silicon or other suitable dielectric material (e.g., silicon dioxide).

[0071] Then, in step 370 and as shown in FIG. 3B, etching is performed to form openings through the first insulating layer 250 and the ILD region 240 and extending to the SSD structures 210 and the gate structure 150 in the source / drain regions 220. In step 375, the openings are then filled with a conductive material to form source / drain vias 256 and gate vias 258. Note that, as shown here, a via 256 is formed at each SSD structure 210. FIG. 2 FIG. 14 Then, in step 380 and as shown in FIG. 3C, a second insulating layer 260 is formed over the first insulating layer 250 and the active region 118 including the source / drain regions 220 and the gate structure 150. In step 385, etching is then performed to form openings through the second insulating layer 260 and extending to the vias 256, 258 in the first insulating layer 250. In step 390, the openings are then filled with a conductive material to form source / drain pads 266 and gate pads 268. Note that, as shown, the S / D pads 266 are in contact with the vias 256 and the SSD structures 210, such that the SSD structures in each lightly doped drain region are electrically connected together. In this embodiment, the source / drain electrodes 272 are formed by the combination of the S / D vias 256 and the S / D pads 266. The gate electrodes 274 are formed by the combination of the gate vias 258 and the gate pads 268.

[0072] The vias 256, 258 can themselves be sufficient to act as electrodes (i.e., source, drain, and gate) for further processing steps. If a larger contact footprint is desired, these steps can be repeated.

[0073] For example, in step 380 and as shown in FIG. 3C, a second insulating layer 260 is formed over the first insulating layer 250 and the active region 118 including the source / drain regions 220 and the gate structure 150. In step 385, etching is then performed to form openings through the second insulating layer 260 and extending to the vias 256, 258 in the first insulating layer 250. In step 390, the openings are then filled with a conductive material to form source / drain pads 266 and gate pads 268. Note that, as shown, the S / D pads 266 are in contact with the vias 256 and the SSD structures 210, such that the SSD structures in each lightly doped drain region are electrically connected together. In this embodiment, the source / drain electrodes 272 are formed by the combination of the S / D vias 256 and the S / D pads 266. The gate electrodes 274 are formed by the combination of the gate vias 258 and the gate pads 268. FIG. 2 FIG. 15A FIG. 2 is a perspective view of another embodiment of a packaged transistor 102. In this embodiment, only a first insulating layer 250 is applied. Source / drain vias 256 are formed through the ILD region 240. S / D pads 272 are then formed in the first insulating layer 250 to connect the S / D vias together and form source / drain electrodes 272. Gate electrodes 274 are also formed in the first insulating layer 250.

[0074] FIG. 15B is a perspective view of another embodiment of a packaged transistor 102. In this embodiment, only a first insulating layer 250 is applied. Source / drain vias 256 are formed through the ILD region 240. S / D pads 272 are then formed in the first insulating layer 250 to connect the S / D vias together and form source / drain electrodes 272. Gate electrodes 274 are also formed in the first insulating layer 250.

[0075] ​​​FIG. 16 is a perspective view of another embodiment of a packaged transistor 103. Notably, the gate electrode 274 can be separated from the source / drain electrode 272 in the direction of the X-axis.

[0076] The transistors and methods of the present disclosure include several different dielectric structures. Such dielectric structures can generally be made of any suitable combination of dielectric materials, although the properties of any particular layer can be further defined. Examples of dielectric materials can include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), silicon oxynitride (SiO x N y ), hafnium oxynitride (HfO x N y ), or zirconium oxynitride (ZrO x N y ), or hafnium silicate (ZrSi x O y ), or zirconium silicate (ZrSi x O y ), or silicon carbon nitride (SiC x O y N z ), or hexagonal boron nitride (hBN). Other dielectric materials can include tantalum oxide (Ta2O5), nitrides such as silicon nitride, polysilicon, phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high stress undoped silicate glass (HSUSG), and borosilicate glass (BSG).

[0077] It should also be noted that certain conventional steps are not explicitly described in the above discussion. For example, a pattern / structure can be formed in a given layer by applying a photoresist layer, patterning the photoresist layer, developing the photoresist layer, and then etching.

[0078] Generally, a photoresist layer can be applied by means such as spin coating, spraying, roller coating, dip coating, or extrusion coating. Typically, during spin coating, the substrate is placed on a spinning platform, which can include a vacuum chuck that holds the flat substrate. The photoresist composition is then applied to the center of the substrate. The speed of the spinning platform is then increased to spread the photoresist evenly from the center of the substrate to the periphery of the substrate. The rotational speed of the platform is then fixed to control the thickness of the final photoresist layer.

[0079] Next, the photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. In some particular embodiments, the baking is performed at a temperature of about 90 °C to about 110 °C. The baking can be performed using a hot plate or an oven or similar equipment. Thus, a photoresist layer is formed on the substrate.

[0080] The photoresist layer is then patterned by exposure to radiation. The radiation can be any wavelength of light with the desired mask pattern. In particular embodiments, EUV light having a wavelength of about 13.5 nanometers is used for patterning, as this allows for smaller feature sizes to be obtained. This will result in some portions of the photoresist layer being exposed to radiation and some portions of the photoresist not being exposed to radiation. The aforementioned exposure can result in some portions of the photoresist being soluble in a developer while other portions of the photoresist are not soluble in the developer.

[0081] After exposure to radiation, an additional photoresist baking step (i.e., post-exposure bake, PEB) can be performed. This can be helpful, for example, to release acid leaving groups (ALGs) or other molecules of interest in chemical amplification photoresists.

[0082] The photoresist layer is then developed using a developer. The developer can be an aqueous or organic solution. The soluble portions of the photoresist layer will dissolve and be washed away during the development step, leaving behind a photoresist pattern. One common example of a developer is aqueous tetramethylammonium hydroxide (TMAH). In general, any suitable developer can be used. Sometimes, a post-development bake or "hard bake" can be performed to stabilize the developed photoresist pattern for optimal performance in subsequent steps.

[0083] Continuing, portions of the layer located under the patterned photoresist layer are exposed. Etching transfers the photoresist pattern to the layer under the patterned photoresist layer. After use, the patterned photoresist layer can be removed, for example, using various solvents such as N-methyl-pyrrolidone (NMP) or alkaline media or other strippers at elevated temperatures or using an oxygen plasma for dry etching.

[0084] Generally, any of the etching steps described herein can be performed using a wet etch, dry etch, or plasma etch process, such as a reactive ion etch (RIE) or inductively coupled plasma (ICP), or a combination thereof, as appropriate. The etching can be anisotropic. Depending on the material, the etchant can include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), fluorocarbon, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BC13), ammonia (NH3), bromine (Br2), nitrogen trifluoride (NF3), or the like, or a combination of the foregoing materials in various ratios. For example, silicon dioxide can be wet etched using hydrofluoric acid with ammonium fluoride. Alternatively, silicon dioxide can be etched using various mixtures of CHF3, O2, CF4, and / or H2.

[0085] For example, planarization of the surface can be performed using a chemical mechanical polishing (CMP) process. Generally, CMP is performed using a rotating platform to which a polishing pad is attached. The substrate is attached to a rotating carrier. A slurry or solution containing various chemicals and abrasives is dispensed onto the polishing pad or wafer substrate. During polishing, both the polishing pad and the carrier are rotated, which causes mechanical and chemical effects on the surface of the wafer substrate and / or its top layers, removing unwanted material and creating a highly planar surface. A post-CMP cleaning step is then performed using a rotating cleaning brush and a cleaning fluid to clean one or both sides of the wafer substrate.

[0086] Some variations in the transistors can be taken into account. FIG. 17 is a Y-axis cross-sectional view of the transistor 104 in another embodiment. In this embodiment, the gate dielectric layer 140 is formed in a recess in the substrate, or in other words, the gate dielectric layer 140 is present below the upper surface 112 of the substrate 110. The gate dielectric layer 140 fills the recess. FIG. 18 is a Y-axis cross-sectional view of the transistor 105 in another embodiment. Here, both the gate dielectric layer 140 and the gate structure 150 extend into a recess in the substrate 110. The gate dielectric layer 140 can be considered to cover the surface of the recess. This can help to better control the thickness of the gate dielectric layer 140 and avoid impacting the bottom-most interconnect layer (M1).

[0087] FIG. 19is a perspective view of a transistor according to another embodiment of some embodiments of the present disclosure. Here, transistor 106 is in the form of a FinFET having a three-dimensional structure, with fin 280 being taller than substrate 110. FIG. 20 is a Y-axis cross-sectional view taken through FIG. 19 along section line A-A, FIG. 21 is a Y-axis cross-sectional view taken through FIG. 19 along section line B-B.

[0088] Referring first to FIG. 19 and FIG. 20 , gate dielectric layer 140 and gate structure 150 form gate stack layer 160, which is present on three sides of fin 280. Lightly doped drain regions 120, 130 are visible. Here, source / drain regions 220 are shown as part of the fin, although they can also be separate structures connected to multiple ends of multiple fins. First and second encapsulation layers 170, 180, along with gate spacers 190, electrically isolate SSD structure 210 from gate stack layer 160. As shown in FIG. 19 and FIG. 21 , SSD structure 210 extends into source / drain regions 220, and through lightly doped drain region 120. Top cap portion 212 of SSD structure 210 sits above upper surface 282 of the fin.

[0089] FIG. 22 is a flowchart of a method 400 for forming a FinFET structure according to some embodiments of FIGS. 19-21 .

[0090] Initially, in step 402, the substrate 110 is shaped to form one or more fins 280. Typically, one or more hard mask layers are applied to the substrate. Then, mandrels are formed on the hard mask layers over the substrate. The mandrel pattern can be formed by depositing a mandrel material layer, forming a photoresist layer on the mandrel material layer, exposing the photoresist to radiation, and developing the photoresist layer, and then etching the mandrel material layer to form the mandrels. If desired, the mandrels are then used as a mask, and etching is performed through the hard mask layers and into the substrate to form the plurality of fins. Alternatively, in a process known as self-aligned double patterning (SADP), spacers are formed on the sidewalls of the mandrels, and then the mandrels are removed. The spacers are then used as a mask, and etching is performed through the hard mask layers and into the substrate to form the plurality of fins. Self-aligned quadruple patterning (SAQP) is a similar process that can also be used to form the plurality of fins.

[0091] Many of the steps in the following are the same as many of the steps in the method of FIG. 2 , with appropriate modifications for a FinFET. In step 405, a plurality of isolation regions, such as STI regions, are formed between adjacent fins to define active regions. In step 410, LDD regions are formed on opposite sides of the active regions 118. In step 415, a gate dielectric layer 140 is formed on three sides of the fins. Again, the gate dielectric layer overlaps the LDD regions. In step 420, dummy gates 168 are formed on the gate dielectric layer 140 to form a gate stack layer 160. The dummy gates also overlap the LDD regions. In optional steps 425 and 430, a first encapsulation layer 170 and a second encapsulation layer 180 can be formed on the sidewalls of the gate stack layer 160. In step 435, a gate spacer 190 is formed on the sidewalls of the gate stack layer. The gate spacer is also located over the LDD regions. In step 440, S / D trenches are etched in each LDD region to form source / drain regions 450. In step 445, SSD structures are formed in each S / D trench. In step 450, ILD regions are formed over the source / drain regions (note that this step is not shown in FIGS. 19-21 ). In step 455, the dummy gates are removed to form gate portions. In step 460, a conductive gate material is deposited to fill the gate portions and form gate structures 150 in the form of gate layers. The resulting structure is shown in FIGS. 19-21 , which does not have ILD regions. FIG. 2Process steps 365-390 can also be performed to encapsulate the FinFET.

[0092] The combination of the lightly doped drain regions and the SSD structure increases the S / D junction breakdown voltage and also allows a relatively uniform electric field to be achieved at the surface of the transistor. This achieves the same result as a Reduced Surface Field (RESURF) where a PN junction is constructed under the drain in the transistor such that a depletion layer extending from the PN junction reaches the surface of the component, but this structure does not require additional processing steps. Additionally, the dopant concentration in the SSD structure can be increased to reduce the surface electric field without reducing the S / D junction breakdown voltage.

[0093] The transistors of the present disclosure can be used in high voltage, medium voltage, and low voltage components on a chip. High voltage components typically operate in a voltage range of about 12 V to about 28 V. Medium voltage components typically operate in a voltage range of about 3 V to about 9 V. Low voltage components typically operate at voltages below 1 V.

[0094] Additional processing steps can be performed to fabricate semiconductor components or integrated circuits having additional structures. Examples of such steps can include ion implantation, deposition of other materials, etching, etc.

[0095] The semiconductor components can be used in various applications, such as bipolar-complementary metal-oxide-semiconductor-dual diffusion metal-oxide-semiconductor (BCD) circuits for driving discrete high voltage components; drivers suitable for LCD, OLED, AMOLED, or QLED display panels; image sensors that can be used in systems such as mobile phones, facial recognition systems, or motion sensors for automotive applications, security applications, energy efficiency, etc.; power management components that control the flow and direction of power; and / or image signal processors (ISPs).

[0096] Accordingly, some embodiments of the present disclosure are directed to a method of forming a transistor. A plurality of lightly doped drain (LDD) regions are formed in a substrate and on opposite sides of an active region. A gate stack layer is formed on the substrate and overlapping the LDD regions. The gate stack layer includes a gate dielectric layer and a dummy gate on the gate dielectric layer. A gate spacer is formed on sidewalls of the gate stack layer on the LDD regions. A plurality of source / drain trenches are etched in each of the LDD regions to form a plurality of source / drain regions. A strain source and drain (SSD) structure is formed in each of the source / drain trenches. The SSD structure does not extend under the gate spacer. In some embodiments, each strain source and drain structure has a dopant gradient concentration that increases from a periphery of the strain source and drain structure to a center of the strain source and drain structure. In some embodiments, the dopant concentration at the periphery of the strain source and drain structure is about 1 x 1018cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1019cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1020cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1021cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1022cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1023cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1024cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1025cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1026cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1027cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1028cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1029cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1030cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1031cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1032cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1033cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1034cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1035cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1036cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1037cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1038cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1039cm-3. In some embodiments, the dopant concentration at the center of the strain source and drain structure is about 1 x 1040cm-3.19 about 5 x 1011 20 atoms per cubic centimeter. In some embodiments, the dopant concentration at the center of the strained source and drain structure is about 5 x 1011 20 about 5 x 1011 21 atoms per cubic centimeter. In some embodiments, each strained source and drain structure comprises SiP or SiGe. In some embodiments, the gate spacer has a width of about 10 nanometers to about 100 nanometers. In some embodiments, each strained source and drain structure has a width of about 10 nanometers to about 100 nanometers. In some embodiments, a spacing width of about 10 nanometers to about 100 nanometers exists between adjacent strained source and drain structures. In some embodiments, each source / drain trench has a trapezoidal profile with a smaller width at the bottom of the each source / drain trench. In some embodiments, the method further comprises: prior to forming the lightly doped drain region, forming an isolation region in the substrate to define the active region. In some embodiments, the method further comprises: prior to forming the gate spacer, forming at least one encapsulation layer on the sidewall of the gate stack layer. In some embodiments, the at least one encapsulation layer has a width of about 10 nanometers to about 100 nanometers. In some embodiments, after forming the strained source and drain structure, further comprising: removing the dummy gate to form a gate portion; depositing a gate material in the gate portion to form a gate structure; applying an interlayer dielectric material on the source / drain region; forming a first insulating layer on the active region; etching a plurality of openings through the first insulating layer to the source / drain region and the gate structure; and filling the plurality of openings with a conductive material to form at least one source via, at least one drain via to with gate via. In some embodiments, the method further comprises: forming a second insulating layer over the first insulating layer; etching the second insulating layer to form pads over the vias; and filling the pads with a conductive material to form source electrodes, drain electrodes to with gate electrodes.

[0097] Other embodiments of the present disclosure are directed to a transistor including a substrate, a gate stack layer, lightly doped drain regions, gate spacers, and SSD structures. The gate stack layer is on the substrate and includes a gate dielectric layer and a gate structure on the gate dielectric layer. First and second lightly doped drain (LDD) regions extend from below the gate stack layer to opposite sides of the gate stack layer. Gate spacers are on sidewalls of the gate stack layer and on the first and second LDD regions. A plurality of strain source and drain (SSD) structures are present within each LDD region, where the SSD structures do not extend below the gate spacers. In some embodiments, the strain source and drain structures are in the form of trenches, where a width at a bottom of the trench is less than a width at a top of the trench. In some embodiments, each strain source and drain structure has an increasing dopant gradient concentration from a periphery of the strain source and drain structure to a center of the strain source and drain structure.

[0098] Some other embodiments of the present disclosure are directed to a transistor including a substrate. The substrate includes a fin extending between two source / drain regions. A gate dielectric layer is present on at least three sides of the fin between the two source / drain regions. A gate layer is on the gate dielectric layer. Gate spacers are on sidewalls of the gate layer; lightly doped drain (LDD) regions extend from each source / drain region below the gate dielectric layer. A plurality of strain source and drain (SSD) structures are present within each LDD region, where the SSD structures do not extend below the gate spacers. In some embodiments, a separation width of about 10 nm to about 100 nm is present between adjacent strain source and drain structures. In some embodiments, each strain source and drain structure has an increasing dopant gradient concentration from a periphery of the strain source and drain structure to a center of the strain source and drain structure.

[0099] The present disclosure also discloses a semiconductor assembly including one or more transistors having the above-described structures. For example, the transistors can be encapsulated with an ILD region, an insulating layer, and an electrode extending through the insulating layer as previously described.

[0100] The methods, systems, and assemblies of the present disclosure are further illustrated in the following non-limiting examples, which should not be construed as limiting the described materials, conditions, process parameters, and the like.

[0101] Examples:

[0102] Transistors according to the present disclosure were tested at three different temperatures (-40°C, 25°C, and 125°C). FIG. 23The graph is a plot of drain leakage current versus drain voltage at three temperature conditions. As shown, the leakage current does not significantly increase until the drain voltage is greater than 8V.

[0103] The foregoing overview of the features of several embodiments enables a better understanding of the aspects of the disclosure. Those skilled in the art will readily recognize from the disclosure that the scope of the disclosure is not limited to the embodiments recited, that means other than those described can be employed, and that numerous modifications can be made to the embodiments described without departing from the spirit and scope of the disclosure.

Claims

1. A transistor, comprising: Comprising: a substrate; a gate stack layer over the substrate, the gate stack layer comprising a gate dielectric layer and a gate structure over the gate dielectric layer; a first and a second lightly doped drain region extending from below the gate stack layer to opposite sides of the gate stack layer; a gate spacer on sidewalls of the gate stack layer over the first and second lightly doped drain regions; and a strained source and drain structure within each lightly doped drain region, wherein the strained source and drain structure does not extend below the gate spacer. wherein the strained source and drain structure is in the form of a trench, wherein a width at a bottom of the trench is less than a width at a top of the trench.

2. The transistor of claim 1, wherein wherein each strained source and drain structure has an increasing dopant gradient concentration from a periphery of the strained source and drain structure to a center of the strained source and drain structure.

3. The transistor of claim 1, wherein Comprising:

4. A transistor, characterized by a substrate comprising a plurality of fins extending between two source / drain regions; a gate dielectric layer on at least three sides of the fins between the two source / drain regions; a gate layer over the gate dielectric layer; a gate spacer on sidewalls of the gate layer; a lightly doped drain region extending from each source / drain region below the gate dielectric layer; and a strained source and drain structure within each lightly doped drain region, wherein the strained source and drain structure does not extend below the gate spacer. wherein a spacing width of 10 nanometers to 100 nanometers exists between adjacent strained source and drain structures. wherein each strained source and drain structure has an increasing dopant gradient concentration from a periphery of the strained source and drain structure to a center of the strained source and drain structure.

5. The transistor of claim 4, wherein ​ 6. The transistor of claim 4, wherein ​

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