Driving circuit

Abstract

The utility model discloses a driving circuit. The driving circuit includes a stage including: a seventh transistor and an eighth transistor electrically connected between a first terminal for receiving a first voltage and a second terminal for receiving a second voltage lower than the first voltage; a ninth transistor and a tenth transistor electrically connected between the first terminal and the second terminal; a fourth transistor including a gate electrically connected to a first node configured to receive a start signal and a back gate electrically connected to a third node, and electrically connected between the second terminal and a second node to which the gate of the eighth transistor is electrically connected; a fifth transistor electrically connected between the first node and the third node, and including a gate electrically connected to the second terminal; and a second capacitor electrically connected to the third node and a second output node between the ninth transistor and the tenth transistor.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0027502, filed on February 26, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to a driving circuit for outputting gate signals and a display device including the driving circuit. Background Technology

[0004] The display device includes a pixel region containing multiple pixels, a gate driving circuit, a data driving circuit, and / or a controller. The gate driving circuit includes stages connected to gate lines, and these stages supply gate signals to the gate lines connected thereto in response to signals from the controller. Utility Model Content

[0005] One or more embodiments include a drive circuit capable of stably outputting a gate signal at low power and a display device including the drive circuit. The technical solutions to be achieved by this disclosure are not limited to the above-described technical solutions, and those skilled in the art can clearly understand other technical solutions not mentioned above from the description of this disclosure.

[0006] Other aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0007] According to one or more embodiments, a driving circuit includes a stage comprising: a first output circuit configured to output an output signal and including a seventh transistor and an eighth transistor electrically connected between a first voltage input terminal for receiving a first voltage and a second voltage input terminal for receiving a second voltage lower than the first voltage; a second output circuit configured to output a carry signal and including a ninth transistor and a tenth transistor electrically connected between the first voltage input terminal and the second voltage input terminal; and a control circuit electrically connected to the first output circuit, the second output circuit, and an input terminal configured to receive a start signal, and including: a fourth transistor including a gate electrically connected to a first node configured to receive the start signal and a back gate electrically connected to a third node, and electrically connected between the second voltage input terminal and a second node to which the gate of the eighth transistor is electrically connected; a fifth transistor electrically connected between the first node and the third node and including a gate electrically connected to the second voltage input terminal; and a second capacitor electrically connected to the third node and a second output node between the ninth transistor and the tenth transistor.

[0008] When the voltage of the first node is high, the voltage of the third node can be at a high level that is substantially equal to the high level of the voltage of the first node. When the voltage of the first node is low, the voltage of the third node is at a low level that is lower than the low level of the voltage of the first node.

[0009] The fourth transistor can be an N-channel transistor, and the fifth transistor can be a P-channel transistor.

[0010] The fourth transistor can be an oxide transistor, and the fifth transistor can be a silicon transistor.

[0011] The first output circuit may further include a sixth transistor electrically connected between the second voltage input terminal and the first output node, and includes a gate electrically connected to a third node, the first output node being located between the seventh transistor and the eighth transistor.

[0012] The control circuit may further include: a first transistor electrically connected between the input terminal and the first node, and including a gate electrically connected to a first clock terminal configured to receive a first clock signal; and a second transistor electrically connected between the input terminal and the first node, and including a gate electrically connected to a second clock terminal configured to receive a second clock signal.

[0013] The second transistor may further include a back gate electrically connected to a third terminal configured to receive a third voltage lower than the second voltage.

[0014] The second clock signal can be the inverted version of the first clock signal.

[0015] The control circuit may further include a third transistor electrically connected between the first voltage input terminal and the second node and including a gate electrically connected to the first node.

[0016] The eighth transistor may include a back gate electrically connected to a third terminal configured to receive a third voltage lower than the second voltage.

[0017] The tenth transistor may include a back gate electrically connected to a third terminal configured to receive a third voltage lower than the second voltage.

[0018] The driving circuit may further include: a third output circuit, including a thirteenth transistor and a fourteenth transistor electrically connected between the first voltage input terminal and the second voltage input terminal, and configured to output a second carry signal, wherein the second carry signal is at a low level when the carry signal is at a high level, and wherein the second carry signal is at a high level when the carry signal is at a low level.

[0019] The control circuit may further include: a twelfth transistor electrically connected between the second node and the fourth node, and including a gate electrically connected to the second voltage input terminal; and a third capacitor electrically connected to the fourth node and a third output node between the thirteenth transistor and the fourteenth transistor, wherein the eighth transistor includes a back gate electrically connected to the fourth node.

[0020] When the voltage of the second node is high, the voltage of the fourth node can be at a high level that is substantially equal to the high level of the voltage of the second node. When the voltage of the second node is low, the voltage of the fourth node is at a low level that is lower than the low level of the voltage of the second node.

[0021] According to one or more embodiments, the driving circuit includes a stage comprising: a seventh transistor and an eighth transistor electrically connected between a first voltage input terminal configured to receive a first voltage and a second voltage input terminal configured to receive a second voltage lower than the first voltage, and configured to transmit an output signal to a first output terminal; a ninth transistor and a tenth transistor electrically connected between the first voltage input terminal and the second voltage input terminal, and configured to transmit a carry signal to a second output terminal; a first transistor electrically connected between a first node and an input terminal configured to receive a start signal, and including a gate configured to receive a clock signal; and a fourth transistor electrically connected between the second voltage input terminal and a second node to which the gate of the eighth transistor is electrically connected, and including a gate electrically connected to the first node and a back gate configured to receive an AC voltage.

[0022] The driving circuit may further include: a fifth transistor electrically connected between the first node and the third node, and including a gate electrically connected to the second voltage input terminal; and a second capacitor electrically connected to the third node and the second output terminal, wherein the back gate of the fourth transistor is electrically connected to the third node.

[0023] When the voltage of the first node is high, the voltage of the third node can be at a high level that is substantially equal to the high level of the voltage of the first node. When the voltage of the first node is low, the voltage of the third node is at a low level that is lower than the low level of the voltage of the first node.

[0024] The driving circuit may further include: a sixth transistor electrically connected between the first output terminal and the second voltage input terminal, and including a gate electrically connected to the third node.

[0025] The driving circuit may further include: a thirteenth transistor and a fourteenth transistor electrically connected between a first voltage input terminal and a second voltage input terminal and configured to transmit a second carry signal to a third output terminal; a twelfth transistor electrically connected between a second node and a fourth node and including a gate electrically connected to the second voltage input terminal; and a third capacitor electrically connected to the fourth node and the third output terminal, wherein the eighth transistor includes a back gate electrically connected to the fourth node.

[0026] When the voltage of the second node is high, the voltage of the fourth node can be at a high level that is substantially equal to the high level of the voltage of the second node. When the voltage of the second node is low, the voltage of the fourth node is at a low level that is lower than the low level of the voltage of the second node. Attached Figure Description

[0027] The above and other aspects of the embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 It is a schematic diagram illustrating a stage of a drive circuit according to one or more embodiments;

[0029] Figure 2 It is a schematic diagram illustrating signals input to a transistor included in a stage according to one or more embodiments;

[0030] Figure 3 It is a schematic diagram illustrating a drive circuit according to one or more embodiments;

[0031] Figure 4 It is a schematic diagram illustrating the input and output signals of a drive circuit according to one or more embodiments;

[0032] Figure 5 It is a schematic illustration including Figure 3 A diagram illustrating an example of a stage in a drive circuit;

[0033] Figure 6 It is used to describe Figure 5 Timing diagram of the driver at each level;

[0034] Figure 7 It is a schematic illustration including Figure 3 A diagram illustrating an example of a stage in a drive circuit;

[0035] Figure 8 It is used to describe Figure 7 The timing diagram of the driver at the level; and

[0036] Figure 9 This is a schematic diagram illustrating a display device according to one or more embodiments. Detailed Implementation

[0037] Various aspects of some embodiments of this disclosure and their implementation methods can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be comprehensive and complete, and will fully convey aspects of this disclosure to those skilled in the art. Accordingly, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments or are not essential for a full understanding of aspects of this disclosure by those skilled in the art may be omitted. Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore their repeated description may be omitted.

[0038] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown herein. The terms "can," "may," or "may not" are used in the description of embodiments to correspond to one or more embodiments of this disclosure.

[0039] In view of the overall content of this disclosure, those skilled in the art will understand that this disclosure covers all modifications, equivalents and substitutions within the scope of the ideas and techniques of this disclosure, each of the features of the embodiments of this disclosure may be combined with each other in part or in whole, and various interlocks and operations are technically possible, and each embodiment may be implemented independently of each other or may be implemented together in combination, unless otherwise stated or implied.

[0040] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, this disclosure is not limited thereto because the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of description.

[0041] It will be understood that when an element, layer, region, or component is referred to as "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component," it can be directly formed on, directly connected to, or coupled to that other element, layer, region, or component, or indirectly formed on, indirectly connected to, or coupled to that other element, layer, region, or component, such that one or more intermediary elements, layers, regions, or components may be present. Additionally, this can collectively refer to direct or indirect coupling or connection, as well as integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically coupled" to another layer, region, or component, it can be directly electrically connected or coupled to that other layer, region, or component, or one or more intermediary layers, regions, or components may be present. One or more intermediary components may include switches, resistors, and / or capacitors, etc. In describing embodiments, unless explicitly described as a direct connection, the expression "connection" refers to an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected to or coupled to another component or on another component without an intermediary component.

[0042] Furthermore, in this specification, when a portion of a layer, film, region, or plate is formed on another portion, the forming direction is not limited to the upward direction, but includes forming the portion on a side surface or in a downward direction. Conversely, when a portion of a layer, film, region, or plate is formed "below" another portion, this includes not only the case where the portion is "directly below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing the relationship between components, such as "between," "immediately between," "adjacent to," and "directly adjacent to," can be interpreted similarly. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0043] For the purposes of this disclosure, expressions such as “at least one of” or “any one of” or “one or more of” modify the entire list of elements when placed after a list of elements, without modifying any individual element in that list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more items in the relevant list. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, expressions such as “at least one of”, “multiple”, “one of”, and other prepositional phrases modify the entire list of elements when placed before or after a list of elements, without modifying any individual element in that list. Unless otherwise stated, when “C to D” is stated, it means above C and below D.

[0044] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms do not correspond to a particular order, position, or advantage, and are used only to distinguish one element, component, part, area, region, layer, segment, or part from another element, component, part, area, region, layer, segment, or part. Therefore, the first element, component, area, layer, or segment described below may be referred to as the second element, component, area, layer, or segment without departing from the spirit and scope of this disclosure. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or sets. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first set),” “second category (or second set),” etc.

[0045] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, the singular form “a” is intended to include the plural form as well, and the plural form is intended to include the singular form, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and variations thereof, “having” and variations thereof, and “including” and variations thereof, when used in this specification, indicate the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0046] As used herein, the terms “substantially,” “approximately,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to describe the inherent deviations of measured or calculated values ​​that will be recognized by those skilled in the art. For example, “substantially” can include a range of + / - 5% of the corresponding value. Taking into account the measurement in question and the error associated with the measured value of a particular quantity (i.e., limitations of the measurement system), “approximately” or “approximately” as used herein includes the stated value and means within an acceptable range of deviation for that particular value as determined by those skilled in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.”

[0047] In some embodiments, well-known structures and arrangements may be described in the accompanying drawings with respect to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, storage elements, wire connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled by software to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and processors performing functions different from those of the dedicated hardware (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, in some embodiments, blocks, units, and / or modules may be physically separated into two or more interacting individual blocks, units, and / or modules without departing from the scope of this disclosure. Additionally, in some embodiments, blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules without departing from the scope of this disclosure.

[0048] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] In the following embodiments, "ON" used in conjunction with device states can refer to the active state of the device, and "OFF" can refer to the deactivated state of the device. "ON" used in conjunction with a signal received by the device can refer to a signal that activates the device, and "OFF" can refer to a signal that deactivated the device. The device can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) can be activated by a low-level voltage, and an N-channel transistor (N-type transistor) can be activated by a high-level voltage. Therefore, it should be understood that the "ON" voltage for P-channel and N-channel transistors are opposite (low to high) voltage levels. In the following text, the voltage that activates (turns on) the transistor will be referred to as the gate on voltage, and the voltage that deactivates (turns off) the transistor will be referred to as the gate off voltage.

[0050] Figure 1 This is a schematic diagram illustrating a stage of a drive circuit according to one or more embodiments. Figure 2 It is a schematic diagram illustrating signals input to a transistor included in a stage according to one or more embodiments.

[0051] The drive circuit may include multiple stages ST, and each stage ST may receive at least one input signal In and generate at least one output signal Out. The at least one input signal In may include a start signal, at least one clock signal, and / or at least one voltage signal.

[0052] Each stage ST can include multiple transistors. Some of these transistors can be P-channel transistors, and some others can be N-channel transistors.

[0053] Each of the P-channel and N-channel transistors can be a three-terminal device including a gate G, a source S, and a drain D. In one or more embodiments, each of the P-channel and N-channel transistors can be a four-terminal device including a gate G, a source S, a drain D, and a back gate BG.

[0054] A P-channel transistor can be a silicon transistor. A silicon transistor can include silicon semiconductors, and silicon semiconductors can include amorphous silicon or polycrystalline silicon, etc. For example, a silicon transistor can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The gate on-voltage of a P-channel transistor can be a low-level voltage, and its gate off-voltage can be a high-level voltage.

[0055] An N-channel transistor can be an oxide transistor. An oxide transistor can include an oxide semiconductor, and the oxide semiconductor can include zinc oxide materials such as zinc oxide, indium zinc oxide, or gallium indium zinc oxide. In some embodiments, the oxide semiconductor can be an indium gallium zinc oxide (IGZO) semiconductor. In some embodiments, the oxide semiconductor can be an indium tin gallium zinc oxide (ITGZO) semiconductor. For example, an oxide transistor can be a low-temperature polycrystalline oxide (LTPO) thin-film transistor. The gate on-voltage of an N-channel transistor can be a high-level voltage, and its gate off-voltage can be a low-level voltage.

[0056] For a 4-terminal N-channel oxide transistor, when a (-) voltage is applied to its back gate BG, its threshold voltage can be increased and thus can be positively offset (positive offset), and when a (+) voltage is applied to its back gate BG, the threshold voltage can be decreased and thus can be negatively offset (negative offset).

[0057] The threshold voltage of an oxide transistor (OMT) may decrease due to process dispersion, and therefore, the OMT may not be turned off. To adjust the threshold voltage of an OMT, a (-) voltage can be applied to its back gate (BG) to positively shift the threshold voltage. However, as a result, the operating speed of the OMT may decrease, and therefore, its on-current may decrease. When a (+) voltage is applied to the back gate (BG) of the OMT, the decrease in operating speed and the decrease in on-current can be reduced or minimized, but its threshold voltage can be negatively shifted.

[0058] In one or more embodiments, such as Figure 2 As shown, an alternating current (AC) voltage can be applied to the back gate BG of the N-channel oxide transistor. For example, during some periods of operation of stage ST, a (-) voltage can be applied to the back gate BG of the N-channel oxide transistor, and during some other periods, a (+) voltage can be applied to the back gate BG of the N-channel oxide transistor. The (-) voltage can be referred to as a low-level voltage, and the (+) voltage can be referred to as a high-level voltage. In one or more embodiments, the AC voltage can be the voltage of the corresponding node in stage ST whose voltage level changes.

[0059] Figure 3 This is a schematic diagram illustrating a drive circuit according to one or more embodiments. Figure 4 This is a schematic diagram illustrating the input and output signals of a drive circuit according to one or more embodiments.

[0060] refer to Figure 3The drive circuit DRV according to one or more embodiments may include multiple stages ST1 to STn. The multiple stages ST1 to STn can sequentially output output signals OUT[1], OUT[2], OUT[3], OUT[4], ..., OUT[n] to signal lines.

[0061] Each of stages ST1 to STn may include multiple terminals through which multiple signals are input. The multiple signals may include clock signals and voltage signals. The multiple terminals may include input terminal IN, first voltage input terminal V1, second voltage input terminal V2, third voltage input terminal V3, first clock terminal CK1, second clock terminal CK2, first output terminal GOUT, and second output terminal COUT.

[0062] A start signal can be input (supplied) to the input terminal IN. Multiple stages ST1 to STn can output output signals OUT[1], OUT[2], OUT[3], OUT[4], ..., OUT[n] respectively in response to the start signal. The start signal can be an external signal FLM or a carry signal CR[1], CR[2], CR[3], CR[4], ..., CR[n-1]. The external signal FLM can be input as a start signal to the input terminal IN of the first stage ST1, and the carry signal output from the previous stage (hereinafter referred to as the "carry signal") can be input as a start signal to the input terminal IN of each of the second stage ST2 to the nth stage STn. The previous stage can be the stage located at least one stage before the current stage. Figure 3 The diagram illustrates an example where the preceding stage is the stage immediately preceding the current stage. For example, the carry signal CR[3] output from the third stage ST3 can be input as a start signal to the input terminal IN of the fourth stage ST4.

[0063] A first voltage VGH can be input to a first voltage input terminal V1, a second voltage VGL can be input to a second voltage input terminal V2, and a third voltage VGL2 can be input to a third voltage input terminal V3. The second voltage VGL can be lower than the first voltage VGH. The third voltage VGL2 can be lower than the second voltage VGL. The third voltage VGL2 can be approximately 3V lower than the second voltage VGL, but this disclosure is not limited thereto. The difference between the second voltage VGL and the third voltage VGL2 can be determined based on the threshold voltage variation of the transistor supplied as the third voltage VGL2 as the back gate voltage. In one or more embodiments, the first voltage VGH can be approximately 7.5V and the second voltage VGL can be approximately -9V, but this disclosure is not limited thereto. Hereinafter, the first voltage VGH can be referred to as a high-level voltage, and the second voltage VGL and the third voltage VGL2 can be referred to as low-level voltages.

[0064] A first clock signal CLK1 or a second clock signal CLK2 can be input to a corresponding one of the first clock terminal CK1 and the second clock terminal CK2. The first clock signal CLK1 and the second clock signal CLK2 can be alternately input to the first clock terminal CK1 of stages ST1 to STn. The second clock signal CLK2 and the first clock signal CLK1 can be alternately input to the second clock terminal CK2 of stages ST1 to STn. In one or more embodiments, the first clock signal CLK1 and the second clock signal CLK2 can be input to the first clock terminal CK1 and the second clock terminal CK2 of odd-numbered stages ST1, ST3, ... The second clock signal CLK2 and the first clock signal CLK1 can be input to the first clock terminal CK1 and the second clock terminal CK2 of even-numbered stages ST2, ST4, ... Conversely, in one or more embodiments, the second clock signal CLK2 and the first clock signal CLK1 can be input to the first clock terminal CK1 and the second clock terminal CK2 of the odd-numbered ST1, ST3, ... and the first clock signal CLK1 and the second clock signal CLK2 can be input to the first clock terminal CK1 and the second clock terminal CK2 of the even-numbered ST2, ST4, ...

[0065] like Figure 4 As shown, the first clock signal CLK1 and the second clock signal CLK2 can be square wave signals alternating between high-level voltages and low-level voltages. In one or more embodiments, the first clock signal CLK1 and the second clock signal CLK2 can be square wave signals alternating between a first voltage VGH and a second voltage VGL. The first clock signal CLK1 and the second clock signal CLK2 can be signals that are out of phase with each other. In one or more embodiments, for one of the first clock signal CLK1 and the second clock signal CLK2, the duration for which a high-level voltage is held in one cycle can be shorter than the duration for which a low-level voltage is held in one cycle, and for the other, the duration for which a high-level voltage is held in one cycle can be longer than the duration for which a low-level voltage is held in one cycle. In one or more embodiments, for the first clock signal CLK1 and the second clock signal CLK2, the duration for which a high-level voltage is held in one cycle can be equal to the duration for which a low-level voltage is held in one cycle.

[0066] The output signal can be output from the first output terminal GOUT. For example... Figure 4As shown, the output signals OUT[1], OUT[2], OUT[3], OUT[4], ..., OUT[n] output from the first output terminal GOUT of stages ST1 to STn can be sequentially offset by corresponding intervals. In one or more embodiments, stages ST1 to STn can be sequentially output by offsetting each of the high-level voltage output signals OUT[1], OUT[2], OUT[3], OUT[4], ..., OUT[n] by 1 / 2 cycle of the clock signal.

[0067] The carry signal can be output from the second output terminal COUT. For example... Figure 4 As shown, the carry signals CR[1], CR[2], CR[3], CR[4], ..., CR[n] output from the second output terminal COUT of stages ST1 to STn can be sequentially offset by corresponding intervals. In one or more embodiments, stages ST1 to STn can be sequentially output by offsetting each of the high-level carry signals CR[1], CR[2], CR[3], CR[4], ..., CR[n] by half a cycle of the clock signal.

[0068] A reset signal ESR can be input to the reset terminal RS. The gate-on voltage reset signal ESR can be input to the transistor gate at a corresponding timing, and the gate-off voltage reset signal ESR can be input to the transistor gate at other timings. For example, when power is applied to the display device (power on), the reset signal ESR can be input as the gate-on voltage to stages ST1 to STn for a corresponding time period, and can be input as the gate-off voltage to stages ST1 to STn after the corresponding time period has elapsed. While stages ST1 to STn operate to generate the gate signal, the reset signal ESR can be input as the gate-off voltage.

[0069] Figure 5 It is a schematic illustration including Figure 3 A diagram illustrating an example of a stage in a drive circuit. Figure 6 It is used to describe Figure 5 Timing diagram of the driver at the level.

[0070] refer to Figure 5 Level STa may include control circuitry 131, a first output circuitry 133, and a second output circuitry 135. Level STa may further include a reset circuitry 139. Level STa may include multiple nodes, and in the following text, some of these nodes will be referred to as first to third nodes NA, NB, and NC.

[0071] Each of the control circuit 131, the first output circuit 133, and the second output circuit 135 may include at least one transistor. In one or more embodiments, the at least one transistor may include an N-channel transistor and / or a P-channel transistor. In one or more embodiments, the dopant conductivity type of the second transistor T2, the fourth transistor T4, the eighth transistor (e.g., a first pull-down transistor) T8, and the tenth transistor (e.g., a second pull-down transistor) T10 of stage STa may be opposite to the dopant conductivity type of the other transistors. For example, the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 may be N-channel transistors, and the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor (e.g., a first pull-up transistor) T7, the ninth transistor (e.g., a second pull-up transistor) T9, and the eleventh transistor T11 may be P-channel transistors.

[0072] Control circuit 131 can control the voltages of the first node NA and the second node NB in ​​response to a start signal STV input via input terminal IN. The start signal STV can be an external signal FLM or a carry signal CR (see...). Figure 3 The control circuit 131 may include a first transistor T1 through a fifth transistor T5. The control circuit 131 may further include a first capacitor C1 and a second capacitor C2.

[0073] The first transistor T1 can be connected between the input terminal IN and the first node NA. The gate of the first transistor T1 can be connected to the first clock terminal CK1. When the clock signal CLK applied to the first clock terminal CK1 is low, the first transistor T1 can be turned on to transmit the start signal STV input through the input terminal IN to the first node NA.

[0074] The second transistor T2 can be connected between the input terminal IN and the first node NA. The second transistor T2 can be connected in parallel with the first transistor T1. The gate of the second transistor T2 can be connected to the second clock terminal CK2. When the clock signal CLK applied to the second clock terminal CK2 is high, the second transistor T2 can be turned on to transmit the start signal STV input through the input terminal IN to the first node NA.

[0075] When the start signal STV is transmitted to the first node NA, the first transistor T1 and the second transistor T2 can compensate for the voltage loss of the start signal STV caused by the threshold voltage of the first transistor T1 or the second transistor T2. In one or more embodiments, one of the first transistor T1 and the second transistor T2 may be omitted.

[0076] In one or more embodiments, the clock signal CLK input to the gate of the first transistor T1 can be a first clock signal CLK1, and the clock signal CLK input to the gate of the second transistor T2 can be a second clock signal CLK2. In one or more embodiments, the clock signal CLK input to the gate of the first transistor T1 can be a second clock signal CLK2, and the clock signal CLK input to the gate of the second transistor T2 can be a first clock signal CLK1.

[0077] The second transistor T2 may further include a four-terminal dual-gate transistor comprising a back gate connected to a third voltage input terminal V3 configured to supply a third voltage VGL2. The gate of the second transistor T2 may be a top gate located above the semiconductor, and its back gate may be a bottom gate located below the semiconductor. The gate and back gate may overlap with the channel region of the semiconductor. When the third voltage VGL2 is input to the back gate of the second transistor T2, the threshold voltage of the second transistor T2 may be positively offset.

[0078] The third transistor T3 can be connected between the first voltage input terminal V1 and the second node NB. The gate of the third transistor T3 can be connected to the first node NA. When the voltage of the first node NA is low, the third transistor T3 can be turned on to transmit the first voltage VGH input through the first voltage input terminal V1 to the second node NB.

[0079] The fourth transistor T4 can be connected between the second node NB and the second voltage input terminal V2. The gate of the fourth transistor T4 can be connected to the first node NA. When the voltage of the first node NA is high, the fourth transistor T4 can be turned on to transmit the second voltage VGL input through the second voltage input terminal V2 to the second node NB.

[0080] The fourth transistor T4 may be a four-terminal dual-gate transistor that further includes a back gate connected to the third node NC. The gate of the fourth transistor T4 may be a top gate located above the semiconductor, and its back gate may be a bottom gate located below the semiconductor. The voltage input to the back gate of the fourth transistor T4 may be an AC voltage that alternates between a high-level voltage and a low-level voltage.

[0081] In one or more embodiments, a low-level voltage can be applied to the back gate of the fourth transistor T4 when the output gate cutoff voltage is OUT, and a high-level voltage can be applied to the back gate of the fourth transistor T4 when the output gate turn-on voltage is OUT. Therefore, by positively shifting the threshold voltage of the fourth transistor T4, the output gate turn-on voltage can be reduced or minimized (e.g., prevented) from being present when the output gate turn-on voltage is OUT.

[0082] The fourth transistor T4 experiences a decrease in on-current and a reduction in operating speed.

[0083] In one or more embodiments, while the first node NA is low, the voltage of the third node NC can become low, and thus, the threshold voltage of the fourth transistor T4 can be positively shifted. When the first node NA is high, the voltage of the third node NC can become high, and thus, the on-state current of the fourth transistor T4 can increase.

[0084] The fifth transistor T5 can be connected between the first node NA and the third node NC. The gate of the fifth transistor T5 can be connected to the second voltage input terminal V2. When the voltage of the first node NA is high, the fifth transistor T5 can be turned on by the second voltage VGL input via the second voltage input terminal V2, so as to electrically connect the first node NA and the third node NC to each other.

[0085] A first capacitor C1 can be connected between the first voltage input terminal V1 and the first node NA. The first capacitor C1 can be configured to stabilize the voltage of the first node NA. A second capacitor C2 can be connected between the third node NC and the second output terminal COUT. The second capacitor C2 can be a capacitor configured to bootstrap the voltage of the third node NC.

[0086] In one or more embodiments, the fifth transistor T5 and the second capacitor C2 may be an AC voltage generation circuit configured to control the voltage of the third node NC to a high-level voltage or a low-level voltage. The back gate of the fourth transistor T4 may be connected to the third node NC to receive the AC voltage input.

[0087] The first output circuit 133 can be connected between the first voltage input terminal V1 and the second voltage input terminal V2. The first output circuit 133 can output a high-level voltage or a low-level voltage output signal OUT according to the voltage of the second node NB. The first output circuit 133 may include a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The node between the seventh transistor T7 and the eighth transistor T8 (e.g., the first output node) can be the first output terminal GOUT.

[0088] A seventh transistor T7 can be connected between the first voltage input terminal V1 and the first output terminal GOUT. The gate of the seventh transistor T7 can be connected to the second node NB. The seventh transistor T7 can be a pull-up transistor configured to transfer a high-level voltage to the first output terminal GOUT. When the voltage of the second node NB is low, the seventh transistor T7 can be turned on to transfer the first voltage VGH input through the first voltage input terminal V1 to the first output terminal GOUT.

[0089] The eighth transistor T8 can be connected between the first output terminal GOUT and the second voltage input terminal V2. The gate of the eighth transistor T8 can be connected to the second node NB. The eighth transistor T8 can be a pull-down transistor configured to transmit a low-level voltage to the first output terminal GOUT. When the voltage of the second node NB is high, the eighth transistor T8 can be turned on to transmit the second voltage VGL input through the second voltage input terminal V2 to the first output terminal GOUT.

[0090] The eighth transistor T8 may further include a four-terminal dual-gate transistor comprising a back gate connected to a third voltage input terminal V3 configured to supply a third voltage VGL2. The gate of the eighth transistor T8 may be a top gate located above the semiconductor, and its back gate may be a bottom gate located below the semiconductor. When the third voltage VGL2 is input to the back gate of the eighth transistor T8, the threshold voltage of the eighth transistor T8 may be positively offset.

[0091] A sixth transistor T6 can be connected between the first output terminal GOUT and the second voltage input terminal V2. The gate of the sixth transistor T6 can be connected to the third node NC. The sixth transistor T6 can be a pull-down transistor configured to transmit a low-level voltage to the first output terminal GOUT. When the voltage of the third node NC is low, the sixth transistor T6 can be turned on to transmit the second voltage VGL input through the second voltage input terminal V2 to the first output terminal GOUT.

[0092] The second output circuit 135 can be connected between the first voltage input terminal V1 and the second voltage input terminal V2. The second output circuit 135 can output a carry signal CR of either a high-level voltage or a low-level voltage based on the voltage at the second node NB. The second output circuit 135 may include a ninth transistor T9 and a tenth transistor T10. The node between the ninth transistor T9 and the tenth transistor T10 (e.g., the second output node) can be the second output terminal COUT.

[0093] The ninth transistor T9 can be connected between the first voltage input terminal V1 and the second output terminal COUT. The gate of the ninth transistor T9 can be connected to the second node NB. The ninth transistor T9 can be a pull-up transistor configured to transfer a high-level voltage to the second output terminal COUT. When the voltage of the second node NB is low, the ninth transistor T9 can be turned on to transfer the first voltage VGH input through the first voltage input terminal V1 to the second output terminal COUT.

[0094] The tenth transistor T10 can be connected between the second output terminal COUT and the second voltage input terminal V2. The gate of the tenth transistor T10 can be connected to the second node NB. The tenth transistor T10 can be a pull-down transistor configured to transmit a low-level voltage to the second output terminal COUT. When the voltage of the second node NB is high, the tenth transistor T10 can be turned on to transmit the second voltage VGL input through the second voltage input terminal V2 to the second output terminal COUT.

[0095] The tenth transistor T10 may further include a four-terminal dual-gate transistor comprising a back gate connected to a third voltage input terminal V3 configured to supply a third voltage VGL2. The gate of the tenth transistor T10 may be a top gate located above the semiconductor, and its back gate may be a bottom gate located below the semiconductor. When the third voltage VGL2 is input to the back gate of the tenth transistor T10, the threshold voltage of the tenth transistor T10 may be positively offset.

[0096] The reset circuit 139 can reset the first node NA based on the reset signal ESR supplied to the reset terminal RS. The reset circuit 139 may include an eleventh transistor T11 (reset transistor). The eleventh transistor T11 may be connected between the first voltage input terminal V1 and the first node NA. The gate of the eleventh transistor T11 may be connected to the reset terminal RS. When a low-level reset signal ESR is applied to the reset terminal RS, the eleventh transistor T11 can be turned on to set the voltage of the first node NA to a first voltage VGH.

[0097] In the following text, reference will be made to Figure 6 describe Figure 5 The operations at each level are illustrated in the diagram. For ease of description, the following will be described. Figure 5 The current stage STa is an example of an odd-numbered stage, where a first clock signal CLK1 is input to a first clock terminal CK1 and a second clock signal CLK2 is input to a second clock terminal CK2. An even-numbered stage differs from an odd-numbered stage only in that the second clock signal CLK2 is input to the first clock terminal CK1 and the first clock signal CLK1 is input to the second clock terminal CK2, and the construction and operation of an even-numbered stage can be substantially the same as those of an odd-numbered stage. The start signal STV of the first stage (e.g., first stage ST1) can be an external signal FLM, and the start signal STV of the second and subsequent stages can be a carry signal (carry signal CR') output from the previous stage. Figure 6 It is one of them Figure 5 The sequence diagram of level STa is an example of a level in the odd-numbered levels after the second level.

[0098] In the first interval P1, a high-level carry signal CR' can be input to the input terminal IN, a high-level first clock signal CLK1 can be input to the first clock terminal CK1, and a low-level second clock signal CLK2 can be input to the second clock terminal CK2.

[0099] Because the first transistor T1 is turned off by the high-level first clock signal CLK1 and the second transistor T2 is turned off by the low-level second clock signal CLK2, the voltage at the first node NA can remain low and the voltage at the second node NB can remain high, as in the previous interval. The second voltage VGL can be transmitted to the first output terminal GOUT through the conducting eighth transistor T8, and the second voltage VGL can be transmitted to the second output terminal COUT through the conducting tenth transistor T10. Accordingly, a low-level output signal OUT and a low-level carry signal CR can be output.

[0100] Furthermore, because the voltage at the first node NA is low, the fifth transistor T5 can be turned off, and through the coupling of the second capacitor C2, the voltage at the third node NC can be maintained below the second voltage VGL. In the first interval P1, the low-level voltage of the first node NA (e.g., approximately equal to the second voltage VGL) can be applied to the gate of the fourth transistor T4, and the low-level voltage of the third node NC, below the second voltage VGL, can be applied to the back gate of the fourth transistor T4. Because the voltage at the third node NC is low, the sixth transistor T6 can be turned on, and the second voltage VGL can be transmitted to the first output terminal GOUT through the turned-on sixth transistor T6. Due to the sixth transistor T6, a stable low-level output signal OUT is possible even when a defect occurs in the eighth transistor T8.

[0101] The low-level voltage NC_LL of the third node NC can be lower than the low-level voltage NA_LL of the first node NA, and can be lower than the low-level voltage NB_LL of the second node NB.

[0102] In the second interval P2, a high-level carry signal CR' can be input to the input terminal IN, a low-level first clock signal CLK1 can be input to the first clock terminal CK1, and a high-level second clock signal CLK2 can be input to the second clock terminal CK2.

[0103] The first transistor T1 can be turned on by a low-level first clock signal CLK1, and the second transistor T2 can be turned on by a high-level second clock signal CLK2. A high-level carry signal CR' can be transmitted to the first node NA through the turned-on first transistor T1 and second transistor T2. Because the voltage at the first node NA is high, the third transistor T3 can be turned off and the fourth transistor T4 can be turned on. A low-level second voltage VGL can be transmitted to the second node NB through the turned-on fourth transistor T4.

[0104] Because the voltage at the second node NB is low, transistors T7 and T9 can be turned on, while transistors T8 and T10 can be turned off. The first voltage VGH can be transmitted to the first output terminal GOUT through the turned-on seventh transistor T7, and a high-level output signal OUT can be output. The first voltage VGH can also be transmitted to the second output terminal COUT through the turned-on ninth transistor T9, and a high-level carry signal CR can be output.

[0105] In the third interval P3, a high-level carry signal CR' can be input to the input terminal IN, a high-level first clock signal CLK1 can be input to the first clock terminal CK1, and a low-level second clock signal CLK2 can be input to the second clock terminal CK2.

[0106] Because the first transistor T1 is turned off by the high-level first clock signal CLK1 and the second transistor T2 is turned off by the low-level second clock signal CLK2, the voltage of the first node NA can remain high and the voltage of the second node NB can remain low, just as in the previous interval. The high-level output signal OUT and the high-level carry signal CR can be output through the conducting seventh transistor T7 and ninth transistor T9.

[0107] In the fourth interval P4, a high-level carry signal CR' can be input to the input terminal IN, a low-level first clock signal CLK1 can be input to the first clock terminal CK1, and a high-level second clock signal CLK2 can be input to the second clock terminal CK2.

[0108] The first transistor T1 can be turned on by a low-level first clock signal CLK1, and the second transistor T2 can be turned on by a high-level second clock signal CLK2. The high-level carry signal CR' can be transmitted to the first node NA through the turned-on first transistor T1 and second transistor T2. The operation of stage STa in the subsequent fourth interval P4 can be the same as the operation of stage STa in the second interval P2. That is, the high-level output signal OUT and the high-level carry signal CR can be output through the turned-on seventh transistor T7 and ninth transistor T9.

[0109] In the fifth interval P5, a high-level carry signal CR' can be input to the input terminal IN, a high-level first clock signal CLK1 can be input to the first clock terminal CK1, and a low-level second clock signal CLK2 can be input to the second clock terminal CK2. The operation of stage STa in the fifth interval P5 is the same as that of stage STa in the third interval P3. That is, the high-level output signal OUT and the high-level carry signal CR can be output through the conducting seventh transistor T7 and ninth transistor T9.

[0110] In the sixth interval P6, a low-level carry signal CR' can be input to the input terminal IN, a high-level first clock signal CLK1 can be input to the first clock terminal CK1, and a low-level second clock signal CLK2 can be input to the second clock terminal CK2.

[0111] Because the first transistor T1 is turned off by the high-level first clock signal CLK1 and the second transistor T2 is turned off by the low-level second clock signal CLK2, regardless of the voltage level of the carry signal CR', the voltage of the first node NA can remain high, and the voltage of the second node NB can remain low, just like in the previous interval. The high-level output signal OUT and the high-level carry signal CR can be output through the conducting seventh transistor T7 and ninth transistor T9.

[0112] Furthermore, during the period from the second interval P2 to the sixth interval P6, because the voltage of the first node NA is at a high level, the fifth transistor T5 can be turned on, and the voltage of the third node NC can be at a high level close to the high level of the first node NA. During the period from the second interval P2 to the sixth interval P6, the high-level voltage of the first node NA can be applied to the gate of the fourth transistor T4, and the high-level voltage of the third node NC can be applied to the back gate of the fourth transistor T4. During the period from the second interval P2 to the sixth interval P6, because the voltage of the third node NC is at a high level, the sixth transistor T6 can be turned off.

[0113] In the seventh interval P7, a low-level carry signal CR' can be input to the input terminal IN, a low-level first clock signal CLK1 can be input to the first clock terminal CK1, and a high-level second clock signal CLK2 can be input to the second clock terminal CK2.

[0114] The first transistor T1 can be turned on by a low-level first clock signal CLK1, and the second transistor T2 can be turned on by a high-level second clock signal CLK2. A low-level carry signal CR' can be transmitted to the first node NA through the turned-on first transistor T1 and the second transistor T2. Because the voltage at the first node NA is low, the third transistor T3 can be turned on, and the fourth transistor T4 can be turned off. A high-level first voltage VGH can be transmitted to the second node NB through the turned-on third transistor T3.

[0115] Because the voltage at the second node NB is high, transistors T7 and T9 can be turned off, while transistors T8 and T10 can be turned on. The second voltage VGL can be transmitted to the first output terminal GOUT through the turned-on eighth transistor T8, and a low-level output signal OUT can be output. The second voltage VGL can be transmitted to the second output terminal COUT through the turned-on tenth transistor T10, and a low-level carry signal CR can be output.

[0116] As the voltage of the first node NA changes from high to low, the fifth transistor T5 can gradually switch from the on state to the off state. Correspondingly, the voltage of the third node NC can drop from high to low. When the carry signal CR drops from high to low while the fifth transistor T5 is off, the third node NC can be bootstrapped through the coupling of the second capacitor C2, and therefore, the voltage of the third node NC can drop further. In this case, the voltage of the third node NC can be determined by the size (capacitance) of the second capacitor C2. In one or more embodiments, in the seventh interval P7, the voltage of the third node NC can be lower than the second voltage VGL. In one or more embodiments, in the seventh interval P7, the voltage level of the third node NC can be approximately similar to the voltage level of the third voltage VGL2.

[0117] After the seventh interval P7, because the low-level carry signal CR' is input to the input terminal IN, even when the first clock signal CLK1 and the second clock signal CLK2 are alternately input at low and high levels, the voltage of the first node NA can remain low and the voltage of the second node NB can remain high. After the seventh interval P7, because the voltage of the third node NC is a low-level voltage lower than the second voltage VGL, a voltage of approximately equal to the second voltage VGL for the first node NA can be applied to the gate of the fourth transistor T4, and a low-level voltage of the third node NC lower than the second voltage VGL can be applied to the back gate of the fourth transistor T4.

[0118] Figure 7 It is a schematic illustration including Figure 3 A diagram illustrating an example of a stage in a drive circuit. Figure 8 It is used to describe Figure 7 Timing diagram of the driver at the level.

[0119] Figure 7 The stage STb illustrated in the diagram may include a control circuit 131', a first output circuit 133', a second output circuit 135, and a third output circuit 137. The stage STb may further include a reset circuit 139. The stage STb may include multiple nodes, and in the following text, some of these nodes will be referred to as the first to fourth nodes NA, NB, NC, and ND. The following description will primarily focus on... Figure 5 The differences between the STa levels shown in the diagram are explained, and for the sake of brevity, redundant descriptions will be omitted.

[0120] and Figure 5 Compared to the control circuit 131 of stage STa shown in the figure, Figure 7 The control circuit 131' of stage STb shown in the figure may further include a twelfth transistor T12 and a third capacitor C3. The control circuit 131' may include first transistors T1 to fifth transistors T5 and twelfth transistor T12. The control circuit 131' may further include a first capacitor C1, a second capacitor C2 and a third capacitor C3.

[0121] The twelfth transistor T12 can be connected between the second node NB and the fourth node ND. The gate of the twelfth transistor T12 can be connected to the second voltage input terminal V2. When the voltage of the second node NB is high, the twelfth transistor T12 can be turned on by the second voltage VGL input via the second voltage input terminal V2, so as to electrically connect the second node NB and the fourth node ND to each other. The twelfth transistor T12 can be a P-channel transistor.

[0122] The third capacitor C3 can be connected between the fourth node ND and the third output terminal COUT2. The third capacitor C3 can be a capacitor configured to bootstrap to a low voltage at the fourth node ND.

[0123] In one or more embodiments, the twelfth transistor T12 and the third capacitor C3 may be an AC voltage generation circuit configured to control the voltage of the fourth node ND to a high-level voltage or a low-level voltage. The back gate of the eighth transistor T8 may be connected to the fourth node ND to receive the applied AC voltage.

[0124] and Figure 5 Compared to the first output circuit 133 of stage STa shown in the diagram, Figure 7 The first output circuit 133' of stage STb shown in the figure can have different back gate connections for the eighth transistor T8. The first output circuit 133' can include a seventh transistor T7 and an eighth transistor T8. The back gate of the eighth transistor T8 can be connected to the fourth node ND. The voltage input to the back gate of the eighth transistor T8 can be an AC voltage that alternates between a high-level voltage and a low-level voltage.

[0125] The second output circuit 135 may include a ninth transistor T9 and a tenth transistor T10.

[0126] Figure 7 The diagram shows the level STb and Figure 5 The difference in stage STa illustrated in the figure lies in that it further includes a third output circuit 137. The third output circuit 137 can be connected between the first voltage input terminal V1 and the second voltage input terminal V2. The third output circuit 137 can output a second carry signal CR2 with a high or low level voltage depending on the voltage at the first output terminal GOUT. In one or more embodiments, the second carry signal CR2 can be the inverted signal of the carry signal CR. In one or more embodiments, the second carry signal CR2 may not be transmitted to the preceding and / or subsequent stages. The second carry signal CR2 may not affect adjacent stages and / or pixels PX (see Figure 1). Figure 9 () is a dummy signal.

[0127] The third output circuit 137 may include a thirteenth transistor (e.g., a third pull-up transistor) T13 and a fourteenth transistor (e.g., a third pull-down transistor) T14. The thirteenth transistor T13 may be a P-channel transistor, and the fourteenth transistor T14 may be an N-channel transistor. The node between the thirteenth transistor T13 and the fourteenth transistor T14 (e.g., the third output node) may be the third output terminal COUT2. The third output circuit 137 may be a circuit for connecting a capacitor that bootstraps the voltage at the fourth node ND to a voltage lower than the second voltage VGL.

[0128] The thirteenth transistor T13 can be connected between the first voltage input terminal V1 and the third output terminal COUT2. The gate of the thirteenth transistor T13 can be connected to the first output terminal GOUT. The thirteenth transistor T13 can be a pull-up transistor configured to transfer a high-level voltage to the third output terminal COUT2. When the voltage at the first output terminal GOUT is low, the thirteenth transistor T13 can be turned on to transfer the first voltage VGH input through the first voltage input terminal V1 to the third output terminal COUT2.

[0129] The fourteenth transistor T14 can be connected between the third output terminal COUT2 and the second voltage input terminal V2. The gate of the fourteenth transistor T14 can be connected to the first output terminal GOUT. The fourteenth transistor T14 can be a pull-down transistor configured to transmit a low-level voltage to the third output terminal COUT2. When the voltage at the first output terminal GOUT is high, the fourteenth transistor T14 can be turned on to transmit the second voltage VGL input through the second voltage input terminal V2 to the third output terminal COUT2.

[0130] The fourteenth transistor T14 may be a four-terminal dual-gate transistor that further includes a back gate connected to a third voltage input terminal V3 configured to supply a third voltage VGL2. The gate of the fourteenth transistor T14 may be a top gate located above the semiconductor, and its back gate may be a bottom gate located below the semiconductor.

[0131] Figure 8 This involves adding the voltage of the fourth node ND and the second carry signal CR2 to... Figure 6 The timing diagram shown in the figure is a timing diagram of the sequence diagram.

[0132] In the first interval P1, because the voltage of the second node NB is at a high level, the twelfth transistor T12 can be turned on, and the voltage of the fourth node ND can be at a high level close to the high level of the voltage of the second node NB. In the first interval P1, the high-level voltage of the second node NB can be applied to the gate of the eighth transistor T8, and the high-level voltage of the fourth node ND can be applied to the back gate of the eighth transistor T8.

[0133] In the second interval P2, as the voltage of the second node NB changes from high to low, the twelfth transistor T12 can gradually switch from the on state to the off state. Correspondingly, the voltage of the fourth node ND can drop from high to low. When the second carry signal CR2 drops from high to low while the twelfth transistor T12 is off, the fourth node ND can be bootstrapped through the coupling of the third capacitor C3, and therefore, the voltage of the fourth node ND can further decrease. In one or more embodiments, in the second interval P2, the voltage of the fourth node ND can be lower than the second voltage VGL.

[0134] During the period from the third interval P3 to the sixth interval P6, because the voltage of the second node NB is at a low level, the twelfth transistor T12 can be turned off, and the voltage of the fourth node ND can be kept at a low level lower than the low level of the second voltage VGL.

[0135] In the second interval P2, a low-level voltage (approximately the second voltage VGL) of the second node NB can be applied to the gate of the eighth transistor T8, and a low-level voltage of the fourth node ND, which is lower than the second voltage VGL, can be applied to the back gate of the eighth transistor T8.

[0136] During and after the seventh interval P7, because the voltage of the second node NB is at a high level, the twelfth transistor T12 can be turned on, and the voltage of the fourth node ND can be at a high level close to the high level of the voltage of the second node NB. During and after the seventh interval P7, the high-level voltage of the second node NB can be applied to the gate of the eighth transistor T8, and the high-level voltage of the fourth node ND can be applied to the back gate of the eighth transistor T8.

[0137] The low-level voltage NC_LL of the third node NC and the low-level voltage ND_LL of the fourth node ND can be lower than the low-level voltage NA_LL of the first node NA, and can be lower than the low-level voltage NB_LL of the second node NB. The low-level voltage NC_LL of the third node NC and the low-level voltage ND_LL of the fourth node ND can be determined based on the size (capacitance) of the second capacitor C2 and the third capacitor C3, respectively.

[0138] Figure 9 This is a schematic diagram illustrating a display device according to one or more embodiments.

[0139] The display device 10 according to one or more embodiments may be a display device such as an organic light-emitting display device, an inorganic light-emitting display device (or an inorganic EL display device) or a quantum dot light-emitting display device.

[0140] refer to Figure 9The display device 10 according to one or more embodiments may include a pixel area 110, a gate driving circuit 130, a data driving circuit 150, a power supply circuit 170, and a controller 190.

[0141] Pixel area 110 may correspond to the display area for displaying an image. Various wires for transmitting electrical signals to be applied to the display area, peripheral drive circuits electrically connected to the pixel circuits, and / or pads attached to the printed circuit board or driver IC chip may be located in a peripheral area (non-display area) outside the display area. For example, gate drive circuit 130, data drive circuit 150, power supply circuit 170, and controller 190 may be provided in the peripheral area.

[0142] Multiple gate lines GL, multiple data lines DL, and multiple pixels PX connected to the gate lines GL and data lines DL can be arranged in pixel area 110. The multiple pixels PX can be repeatedly arranged in a first direction (x-direction or row direction) and a second direction (y-direction or column direction). The multiple pixels PX can be arranged in various forms such as stripe arrangement, pentile arrangement, diamond arrangement, and mosaic arrangement to realize an image. Each of the multiple pixels PX can include an organic light-emitting diode (OLED) as a display element, and the OLED can be connected to pixel circuitry. Pixel circuitry can include multiple transistors and at least one capacitor. Pixel PX can emit light from the OLED, such as red, green, blue, or white light. Each pixel PX can be connected to at least one corresponding gate line of the multiple gate lines GL and a corresponding data line of the multiple data lines DL.

[0143] In one or more embodiments, the plurality of transistors included in the pixel circuit may be P-channel silicon transistors. In one or more embodiments, the plurality of transistors included in the pixel circuit may be N-channel oxide transistors. In one or more embodiments, some of the transistors included in the pixel circuit may be P-channel silicon transistors, and some of the other transistors may be N-channel oxide transistors.

[0144] Each of the gate lines GL can extend in the x-direction (row direction) to connect to a pixel PX located in the same row. Each of the gate lines GL can be configured to transmit a gate signal to a pixel PX in the same row. Each of the data lines DL can extend in the y-direction (column direction) to connect to a pixel PX located in the same column. Each of the data lines DL can be configured to transmit a data signal DATA to each of the pixels PX in the same column in synchronization with the gate signal.

[0145] The gate drive circuit 130 can be connected to multiple gate lines GL, can generate a gate signal GS in response to a gate drive control signal GCS from the controller 190, and can sequentially supply the gate signal GS to the gate lines GL. The gate lines GL can be connected to the gates of transistors included in the pixel PX, and the gate signal GS can be a gate control signal for controlling the on and off states of the transistors to which the gate lines GL are connected. The gate signal GS can include a gate on-voltage that can turn on the transistors and a gate off-voltage that can turn them off. The gate drive circuit 130 can include multiple stages that sequentially generate and output the gate signal GS.

[0146] In one or more embodiments, the gate drive circuit 130 can be implemented as follows: Figure 3 The diagram illustrates the drive circuit DRV. For example, the gate signal GS output by the gate drive circuit 130 to each gate line GL can correspond to a high-level output signal OUT output to a signal line by each of the multiple stages ST1 to STn of the drive circuit DRV. Each of the stages ST1 to STn can be connected to the gate line GL arranged in the corresponding row of the pixel area 110. Each of the stages ST1 to STn can generate the gate signal GS as the output signal OUT and can output the gate signal GS to the connected gate line GL. That is, each of the stages ST1 to STn can supply a high-level gate signal GS to the gate line GL arranged in the corresponding row. In one or more embodiments, each of the stages ST1 to STn of the gate drive circuit 130 can be Figure 5 The level STa or shown in the diagram Figure 7 The diagram shows level STb.

[0147] The number of stages constituting the gate drive circuit 130 according to one or more embodiments can vary depending on the number of rows (horizontal lines) arranged in the pixel area 110.

[0148] The data drive circuit 150 can be connected to multiple data lines DL and can supply data signals DATA to the data lines DL in response to the data drive control signal DCS from the controller 190. The data signal DATA supplied to the data lines DL can also be supplied to the pixel PX of the supplied gate signal GS. The data drive circuit 150 can convert grayscale input image data from the controller 190 into a data signal DATA in the form of voltage or current.

[0149] The power supply circuit 170 can generate signals (voltage and current) suitable for driving pixels PX in pixel region 110 in response to a power drive control signal PCS from controller 190. When the display device 10 is an organic light-emitting display device, the power supply circuit 170 can generate a first power supply voltage ELVDD and a second power supply voltage ELVSS, and can supply them to the pixels PX. The first power supply voltage ELVDD can be a high-level voltage supplied to a terminal of a driving transistor connected to a first electrode (e.g., pixel electrode or anode) of an organic light-emitting diode included in the pixel PX. The second power supply voltage ELVSS can be a low-level voltage supplied to a second electrode (e.g., counter electrode or cathode) of the organic light-emitting diode. The first power supply voltage ELVDD and the second power supply voltage ELVSS can be driving voltages for the emission of light from multiple pixels PX.

[0150] The power supply circuit 170 can generate a first voltage VGH, a second voltage VGL, and a third voltage VGL2, and can supply them to the gate drive circuit 130. The power supply circuit 170 can generate multiple clock signals CLK1 and CLK2 (see...). Figure 3 ) and external signal FLM (see Figure 3 And it can be supplied to the gate drive circuit 130.

[0151] The controller 190 can generate a gate drive control signal GCS, a data drive control signal DCS, and a power drive control signal PCS based on signals input from an external source. The controller 190 can supply the gate drive control signal GCS to the gate drive circuit 130, the data drive control signal DCS to the data drive circuit 150, and the power drive control signal PCS to the power supply circuit 170.

[0152] Figure 9 The display device 10 independently includes a power supply circuit 170 and a controller 190, but this disclosure is not limited thereto. In one or more embodiments, the power supply circuit 170 may be included in the controller 190.

[0153] The display device 10 may include a display panel, and the display panel may include a substrate. Pixels PX may be arranged in the display area of ​​the substrate. In the process of forming transistors constituting pixel circuits in the display area of ​​the substrate, some or all of the gate drive circuits 130 may be directly formed in the peripheral area of ​​the substrate. The data drive circuit 150, power supply circuit 170, and controller 190 may be formed as separate integrated circuit chips or a single integrated circuit chip, and may be located above a flexible printed circuit board (FPCB) electrically connected to pads arranged on one side of the substrate. In other embodiments, the data drive circuit 150, power supply circuit 170, and controller 190 may be directly disposed above the substrate using a chip-on-glass (COG) or chip-on-plastic (COP) method.

[0154] The embodiments are not limited to the above-described stages, but can be applied to stages that include at least one N-channel oxide transistor.

[0155] In one embodiment, at least one N-channel oxide transistor included in the stage may be a four-terminal dual-gate transistor. The voltage applied to the back gate of the N-channel oxide transistor may be an AC voltage. In one or more embodiments, the voltage applied to the back gate of the N-channel oxide transistor may be a high-level voltage in some intervals of the frame and a low-level voltage in some other intervals of the frame.

[0156] For example, when a high-level voltage is applied to the gate of an N-channel oxidant transistor, the same high-level voltage can be applied to the back gate of the N-channel oxidant transistor. When a low-level voltage is applied to the gate of an N-channel oxidant transistor, a low-level voltage lower than the voltage applied to the gate can be applied to the back gate of the N-channel oxidant transistor.

[0157] The back gate of the N-channel oxide transistor can be connected to an AC voltage generation circuit. The AC voltage generation circuit may include a transistor (control transistor) and a capacitor (bootstrap capacitor), and the back gate of the N-channel oxide transistor can be connected to a node (control node) between the transistor and the capacitor. The capacitor of the AC voltage generation circuit can be connected between the control node and a terminal whose voltage level changes (e.g., the first output terminal GOUT, the second output terminal COUT, or the third output terminal COUT2), and the transistor can be turned off while the control node is bootstrapping.

[0158] In one or more embodiments, when the stage includes a plurality of N-channel oxide transistors, a carry-out circuit and an AC voltage generation circuit connected to the carry-out circuit may be added therein. The AC voltage generation circuit may include at least one control node whose voltage level changes during a frame, and the back gate of the N-channel oxide transistors may be connected to the control node.

[0159] According to an embodiment, by using nodes in the stage to apply AC voltage to the back gate of the oxide transistor, since no separate external circuitry is required to generate the AC voltage, a drive circuit capable of stably outputting an output signal and a display device including the drive circuit can be provided without increasing the area of ​​the peripheral region.

[0160] According to one or more embodiments, a drive circuit capable of stably outputting gate signals with low power while reducing the area of ​​the non-display area, and a display device including the drive circuit, can be provided. The aspects of this disclosure are not limited to the foregoing, and various extensions can be made without departing from the spirit of this disclosure.

[0161] It should be understood that the embodiments described herein should be considered for descriptive purposes only and not for limiting purposes. The description of aspects in each embodiment should typically be considered as applicable to other similar aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications in form and detail may be made thereto without departing from the spirit and scope as defined by the claims (the functional equivalents of which will be included therein).

Claims

1. A drive circuit comprising a stage, the stage comprising: a first output circuit configured to output an output signal and comprising a seventh transistor and an eighth transistor electrically connected between a first voltage input terminal for receiving a first voltage and a second voltage input terminal for receiving a second voltage lower than the first voltage; a second output circuit configured to output a carry signal and comprising a ninth transistor and a tenth transistor electrically connected between the first voltage input terminal and the second voltage input terminal; and a control circuit electrically connected to the first output circuit, the second output circuit, and an input terminal configured to receive a start signal, and the control circuit comprising: a fourth transistor comprising a gate electrically connected to a first node configured to receive the start signal and a back gate electrically connected to a third node, and electrically connected between the second voltage input terminal and a second node to which a gate of the eighth transistor is electrically connected; a fifth transistor electrically connected between the first node and the third node and comprising a gate electrically connected to the second voltage input terminal; and a second capacitor electrically connected to the third node and a second output node between the ninth transistor and the tenth transistor. when a voltage of the first node is at a high level, a voltage of the third node is at a high level equal to the high level of the voltage of the first node, and 2. The drive circuit of claim 1, wherein, wherein, when the voltage of the first node is at a low level, the voltage of the third node is at a low level lower than the low level of the voltage of the first node. the fourth transistor is an N-channel transistor and the fifth transistor is a P-channel transistor.

3. The drive circuit of claim 1, wherein, the fourth transistor is an oxide transistor and the fifth transistor is a silicon transistor.

4. The drive circuit of claim 3, wherein, the first output circuit further comprises a sixth transistor electrically connected between the second voltage input terminal and a first output node between the seventh transistor and the eighth transistor and comprising a gate electrically connected to the third node.

5. The drive circuit of claim 3, wherein, the control circuit further comprises:

6. The drive circuit of claim 1, wherein, a first transistor electrically connected between the input terminal and the first node and comprising a gate electrically connected to a first clock terminal configured to receive a first clock signal; and a second transistor electrically connected between the input terminal and the first node and comprising a gate electrically connected to a second clock terminal configured to receive a second clock signal, wherein the second transistor further comprises a back gate electrically connected to a third terminal configured to receive a third voltage lower than the second voltage, and wherein the second clock signal is an inverted signal of the first clock signal. the control circuit further comprises a third transistor electrically connected between the first voltage input terminal and the second node and comprising a gate electrically connected to the first node.

7. The drive circuit of claim 6, wherein, the eighth transistor comprises a back gate electrically connected to a third terminal configured to receive a third voltage lower than the second voltage, and 8. The drive circuit of claim 1, wherein, the second capacitor comprises a back gate electrically connected to a third terminal configured to receive a third voltage lower than the second voltage. The tenth transistor includes a back gate electrically connected to the third terminal.

9. The drive circuit according to claim 1, further comprising: a third output circuit including a thirteenth transistor and a fourteenth transistor electrically connected between the first voltage input terminal and the second voltage input terminal, and configured to output a second carry signal, wherein the second carry signal is at a low level when the carry signal is at a high level, and wherein the second carry signal is at a high level when the carry signal is at a low level.

10. The drive circuit of claim 9, wherein, The control circuit further includes: a twelfth transistor electrically connected between the second node and a fourth node, and including a gate electrically connected to the second voltage input terminal; and a third capacitor electrically connected to the fourth node and a third output node between the thirteenth transistor and the fourteenth transistor, wherein the eighth transistor includes a back gate electrically connected to the fourth node.

11. The drive circuit of claim 10, wherein, The voltage of the fourth node is at a high level equal to the high level of the voltage of the second node when the voltage of the second node is at the high level, and wherein the voltage of the fourth node is at a low level lower than the low level of the voltage of the second node when the voltage of the second node is at the low level.

12. A drive circuit including a stage, the stage including: a seventh transistor and an eighth transistor electrically connected between a first voltage input terminal configured to receive a first voltage and a second voltage input terminal configured to receive a second voltage lower than the first voltage, and configured to transmit an output signal to a first output terminal; a ninth transistor and a tenth transistor electrically connected between the first voltage input terminal and the second voltage input terminal, and configured to transmit a carry signal to a second output terminal; a first transistor electrically connected between a first node and an input terminal configured to receive a start signal, and including a gate configured to receive a clock signal; and a fourth transistor electrically connected between the second voltage input terminal and a second node to which a gate of the eighth transistor is electrically connected, and including a gate electrically connected to the first node and a back gate configured to receive an alternating voltage.

13. The drive circuit according to claim 12, further comprising: a fifth transistor electrically connected between the first node and a third node, and including a gate electrically connected to the second voltage input terminal; and a second capacitor electrically connected to the third node and the second output terminal, wherein the back gate of the fourth transistor is electrically connected to the third node, wherein the voltage of the third node is at a high level equal to the high level of the voltage of the first node when the voltage of the first node is at the high level, and wherein the voltage of the third node is at a low level lower than the low level of the voltage of the first node when the voltage of the first node is at the low level.

14. The drive circuit according to claim 13, further comprising: a sixth transistor electrically connected between the first output terminal and the second voltage input terminal, and including a gate electrically connected to the third node.

15. The drive circuit according to claim 12, further comprising: a thirteenth transistor and a fourteenth transistor electrically connected between the first voltage input terminal and the second voltage input terminal, and configured to transmit a second carry signal to a third output terminal; a twelfth transistor electrically connected between the second node and a fourth node, and including a gate electrically connected to the second voltage input terminal; and a third capacitor electrically connected to the fourth node and the third output terminal, wherein the eighth transistor includes a back gate electrically connected to the fourth node, wherein when a voltage of the second node is at a high level, a voltage of the fourth node is at a high level equal to the high level of the voltage of the second node, and wherein when the voltage of the second node is at a low level, the voltage of the fourth node is at a low level lower than the low level of the voltage of the second node.

Images