Capacitance equalization circuit
By dynamically adjusting the capacitor voltage through a capacitor balancing circuit, the problems of high failure rate and high power consumption of tantalum capacitors are solved, achieving effective protection and extended lifespan of the capacitors.
Patent Information
- Application Number
- CN202520387167.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-06
- Publication Date
- 2026-03-03
- Estimated Expiration
- 2035-03-06
AI Technical Summary
In existing technologies, tantalum capacitors have a high failure rate and cannot be effectively balanced, resulting in a shortened capacitor lifespan. Furthermore, when using a resistor voltage divider scheme, the power consumption is too high or cannot be balanced.
A capacitor equalization circuit is adopted, including a first capacitor bank, a second capacitor bank, a current sharing circuit, and a voltage divider circuit. By comparing the voltages across the capacitor banks, the voltage is dynamically adjusted to achieve equalization. Voltage regulation is achieved using a current sharing branch and a voltage divider branch composed of transistors and resistors.
This technology enables real-time dynamic adjustment of the capacitor, shortens the equalization time, reduces power consumption, effectively protects the capacitor, and extends its service life.
Smart Images
Figure CN223967654U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a capacitor equalization circuit, and more specifically, to a capacitor equalization circuit capable of dynamically adjusting the voltage of a capacitor. Background Technology
[0002] Currently, capacitors (such as tantalum capacitors) are commonly used as energy storage capacitors; for example, tantalum capacitors can be used as energy storage capacitors in MITOP (low-energy trip coils). However, tantalum capacitors have a higher failure rate compared to other capacitors, and they typically exhibit both open-circuit and short-circuit failure modes. To meet fail-safe requirements, a scheme of four tantalum capacitors connected in series and parallel is commonly used. To extend the lifespan of tantalum capacitors, a relatively average voltage needs to be achieved. Voltage equalization can be achieved by connecting two 100K resistors in parallel across the capacitors; however, with further increases in leakage current, a resistor divider scheme requires lower resistance values to achieve better results, leading to a significant increase in power consumption.
[0003] Using resistors for voltage equalization may fail to achieve equalization or result in excessive power consumption, making it unsuitable for practical applications. However, without equalization, tantalum capacitors will experience different voltages, causing the capacitors subjected to higher voltages to fail prematurely, leading to tripping issues.
[0004] Therefore, an effective capacitor equalization scheme is needed. Utility Model Content
[0005] This utility model relates to a capacitor equalization circuit, characterized in that it includes: a first capacitor bank, a first end of which is connected to a power supply and a second end of which is connected to a first node; a second capacitor bank, a first end of which is connected to the first node and a second end of which is connected to a reference ground; a current sharing circuit connected to the first node between the first capacitor bank and the second capacitor bank, and configured to adjust the first voltage and the second voltage based on a comparison between a first voltage across the first capacitor bank and a second voltage across the second capacitor bank; and a voltage divider circuit connected to the current sharing circuit and configured to control the operation of the current sharing circuit.
[0006] In one example, the current sharing circuit includes: a first current sharing branch connected between a power source and a first node and configured to turn on when a first voltage is higher than a second voltage to regulate the first voltage across a first capacitor bank; and a second current sharing branch connected between the first node and a reference ground and configured to turn on when a second voltage is higher than the first voltage to regulate the second voltage across a second capacitor bank.
[0007] In one example, the first current sharing branch includes: a first load resistor with a first end connected to a power supply; and a first transistor with its collector connected to a second end of the first load resistor, its emitter connected to a first node, and its base connected to a voltage divider circuit.
[0008] In one example, the second current sharing branch includes: a second load resistor with its second end connected to a reference ground; and a second transistor with its collector connected to the first end of the second load resistor, its emitter connected to the emitter of the first transistor, and its base connected to a voltage divider circuit.
[0009] In one example, the voltage divider circuit includes: a first voltage divider branch connected between a power supply and a reference ground, and configured to control the switching on and off of the first current sharing branch; and a second voltage divider branch connected between a power supply and a reference ground, and configured to control the switching on and off of the second current sharing branch.
[0010] In one example, the first voltage divider branch includes a first voltage divider resistor and a second voltage divider resistor connected in series, and a second node between the first voltage divider resistor and the second voltage divider resistor is connected to the base of the first transistor. The second voltage divider branch includes a third voltage divider resistor and a fourth voltage divider resistor connected in series, and a third node between the third voltage divider resistor and the fourth voltage divider resistor is connected to the base of the second transistor.
[0011] In one example, when the first voltage is higher than the second voltage, the first transistor turns on, the first voltage decreases, and the second voltage increases; and when the first voltage is lower than the second voltage, the second transistor turns on, the first voltage increases, and the second voltage decreases.
[0012] In one example, the first transistor is an NPN transistor, and the second transistor is a PNP transistor.
[0013] In one example, the voltage at the second node is the sum of half the supply voltage and the voltage drop across the emitter of the first transistor, and the voltage at the third node is the difference between half the supply voltage and the voltage drop across the emitter of the second transistor.
[0014] Therefore, the capacitor balancing circuit according to the present invention can dynamically adjust according to the voltage of the capacitor in real time, which is flexible in operation, has a large adjustable range, and has shorter balancing time and lower balancing power consumption. Therefore, it can more effectively protect the capacitor and extend the service life of the capacitor. Attached Figure Description
[0015] The above and other aspects, features, and advantages of specific embodiments of the present invention will become clearer from the following description taken in conjunction with the accompanying drawings, in which:
[0016] Figure 1 This is a schematic block diagram showing a capacitor equalization circuit according to an embodiment of the present invention;
[0017] Figure 2 A more detailed schematic block diagram of the capacitor equalization circuit according to an embodiment of the present invention is shown; and
[0018] Figure 3 A more detailed schematic circuit diagram of a capacitor equalization circuit according to an embodiment of the present invention is shown. Detailed Implementation
[0019] Before proceeding with the detailed description below, it may be advantageous to define certain words and phrases used throughout this invention. The terms “comprising” and “including” and their derivatives mean, but are not limited to, any of the following. The term “controller” or “control unit” means any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and / or firmware. For example, a controller may include, for instance, an application-specific integrated circuit (ASIC), a general-purpose or special-purpose central processing unit (CPU), a digital signal processor (DSP), and programmable logic devices such as a field-programmable gate array (FPGA). A controller may be manufactured as a single printed circuit board (PCB) or distributed across several interconnected PCBs. A controller may include other processing circuitry; for example, a controller may include two processing circuits such as an FPGA and a CPU interconnected on a PCB. The functionality associated with any particular controller may be centralized or distributed, either local or remote. The phrase “at least one,” when used with a list of items, means that different combinations of one or more of the listed items may be used, and perhaps only one item from the list is required. For example, "at least one of A, B, and C" includes any one of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C. Furthermore, in the description of this utility model, the terms "first," "second," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or order. In embodiments of this disclosure, unless otherwise expressly stated, "connection" does not necessarily mean "direct connection" or "direct contact," but only requires electrical connection.
[0020] Definitions of other specific words and phrases are provided throughout this invention. Those skilled in the art will understand that, in many, if not most, cases, such definitions apply to the prior and future use of the words and phrases thus defined.
[0021] The various embodiments of the present invention described below with reference to the accompanying drawings are for illustrative purposes only and should not be construed as limiting the scope of the present invention in any way. Those skilled in the art will understand that the principles of the present invention can be implemented in any suitably arranged system or device. In some cases, the actions described in the present invention can be performed in different orders and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific order or sequential sequence shown to achieve the desired result. In certain embodiments, multitasking and parallel processing may be advantageous.
[0022] The text and accompanying drawings are provided by way of example only to aid in understanding the present invention. They should not be construed as limiting the scope of the appended claims in any way. Although certain embodiments and examples have been provided, it will be clear to those skilled in the art, based on the content of the present invention, that changes can be made to the illustrated embodiments and examples without departing from the scope of the present invention.
[0023] Figure 1 This is a schematic block diagram showing a capacitor equalization circuit 100 according to an embodiment of the present invention.
[0024] like Figure 1 As shown, the capacitor equalization circuit 100 may include a first capacitor bank 101, a second capacitor bank 102, a current sharing circuit 103, and a voltage divider circuit 104.
[0025] A first terminal of the first capacitor bank 101 can be connected to a power source (not shown), and a second terminal of the first capacitor bank 101 can be connected to a first node P1. A first terminal of the second capacitor bank 102 can be connected to the first node P1, and a second terminal of the second capacitor bank 102 can be connected to a reference ground (not shown).
[0026] According to an example of the present invention, the first capacitor bank 101 and the second capacitor bank 102 may be connected in series, and the first capacitor bank 101 may include one or more capacitors connected in series and / or in parallel, and the second capacitor bank 102 may include one or more capacitors connected in series and / or in parallel, and the number of capacitors included in the first capacitor bank 101 may be the same as or different from the number of capacitors included in the second capacitor bank 102.
[0027] In addition, capacitors include, but are not limited to, tantalum capacitors.
[0028] The equivalent capacitance of one or more capacitors in the first capacitor bank 101 can be C1, and the equivalent capacitance of one or more capacitors in the second capacitor bank 102 can be C2.
[0029] The current sharing circuit 103 can be connected to a first node P1 between the first capacitor bank 101 and the second capacitor bank 102, and can be configured to adjust the first voltage and the second voltage based on a comparison between a first voltage across the first capacitor bank 101 and a second voltage across the second capacitor bank 102.
[0030] The voltage divider circuit 104 can be connected to the current sharing circuit 103 and can be configured to control the operation of the current sharing circuit 103.
[0031] Therefore, the capacitor balancing circuit according to the present invention can dynamically adjust according to the voltage of the capacitor in real time, which is flexible in operation, has a large adjustable range, and has shorter balancing time and lower balancing power consumption. Therefore, it can more effectively protect the capacitor and extend the service life of the capacitor.
[0032] Figure 2 A more detailed schematic block diagram of a capacitor equalization circuit 200 according to an embodiment of the present invention is shown.
[0033] exist Figure 2 The same or similar reference numerals are used to represent the same figures. Figure 1 Components with the same or similar functions and / or structures.
[0034] refer to Figure 1 and Figure 2 The current sharing circuit 103 may include: a first current sharing branch 1031, which may be connected between the power supply and the first node and can be configured to turn on when the first voltage is higher than the second voltage to adjust the first voltage across the first capacitor bank; and a second current sharing branch 1032, which may be connected between the first node and the reference ground and can be configured to turn on when the second voltage is higher than the first voltage to adjust the second voltage across the second capacitor bank.
[0035] The voltage divider circuit 104 may include: a first voltage divider branch 1041, which may be connected between the power supply and the reference ground, and can be configured to control the on and off of the first current sharing branch 1031; and a second voltage divider branch 1042, which may be connected between the power supply and the reference ground, and can be configured to control the on and off of the second current sharing branch 1032.
[0036] In addition, with Figure 1 Similarly, the first terminal of the first capacitor bank 101 can be connected to a power source, and the second terminal of the first capacitor bank 101 can be connected to a first node P1. The first terminal of the second capacitor bank 102 can be connected to the first node P1, and the second terminal of the second capacitor bank 102 can be connected to a reference ground.
[0037] Figure 3A more detailed schematic circuit diagram of a capacitor equalization circuit 300 according to an embodiment of the present invention is shown.
[0038] like Figure 3 As shown, the first capacitor C1 (or Figure 1 and Figure 2 The first terminal of the first capacitor C1 can be connected to a power source, and the second terminal of the first capacitor C1 can be connected to the first node P1. The second capacitor C2 (or...) Figure 1 and Figure 2 The first end of the first capacitor 102 can be connected to the first node P1, and the second end of the second capacitor 102 can be connected to the reference ground.
[0039] Figure 3 The first capacitor C1 shown may be the equivalent capacitance of the first capacitor bank 101, which includes one or more capacitors, and the second capacitor C2 may be the equivalent capacitance of the second capacitor bank 102, which includes one or more capacitors.
[0040] Figure 3 The power supply voltage shown is 18V; however, those skilled in the art will understand that this is merely an example.
[0041] Combination Figure 1 , Figure 2 and refer to Figure 3 The first current sharing branch 1031 may include: a first load resistor R1, the first end of which may be connected to a power supply; and a first transistor Q1, the collector of which may be connected to the second end of the first load resistor R1, the emitter of which may be connected to the first node P1, and the base of which may be connected to the voltage divider circuit 104.
[0042] The second current sharing branch 1032 may include: a second load resistor R2, the second end of which is connected to a reference ground; and a second transistor Q2, the collector of which may be connected to the first end of the second load resistor R1, the emitter of which may be connected to the emitter of the first transistor Q1, and the base of which may be connected to the voltage divider circuit 104.
[0043] In one example, the first voltage divider branch 1041 may include a first voltage divider resistor R3 and a second voltage divider resistor R4 connected in series, and the base of the first transistor Q1 may be connected to a second node P2 between the first voltage divider resistor R3 and the second voltage divider resistor R4.
[0044] The second voltage divider branch 1042 may include a third voltage divider resistor R5 and a fourth voltage divider resistor R6 connected in series, and the base of the second transistor Q2 may be connected to a third node P3 between the third voltage divider resistor R5 and the fourth voltage divider resistor R6.
[0045] In one example, the first transistor Q1 is an NPN transistor, and the second transistor Q2 is a PNP transistor. However, those skilled in the art will understand that the embodiments of this utility model are not limited thereto.
[0046] When the first voltage across the first capacitor C1 is higher than the second voltage across the second capacitor C2, the first transistor Q1 can be turned on. Current flows from the first terminal of the first capacitor C1, through the first current-sharing branch including the first load resistor R1 and the first transistor Q1, to the second capacitor C2, as shown by solid arrow ①. Therefore, the first voltage decreases and the second voltage increases, and the first and second voltages reach equilibrium.
[0047] When the second voltage across the second capacitor C2 is higher than the first voltage across the first capacitor C1, the second transistor Q2 can be turned on. Current flows from the first terminal of the second capacitor C2, through the second current-sharing branch including the second transistor Q2 and the second load resistor R2, to the reference ground, as shown by the dashed arrow ②. Therefore, the second voltage decreases, the first voltage increases, and the first and second voltages reach equilibrium.
[0048] When the first voltage across the first capacitor C1 is equal to the second voltage across the second capacitor C2, both the first transistor Q1 and the second transistor Q2 are cut off.
[0049] In one example, the voltage at the second node P2 can be the sum of half the power supply voltage and the voltage drop across the emitter of the first transistor Q1, and the voltage at the third node P3 can be the difference between half the power supply voltage and the voltage drop across the emitter of the second transistor Q2. Therefore, when the first voltage across the first capacitor C1 is higher than the second voltage across the second capacitor C2, the first transistor Q1 is turned on, and when the first voltage across the first capacitor C1 is lower than the second voltage across the second capacitor C2, the second transistor Q2 is turned on.
[0050] The voltage drop at the emitter of the first transistor Q1 and the voltage drop at the emitter of the second transistor Q2 can both be 0.6V.
[0051] The voltages at the second node P2 and the third node P3 can be set by configuring the resistance values of the first voltage divider resistor R3, the second voltage divider resistor R4, the third voltage divider resistor R5, and the fourth voltage divider resistor R6.
[0052] In addition, the voltages at the second node P2 and the third node P3 can be set based on the equivalent capacitance C1 of the first capacitor bank 101 and the equivalent capacitance C2 of the second capacitor bank 102.
[0053] The first transistor Q1 and the second transistor Q2 can obtain their corresponding equivalent resistances through feedback control. When the current difference is equal, both transistors Q1 and Q2 are turned off. The power consumption generated by Q1 and Q2 depends on the difference in leakage current between the first capacitor C1 and the second capacitor C2. That is to say, even if the leakage current of the first capacitor C1 and the second capacitor C2 is large, no additional balancing current power consumption will be generated when the leakage currents of the two capacitors are equal.
[0054] According to the embodiment of this utility model, the power consumption of the capacitor equalization circuit consists of the power consumption generated by the difference between the basic bias power consumption and the capacitor leakage current. If the leakage current of the two capacitors is equal, for example, both are 100μA, then the capacitor equalization circuit only needs to consume the basic bias power consumption, which significantly reduces the power consumption.
[0055] Furthermore, the capacitor balancing circuit according to this embodiment of the invention can be adjusted under different leakage current differences, such as 0 to 400μA. If a higher balancing capability is required, it is only necessary to adjust the power of the first load resistor R1 and the second load resistor R2, as well as the power of the first transistor Q1 and the second transistor Q2. The operation is flexible and simple.
[0056] According to an embodiment of this invention, when the leakage current difference between the capacitors is 0 to 1 mA, the voltage difference between the two capacitors can be controlled within a steady-state range of 0.1 V. If the leakage current difference between the capacitors is larger, equalization can be achieved simply by adjusting the circuit parameters.
[0057] Return to reference Figure 3 With a power supply voltage of 18V, the first load resistor R1 can be 20KΩ, the second load resistor R2 can be 10KΩ, the first voltage divider resistor R3 can be 425KΩ, the second voltage divider resistor R4 can be 510KΩ, the third voltage divider resistor R5 can be 510KΩ, and the fourth voltage divider resistor R6 can be 425KΩ. Therefore, considering the transistor voltage drop of approximately 0.6V, the voltage at the second node P2 can be set to approximately 9.6V, so that when the first voltage is higher than the second voltage, the first transistor Q1 can be turned on, and the voltage at the third node P3 can be set to approximately 8.3V, so that when the second voltage is higher than the first voltage, the second transistor Q2 can be turned on.
[0058] The resistance values of resistors R1 to R6 are merely examples. Those skilled in the art will understand that this invention is not limited to these, and the corresponding resistance values of each resistor can be selected according to the power supply voltage, leakage current, etc.
[0059] Therefore, the capacitor balancing circuit according to the present invention can dynamically adjust according to the voltage of the capacitor in real time, which is flexible in operation, has a large adjustable range, and has shorter balancing time and lower balancing power consumption. Therefore, it can more effectively protect the capacitor and extend the service life of the capacitor.
[0060] Although the present invention has been described with reference to exemplary embodiments, various changes and modifications may be suggested to those skilled in the art. The present invention is intended to cover such changes and modifications that fall within the scope of the appended claims.
[0061] Any description in this invention should not be construed as implying that any particular element, step, or function is an essential element that must be included within the scope of the claims. The scope of the patent subject matter is defined only by the claims.
Claims
1. A capacitance equalization circuit, characterized by, comprises: a first capacitor bank having a first end connected to a power supply and a second end connected to a first node; a second capacitor bank having a first end connected to the first node and a second end connected to a reference ground; a current sharing circuit connected to the first node between the first capacitor bank and the second capacitor bank and configured to regulate a first voltage across the first capacitor bank and a second voltage across the second capacitor bank based on a comparison between the first voltage and the second voltage; and a voltage dividing circuit connected to the current sharing circuit and configured to control operation of the current sharing circuit. The current sharing circuit comprises:
2. The capacitance equalization circuit of claim 1, wherein, a first current sharing branch connected between the power supply and the first node and configured to turn on when the first voltage is higher than the second voltage to regulate the first voltage across the first capacitor bank; and a second current sharing branch connected between the first node and the reference ground and configured to turn on when the second voltage is higher than the first voltage to regulate the second voltage across the second capacitor bank. The first current sharing branch comprises:
3. The capacitance equalization circuit of claim 2, wherein, a first load resistor having a first end connected to the power supply; and a first transistor having a collector connected to a second end of the first load resistor, an emitter connected to the first node, and a base connected to the voltage dividing circuit. The second current sharing branch comprises:
4. The capacitance equalization circuit of claim 3, wherein, a second load resistor having a second end connected to the reference ground; and a second transistor having a collector connected to a first end of the second load resistor, an emitter connected to the emitter of the first transistor, and a base connected to the voltage dividing circuit. The voltage dividing circuit comprises:
5. The capacitance equalization circuit of claim 4, wherein, a first voltage dividing branch connected between the power supply and the reference ground and configured to control turning on and off of the first current sharing branch; and a second voltage dividing branch connected between the power supply and the reference ground and configured to control turning on and off of the second current sharing branch. The first voltage dividing branch comprises a first voltage dividing resistor and a second voltage dividing resistor connected in series, and a second node between the first voltage dividing resistor and the second voltage dividing resistor is connected to the base of the first transistor, and 6. The capacitance equalization circuit of claim 5, wherein, The second voltage dividing branch comprises a third voltage dividing resistor and a fourth voltage dividing resistor connected in series, and a third node between the third voltage dividing resistor and the fourth voltage dividing resistor is connected to the base of the second transistor. When the first voltage is higher than the second voltage, the first transistor turns on, the first voltage drops, and the second voltage rises; and 7. The capacitance equalization circuit of claim 4, wherein, When the first voltage is lower than the second voltage, the second transistor turns on, the first voltage rises, and the second voltage drops. The first transistor is an NPN transistor and the second transistor is a PNP transistor.
8. The capacitance equalization circuit of claim 4, wherein, A voltage at the second node is a sum of half of the power supply voltage and a voltage drop of the first transistor at the emitter of the first transistor, and 9. The capacitance equalization circuit of claim 6, wherein, A voltage at the third node is a difference of half of the power supply voltage and a voltage drop of the second transistor at the emitter of the second transistor. The first capacitor bank comprises one or more capacitors, and the second capacitor bank comprises one or more capacitors.
10. The capacitance equalization circuit of claim 1, wherein,